WO2004098055A1

WO2004098055A1 - Oscillator assembly and method for producing a multi-frequency output signal

Info

Publication number: WO2004098055A1
Application number: PCT/DE2004/000114
Authority: WO
Inventors: Peter Busch
Original assignee: Fujitsu Siemens Computers Gmbh
Priority date: 2003-04-30
Filing date: 2004-01-26
Publication date: 2004-11-11
Also published as: DE10319556B3

Abstract

The invention relates to an oscillator assembly comprising a voltage-controlled oscillator (1) which is provided with the oscillator output (2) and produces an output time variable voltage (Vosz) and a frequency multiplier circuit (3) arranged thereafter. The inventive oscillator assembly is characterised in that the frequency multiplier circuit (3) comprises a voltage divider (4) which is provided with at least one tap and produces a reference voltage and at least one comparator (5, 6, 7, 8) associated with the tap. The first comparator(s) (5, 6, 7, 8) input is connected to the tap, another input being connected to the output of the oscillator (2). Said invention also relates to a method for producing an output signal (Vaus) with a second frequency which is multiple of the first frequency of the input sawtooth signal (Vosz) or the like, several threshold values being determined and successively attained by said input signal (Vosz) and an output impulse being produced when the threshold value is attained.

Description

description

Oscillator arrangement and method for generating a frequency-multiplied output signal

The invention relates to an oscillator arrangement with a voltage-controlled oscillator having an oscillator output for generating a time-variable output voltage and a downstream frequency multiplier circuit. In addition, the invention relates to a method for generating an output signal of a second frequency which is a multiple of a first frequency of a sawtooth-shaped or sawtooth-like input signal.

Control loops, which, for example, should keep a variable speed of a motor constant, often use the frequency of a voltage-controlled oscillator (VCO) in the order of a few kilohertz as a reference variable for the target speed. If this voltage-controlled oscillator of the "555" type, which is an industry standard, is implemented with an external capacitor and an external charging resistor, the frequency can be varied by varying a control voltage. Regarding the frequency tolerance, this sawtooth voltage is very exact if the discharge time of the capacitor is chosen to be very small due to a very small value of an end-of-charge resistor, so that the charging time of the capacitor dominates over the charging resistor for the total period. Operating voltage tolerances have hardly any influence on the frequency. Such an oscillator circuit according to the prior art is shown in FIG. 4. The external capacitor is labeled C ^, the external charge resistor R ^ and the discharge resistor Rcj. The control voltage, which is designated V _con ^ - _ro j_, is determined via an adjustable resistor Rcontrol. The independence of the frequency from operating voltage tolerances is due to the fact that the charging time essentially depends only on the the divider ratios R _max and Rcontrol and the frequency-determining components C ^ and R ^ is determined.

Additional signals with a frequency that is to be a multiple of the oscillator frequency are often required. Although the frequency of the oscillator could be increased from the outset and the other, lower frequencies generated by a divider circuit, there is the problem that an increase in the frequency of the voltage-controlled oscillator causes circuit-technical difficulties, since the switching process from discharge to charge has to proceed ever faster and so the parasitic effects such as switching delays and excessive oscillator voltage increase more and more.

It is known from the prior art to trigger a monoflop with half the length of the input frequency period in order to generate a frequency-multiplied signal with the output pulses of the oscillator and then to trigger another monoflop with both the positive and the negative edge of this monoflop , which has a correspondingly shorter period. This results in a frequency doubling. However, due to the fixed period of the monoflops, this method is not suitable for a signal with a variable frequency, as is generated by a voltage-controlled oscillator.

For this reason, so-called PLL circuits (phase locked loops) are frequently used, which can also be used to multiply the frequency. Such circuits consist of a voltage-controlled oscillator, a digital divider with the desired multiplication factor and a digital phase comparison circuit, which in turn controls the voltage-controlled oscillator via a suitable compensation at the output. This gives the desired multiplied frequency at the output of this voltage controlled oscillator. This method is suitable for a variable Input frequency, but is relatively complex and usually requires an external capacitor, which should be avoided in the usual implementation of such a circuit in integrated circuits.

The object of the invention is to provide an oscillator arrangement or a method for generating a frequency-multiplied output signal, so that an oscillator can be of simple construction and nevertheless delivers a frequency-multiplied output signal at a variable frequency.

This object is achieved by an oscillator arrangement of the type mentioned at the outset, which is characterized in that the frequency multiplier circuit has a voltage divider with at least one tap for generating comparative voltages and at least one comparator, which is assigned to a tap, a first input of the comparator (s) is connected to a tap and the other input is connected to the oscillator output.

By means of the additional circuit according to the invention, a plurality of switching thresholds in the form of comparison voltages are established by the voltage divider, which are achieved in succession by the output signal of the oscillator, so that the comparators switch over in succession and output a corresponding output signal. Staggered pulses are thus generated.

In an advantageous embodiment of the oscillator arrangement according to the invention, it is a resistive voltage divider. In addition, it is advantageous to connect edge-triggered monoflops to the comparators, which form a pulse after the outputs of the comparators have switched. It is particularly favorable if the voltage divider is connected between a node of the oscillator that determines the maximum voltage of the oscillator output signal and a second node of the oscillator that determines the minimum value of the oscillator output voltage during operation.

Further advantageous embodiments of the invention are specified in the subclaims.

The invention is explained in more detail below using an exemplary embodiment. Show it:

FIG. 1 shows an exemplary embodiment of an oscillator arrangement according to the invention,

FIG. 2 shows a diagram with the oscillator output voltage,

3 shows a second diagram with the oscillator output voltage and the output signal of the frequency multiplier circuit and

Figure 4 shows an oscillator arrangement from the prior art.

In the upper part of FIG. 1, an oscillator 1 is shown, as is known from the prior art (cf. FIG. 4). The oscillator is connected to an operating voltage VDD. The oscillator 1, a control voltage V _con _ro t] _ is supplied, that is, for example, picked up at an adjustable resistor ^R control. The control voltage V _con trol is supplied to the non-inverting input of a first comparator. 13 A second comparator 14 is also provided, the inverting input of which is supplied with a voltage V _max . The voltage V _raax is generated by a voltage divider. An oscillator _output voltage V _osz varies between the maximum voltage V _max and the control voltage V _con t _ro _. The outputs of the comparators 13 and 14 are connected to the reset or set input of a flip-flop 15. The control terminal of a transistor 16 is connected to an output Q of the flip-flop 15 and is connected between ground and a discharge resistor R ^. The discharge resistor R ^ connects the external capacitor C ^ already mentioned via the transistor 16 to ground. The capacitor connection simultaneously forms an oscillator _output , from which the oscillator _output voltage V _{osz can be} tapped. The oscillator output is also connected to the inverting input of the first comparator 13 and the non-inverting input of the comparator 14.

In operation, this circuit works as follows: It is assumed that the transistor 16 is initially high-resistance. In this operating state, the capacitor C ^ is charged via a charging resistor Rt. The rising voltage across the capacitor C ^ is also present at the non-inverting input of the comparator 14. When the switching threshold of the comparator 14 predetermined by V _{max is reached} , it switches over and thus generates a set signal for the flip-flop 15. The flip-flop then jumps to a logic "1" and thus controls the transistor 16 in a conductive manner. This closes the current path between the capacitor C ^ and ground, so that the capacitor C ^ is discharged. The falling voltage across the capacitor Cj- is also present at the inverting input of the first comparator 13. If the control voltage falls below

defined switching threshold, the output of the comparator 13 jumps to a logic "1" and resets the flip-flip 15. The output of the

Flip-flops 15 to a logic "0" and the transistor 16 blocks, so that the discharge process of the capacitor C ^ is interrupted and the process begins again. The oscillator _{output voltage} V _osz at the oscillator _output 2 therefore always varies between the voltages V _max and the control voltage V _con t _ro ] _, since these define the switching thresholds of the comparators 13 and 14. The generated oscillator _{output voltage} V _osz is shown in FIG. 2. From this it can be seen that the occurring maximum value of the oscillator _output voltage V _{osz is} determined by the voltage V _rrιax . The minimum value is determined occurring trol by the control voltage V _con, which voltage is in contrast to the maximum voltage V _max is variable and depends on the set frequency.

Between node 9 and 10 of the oscillator 1, wherein at node 9, the maximum voltage V _max and at node 10, the control voltage V _con t _ro] _ is applied, is a resistive voltage divider 4 with resistors Rl, R2, R3, connected in R4 and R5. The voltage divider 4 is dimensioned such that it ^only insignificantly loads the voltages ^v max ^and d ^v control. If necessary, the voltages V _max and V _con trol must be buffered. A tap is provided between the resistors, which are connected to comparators 5, 6, 7 and 8. The voltages tapped at the voltage divider 4 are each fed to the inverting input of the comparators 5, 6, 7 and 8.

The oscillator _{output voltage} V _ogz is _fed from the oscillator output 2 to the non-inverting inputs of the comparators 5, 6, 7 and 8, respectively. Since different switching thresholds are defined by the different tapped comparison _voltages at the inverting inputs of the comparators, the comparators will _respond one after the other with increasing oscillator _{output voltage} V _osz and jump from "0" to "1".

The different switching thresholds are shown in the diagram in FIG. 3. The resistors R1..R5 are dimensioned so that the times at which the next comparator switches are evenly distributed on the time axis. It is taken into account that the oscillator output voltage behaves according to an e-function. With a ner another form of the oscillator _output voltage V _osz , the resistors of the voltage divider 4 would also have to be dimensioned in an adapted manner.

The outputs of the comparators 5, 6, 7 and 8 each trigger edge-triggered monoflops 11 of a short period. The period must be chosen so short that there is no overlap between the output pulses of the monoflops even at the maximum intended output frequency of the oscillator arrangement. The output pulses of the monoflops 11 are combined via an OR gate 12 to form a common output signal V _out , the four-fold frequency compared to the frequency of the oscillator _{output voltage} V _osz being obtained in the exemplary embodiment shown with four comparators.

The oscillator arrangement shown also operates at variable voltage values of the control voltage _con t _ROJ _ since the reference voltages generated by the voltage divider 4 are mitvariiert with this signal. This is achieved in that the voltage divider 4 is connected between the voltage V _max and the control voltage V _con t _ro l. In principle, the oscillator arrangement works with arbitrarily short output pulses of the monoflops 11. Short output pulses only require small capacitors, which have the design of an integrated one

Circuit can be provided. The effort is considerably less than with a PLL circuit from the prior art. LIST OF REFERENCE NUMBERS

1 oscillator

2 oscillator output

3 frequency multiplier circuit

4 voltage dividers

5, 6, 7, 8 comparators

9 first knot

10 second knots

11 monoflops

12 OR gates

13 first comparator

14 second comparator

15 flip-flops

16 transistor

VDD operating voltage

^ ma maximum voltage ^v control control voltage ^v osz oscillator output voltage ^v from output voltage

* d discharge resistance

Rt charging resistance

Rl ... R5 resistors of the voltage divider 4

^C t capacitor

Claims

claims

1. Oscillator arrangement with an oscillator output (2) having a voltage-controlled oscillator (1) for generating a time-varying output voltage (V _osz ) and a downstream frequency multiplier circuit (3), characterized in that the frequency multiplier circuit (3) - a voltage divider (4) with at least one tap for generating reference voltages and - has at least one comparator (5, 6, 7, 8), which is assigned to each tap, a first input of the comparator (s) (5, 6, 7 , 8) is connected to a tap and the other input is connected to the oscillator output (2).

2. oscillator arrangement according to claim 1, characterized in that the voltage across the voltage divider (4) of the difference between the maximum (V _max) and minimum (V _con trol) i ⁿ the oscillator output voltage (V _osz) occurring voltage.

3. Oscillator arrangement according to claim 2, characterized in that the voltage divider (4) is connected on the one hand to a first node (9) of the oscillator (1) which determines the maximum value (V _max ) of the oscillator _{output voltage} (V _osz ) during operation and on the other hand is connected to a second node (10) of the oscillator (1), which in operation has the minimum value

the oscillator _{output voltage} (v _osz ).

4. Oscillator arrangement according to one of claims 1 to 3, d a d u r c h g e k e n n z e i c h n e t that the voltage divider (4) is a resistive voltage divider.

5. Oscillator arrangement according to claim 4, so that the resistors (R1..R5) of the resistive voltage divider (4) are dimensioned such that the oscillator output voltage is in connection with a predetermined curve shape

(V _osz ) equidistant switching thresholds of the comparators

(5, 6, 7, 8).

6. Oscillator arrangement according to one of claims 1 to 5, d a d u r c h g e k e n n z e i c h n e t that the comparators (5, 6, 7, 8) monoflops (11) are connected downstream.

7. Oscillator arrangement according to claim 6, so that the outputs of the monoflops (11) are connected with an OR link (12).

8. Method for generating an output signal (V _out ) with a second frequency which is a multiple of a first frequency of a sawtooth-shaped or sawtooth-like input signal (V _osz ), characterized in that several threshold values are defined which are determined by the input signal ( V _osz ) can be achieved one after the other and an output pulse is generated when a threshold value is reached.