WO2004099978A3 - Apparatus and method to identify data-speculative operations in microprocessor - Google Patents

Apparatus and method to identify data-speculative operations in microprocessor Download PDF

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Publication number
WO2004099978A3
WO2004099978A3 PCT/US2004/000483 US2004000483W WO2004099978A3 WO 2004099978 A3 WO2004099978 A3 WO 2004099978A3 US 2004000483 W US2004000483 W US 2004000483W WO 2004099978 A3 WO2004099978 A3 WO 2004099978A3
Authority
WO
WIPO (PCT)
Prior art keywords
speculation
microprocessor
data speculation
operations
data
Prior art date
Application number
PCT/US2004/000483
Other languages
French (fr)
Other versions
WO2004099978A2 (en
Inventor
Michael A Filippo
James K Pickett
Benjamin T Sander
Original Assignee
Advanced Micro Devices Inc
Michael A Filippo
James K Pickett
Benjamin T Sander
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc, Michael A Filippo, James K Pickett, Benjamin T Sander filed Critical Advanced Micro Devices Inc
Priority to GB0521335A priority Critical patent/GB2418045B/en
Priority to DE112004000741T priority patent/DE112004000741B4/en
Priority to JP2006508587A priority patent/JP4745960B2/en
Priority to KR1020057020786A priority patent/KR101057163B1/en
Publication of WO2004099978A2 publication Critical patent/WO2004099978A2/en
Publication of WO2004099978A3 publication Critical patent/WO2004099978A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G06F9/3844—Speculative instruction execution using dynamic branch prediction, e.g. using branch history tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3824—Operand accessing
    • G06F9/383—Operand prefetching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3856—Reordering of instructions, e.g. using queues or age tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3854—Instruction completion, e.g. retiring, committing or graduating
    • G06F9/3858—Result writeback, i.e. updating the architectural state or memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3865—Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags

Abstract

A microprocessor (100) may include a retire queue (102) and one or more data speculation verification units. The data speculation verification units are each configured to verify data speculation performed on operations. Each data speculation verification unit generates a respective speculation pointer identifying outstanding operations on which data speculation has been verified by that data speculation verification unit. The retire queue (102) is configured to selectively retire operations dependent on the speculation pointer received from each of the data speculation verification units.
PCT/US2004/000483 2003-05-02 2004-01-09 Apparatus and method to identify data-speculative operations in microprocessor WO2004099978A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB0521335A GB2418045B (en) 2003-05-02 2004-01-09 Speculation pointers to identify data-speculative operations in microprocessor
DE112004000741T DE112004000741B4 (en) 2003-05-02 2004-01-09 Speculation pointer for identifying data-speculative operations in a microprocessor
JP2006508587A JP4745960B2 (en) 2003-05-02 2004-01-09 A speculative pointer that identifies data speculative operations in a microprocessor
KR1020057020786A KR101057163B1 (en) 2003-05-02 2004-01-09 Inference Pointers to Identify Data-Inference Operations in a Microprocessor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/429,159 US7266673B2 (en) 2003-05-02 2003-05-02 Speculation pointers to identify data-speculative operations in microprocessor
US10/429,159 2003-05-02

Publications (2)

Publication Number Publication Date
WO2004099978A2 WO2004099978A2 (en) 2004-11-18
WO2004099978A3 true WO2004099978A3 (en) 2005-12-08

Family

ID=33310560

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/000483 WO2004099978A2 (en) 2003-05-02 2004-01-09 Apparatus and method to identify data-speculative operations in microprocessor

Country Status (8)

Country Link
US (1) US7266673B2 (en)
JP (1) JP4745960B2 (en)
KR (1) KR101057163B1 (en)
CN (1) CN100373330C (en)
DE (1) DE112004000741B4 (en)
GB (1) GB2418045B (en)
TW (1) TWI318371B (en)
WO (1) WO2004099978A2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7721054B2 (en) * 2005-01-18 2010-05-18 Texas Instruments Incorporated Speculative data loading using circular addressing or simulated circular addressing
US8595557B2 (en) * 2005-02-23 2013-11-26 International Business Machines Corporation Method and apparatus for verifying memory testing software
US7921280B2 (en) * 2008-06-27 2011-04-05 Intel Corporation Selectively powered retirement unit using a partitioned allocation array and a partitioned writeback array
US8880854B2 (en) * 2009-02-11 2014-11-04 Via Technologies, Inc. Out-of-order execution microprocessor that speculatively executes dependent memory access instructions by predicting no value change by older instructions that load a segment register
US8707015B2 (en) 2010-07-01 2014-04-22 Advanced Micro Devices, Inc. Reclaiming physical registers renamed as microcode architectural registers to be available for renaming as instruction set architectural registers based on an active status indicator
US8589892B2 (en) 2010-11-21 2013-11-19 International Business Machines Corporation Verification of speculative execution
US8745599B2 (en) * 2012-01-19 2014-06-03 National Tsing Hua University Probabilistic pointer analysis method using SSA form
US10776123B2 (en) 2018-12-03 2020-09-15 Advanced Micro Devices, Inc. Faster sparse flush recovery by creating groups that are marked based on an instruction type
CN112559048B (en) * 2019-09-25 2023-12-12 阿里巴巴集团控股有限公司 Instruction processing device, processor and processing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5781752A (en) * 1996-12-26 1998-07-14 Wisconsin Alumni Research Foundation Table based data speculation circuit for parallel processing computer
WO2001061480A1 (en) * 2000-02-14 2001-08-23 Intel Corporation Processor having replay architecture with fast and slow replay paths
WO2002042902A2 (en) * 2000-11-02 2002-05-30 Intel Corporation Method and apparatus for scheduling multiple micro-operations in a processor

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US5740393A (en) * 1993-10-15 1998-04-14 Intel Corporation Instruction pointer limits in processor that performs speculative out-of-order instruction execution
US5903741A (en) * 1995-01-25 1999-05-11 Advanced Micro Devices, Inc. Method of allocating a fixed reorder buffer storage line for execution results regardless of a number of concurrently dispatched instructions
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US6665792B1 (en) * 1996-11-13 2003-12-16 Intel Corporation Interface to a memory system for a processor having a replay system
US6735688B1 (en) 1996-11-13 2004-05-11 Intel Corporation Processor having replay architecture with fast and slow replay paths
US6212626B1 (en) 1996-11-13 2001-04-03 Intel Corporation Computer processor having a checker
US6381691B1 (en) * 1999-08-13 2002-04-30 International Business Machines Corporation Method and apparatus for reordering memory operations along multiple execution paths in a processor
WO2003001369A2 (en) 2001-06-26 2003-01-03 Sun Microsystems, Inc. Method and apparatus for facilitating speculative stores in a multiprocessor system
AU2002367955A1 (en) 2001-06-26 2004-01-06 Sun Microsystems, Inc. Method and apparatus for facilitating speculative loads in a multiprocessor system
US6952764B2 (en) 2001-12-31 2005-10-04 Intel Corporation Stopping replay tornadoes
US7363470B2 (en) 2003-05-02 2008-04-22 Advanced Micro Devices, Inc. System and method to prevent in-flight instances of operations from disrupting operation replay within a data-speculative microprocessor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5781752A (en) * 1996-12-26 1998-07-14 Wisconsin Alumni Research Foundation Table based data speculation circuit for parallel processing computer
WO2001061480A1 (en) * 2000-02-14 2001-08-23 Intel Corporation Processor having replay architecture with fast and slow replay paths
WO2002042902A2 (en) * 2000-11-02 2002-05-30 Intel Corporation Method and apparatus for scheduling multiple micro-operations in a processor

Also Published As

Publication number Publication date
GB2418045A (en) 2006-03-15
KR101057163B1 (en) 2011-08-17
US7266673B2 (en) 2007-09-04
TW200502849A (en) 2005-01-16
GB0521335D0 (en) 2005-11-30
GB2418045B (en) 2007-02-28
DE112004000741T5 (en) 2006-05-11
KR20060004974A (en) 2006-01-16
CN100373330C (en) 2008-03-05
DE112004000741B4 (en) 2008-02-14
CN1784654A (en) 2006-06-07
US20040221140A1 (en) 2004-11-04
TWI318371B (en) 2009-12-11
WO2004099978A2 (en) 2004-11-18
JP2006525595A (en) 2006-11-09
JP4745960B2 (en) 2011-08-10

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