WO2004107201A3 - Processing architecture for a reconfigurable arithmetic node in an adaptive computing system - Google Patents
Processing architecture for a reconfigurable arithmetic node in an adaptive computing system Download PDFInfo
- Publication number
- WO2004107201A3 WO2004107201A3 PCT/US2003/037225 US0337225W WO2004107201A3 WO 2004107201 A3 WO2004107201 A3 WO 2004107201A3 US 0337225 W US0337225 W US 0337225W WO 2004107201 A3 WO2004107201 A3 WO 2004107201A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- node
- computing system
- fir filter
- processing architecture
- adaptive computing
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
Abstract
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU2003295744A AU2003295744A1 (en) | 2003-05-21 | 2003-11-19 | Processing architecture for a reconfigurable arithmetic node in an adaptive computing system |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/443,596 US7433909B2 (en) | 2002-06-25 | 2003-05-21 | Processing architecture for a reconfigurable arithmetic node |
US10/443,596 | 2003-05-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2004107201A2 WO2004107201A2 (en) | 2004-12-09 |
WO2004107201A3 true WO2004107201A3 (en) | 2005-04-21 |
Family
ID=33489338
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2003/037225 WO2004107201A2 (en) | 2003-05-21 | 2003-11-19 | Processing architecture for a reconfigurable arithmetic node in an adaptive computing system |
Country Status (3)
Country | Link |
---|---|
US (1) | US7433909B2 (en) |
AU (1) | AU2003295744A1 (en) |
WO (1) | WO2004107201A2 (en) |
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2003
- 2003-05-21 US US10/443,596 patent/US7433909B2/en active Active
- 2003-11-19 WO PCT/US2003/037225 patent/WO2004107201A2/en active Application Filing
- 2003-11-19 AU AU2003295744A patent/AU2003295744A1/en not_active Abandoned
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Also Published As
Publication number | Publication date |
---|---|
US20040030736A1 (en) | 2004-02-12 |
AU2003295744A1 (en) | 2005-01-21 |
US7433909B2 (en) | 2008-10-07 |
WO2004107201A2 (en) | 2004-12-09 |
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