WO2005004195A3 - Method and apparatus for packaging integrated circuit devices - Google Patents

Method and apparatus for packaging integrated circuit devices Download PDF

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Publication number
WO2005004195A3
WO2005004195A3 PCT/IL2004/000589 IL2004000589W WO2005004195A3 WO 2005004195 A3 WO2005004195 A3 WO 2005004195A3 IL 2004000589 W IL2004000589 W IL 2004000589W WO 2005004195 A3 WO2005004195 A3 WO 2005004195A3
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WO
WIPO (PCT)
Prior art keywords
generally planar
planar surface
integrated circuit
formed over
circuit devices
Prior art date
Application number
PCT/IL2004/000589
Other languages
French (fr)
Other versions
WO2005004195A2 (en
Inventor
Gil Zilber
Julia Aksenton
Vage Oganesian
Original Assignee
Shellcase Ltd
Gil Zilber
Julia Aksenton
Vage Oganesian
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Filing date
Publication date
Application filed by Shellcase Ltd, Gil Zilber, Julia Aksenton, Vage Oganesian filed Critical Shellcase Ltd
Priority to JP2006518485A priority Critical patent/JP2007528120A/en
Publication of WO2005004195A2 publication Critical patent/WO2005004195A2/en
Publication of WO2005004195A3 publication Critical patent/WO2005004195A3/en

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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/01—Chemical elements
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01—Chemical elements
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    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

An integrally packaged integrated circuit device including an integrated circuit die including a crystalline substrate having first and second generally planar surfaces and edge surfaces and semiconductor circuitry formed over the first generally planar surface, at least one chip scale packaging layer formed over the semiconductor circuitry and the first generally planar surface, an insulation layer formed over the second generally planar surface and the edge surfaces and at least one electrical conductor formed directly on the insulation layer overlying the second generally planar surface, the at least one electrical conductor being connected to the circuitry by at least one pad formed directly on the first generally planar surface.
PCT/IL2004/000589 2003-07-03 2004-07-01 Method and apparatus for packaging integrated circuit devices WO2005004195A2 (en)

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