WO2005027194A3 - Method of making nonvolatile transistor pairs with shared control gate - Google Patents

Method of making nonvolatile transistor pairs with shared control gate Download PDF

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Publication number
WO2005027194A3
WO2005027194A3 PCT/US2004/028422 US2004028422W WO2005027194A3 WO 2005027194 A3 WO2005027194 A3 WO 2005027194A3 US 2004028422 W US2004028422 W US 2004028422W WO 2005027194 A3 WO2005027194 A3 WO 2005027194A3
Authority
WO
WIPO (PCT)
Prior art keywords
poly
remnants
floating gate
pair
transistors
Prior art date
Application number
PCT/US2004/028422
Other languages
French (fr)
Other versions
WO2005027194A2 (en
Inventor
Bohumil Lojek
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Priority to EP04782838A priority Critical patent/EP1665356A2/en
Publication of WO2005027194A2 publication Critical patent/WO2005027194A2/en
Publication of WO2005027194A3 publication Critical patent/WO2005027194A3/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors

Abstract

A pair of nonvolatile memory transistors are carved from a single polysilicon floating gate (23) on an insulated substrate (11). After surrounding the poly floating gate with insulator, the poly is etched except for two remnants (21a, 21b) remaining on lateral sides of the original floating gate. These remnants become a pair of new floating gates for the transistor pair. Prior to etching of the poly (23), the poly may be used for self-aligned placement of highly doped regions (35, 37) that serve as electrodes for the two transistors. If the single poly floating gate has a minimum feature size for a manufacturing process, the pair of poly remnants (21a, 21b) remaining after etching are even smaller, perhaps less than a fraction of the minimum feature size. With this small size, the devices will operate by band-to-band tunneling, i.e. without tunnel oxide, characteristic of larger EEPROM and EPROM devices. A single conductive control electrode (53) over the poly remnants can allow both transistors to operate as independent storage devices if bit lines (83, 85), connected to other electrodes, are phased.
PCT/US2004/028422 2003-09-04 2004-09-01 Method of making nonvolatile transistor pairs with shared control gate WO2005027194A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP04782838A EP1665356A2 (en) 2003-09-04 2004-09-01 Method of making nonvolatile transistor pairs with shared control gate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/656,071 2003-09-04
US10/656,071 US6905926B2 (en) 2003-09-04 2003-09-04 Method of making nonvolatile transistor pairs with shared control gate

Publications (2)

Publication Number Publication Date
WO2005027194A2 WO2005027194A2 (en) 2005-03-24
WO2005027194A3 true WO2005027194A3 (en) 2005-05-19

Family

ID=34226274

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/028422 WO2005027194A2 (en) 2003-09-04 2004-09-01 Method of making nonvolatile transistor pairs with shared control gate

Country Status (5)

Country Link
US (2) US6905926B2 (en)
EP (1) EP1665356A2 (en)
CN (1) CN1875468A (en)
TW (1) TW200520105A (en)
WO (1) WO2005027194A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050239250A1 (en) * 2003-08-11 2005-10-27 Bohumil Lojek Ultra dense non-volatile memory array
US6905926B2 (en) * 2003-09-04 2005-06-14 Atmel Corporation Method of making nonvolatile transistor pairs with shared control gate
US7554151B2 (en) * 2005-11-03 2009-06-30 Atmel Corporation Low voltage non-volatile memory cell with electrically transparent control gate
US20070166971A1 (en) * 2006-01-17 2007-07-19 Atmel Corporation Manufacturing of silicon structures smaller than optical resolution limits
US7439567B2 (en) * 2006-08-09 2008-10-21 Atmel Corporation Contactless nonvolatile memory array
US20080116447A1 (en) * 2006-11-20 2008-05-22 Atmel Corporation Non-volatile memory transistor with quantum well charge trap
US7494870B2 (en) * 2007-01-12 2009-02-24 Sandisk Corporation Methods of forming NAND memory with virtual channel
KR101518332B1 (en) * 2008-12-01 2015-05-08 삼성전자주식회사 Manufacturing method of semiconductor apparatus

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5516713A (en) * 1994-09-06 1996-05-14 United Microelectronics Corporation Method of making high coupling ratio NAND type flash memory
US5972752A (en) * 1997-12-29 1999-10-26 United Semiconductor Corp. Method of manufacturing a flash memory cell having a tunnel oxide with a long narrow top profile
US6159807A (en) * 1998-09-21 2000-12-12 International Business Machines Corporation Self-aligned dynamic threshold CMOS device
US6369422B1 (en) * 2001-05-01 2002-04-09 Atmel Corporation Eeprom cell with asymmetric thin window
US6624027B1 (en) * 2002-05-09 2003-09-23 Atmel Corporation Ultra small thin windows in floating gate transistors defined by lost nitride spacers

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5352618A (en) 1993-07-30 1994-10-04 Atmel Corporation Method for forming thin tunneling windows in EEPROMs
US5761121A (en) 1996-10-31 1998-06-02 Programmable Microelectronics Corporation PMOS single-poly non-volatile memory structure
US6174771B1 (en) 1998-11-17 2001-01-16 Winbond Electronics Corp. Split gate flash memory cell with self-aligned process
US6709921B2 (en) * 2001-09-27 2004-03-23 Macronix International Co., Ltd. Fabrication method for a flash memory device with a split floating gate and a structure thereof
US6657252B2 (en) * 2002-03-19 2003-12-02 International Business Machines Corporation FinFET CMOS with NVRAM capability
US6888755B2 (en) * 2002-10-28 2005-05-03 Sandisk Corporation Flash memory cell arrays having dual control gates per memory cell charge storage element
US6905926B2 (en) 2003-09-04 2005-06-14 Atmel Corporation Method of making nonvolatile transistor pairs with shared control gate

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5516713A (en) * 1994-09-06 1996-05-14 United Microelectronics Corporation Method of making high coupling ratio NAND type flash memory
US5972752A (en) * 1997-12-29 1999-10-26 United Semiconductor Corp. Method of manufacturing a flash memory cell having a tunnel oxide with a long narrow top profile
US6159807A (en) * 1998-09-21 2000-12-12 International Business Machines Corporation Self-aligned dynamic threshold CMOS device
US6369422B1 (en) * 2001-05-01 2002-04-09 Atmel Corporation Eeprom cell with asymmetric thin window
US6486031B1 (en) * 2001-05-01 2002-11-26 Atmel Corporation Method of making an EEPROM cell with asymmetric thin window
US6624027B1 (en) * 2002-05-09 2003-09-23 Atmel Corporation Ultra small thin windows in floating gate transistors defined by lost nitride spacers

Also Published As

Publication number Publication date
TW200520105A (en) 2005-06-16
US6905926B2 (en) 2005-06-14
WO2005027194A2 (en) 2005-03-24
US7348626B2 (en) 2008-03-25
EP1665356A2 (en) 2006-06-07
US20050054160A1 (en) 2005-03-10
CN1875468A (en) 2006-12-06
US20050194632A1 (en) 2005-09-08

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