WO2005031805A3 - Multi-surface ic packaging structures and methods for their manufacture - Google Patents

Multi-surface ic packaging structures and methods for their manufacture Download PDF

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Publication number
WO2005031805A3
WO2005031805A3 PCT/US2004/031350 US2004031350W WO2005031805A3 WO 2005031805 A3 WO2005031805 A3 WO 2005031805A3 US 2004031350 W US2004031350 W US 2004031350W WO 2005031805 A3 WO2005031805 A3 WO 2005031805A3
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WO
WIPO (PCT)
Prior art keywords
manufacture
methods
packaging structures
interconnection
package
Prior art date
Application number
PCT/US2004/031350
Other languages
French (fr)
Other versions
WO2005031805A2 (en
Inventor
Joseph C Fjelstad
Para K Segaram
Thomas J Obenhuber
Kevin P Grundy
Original Assignee
Silicon Pipe Inc
Joseph C Fjelstad
Para K Segaram
Inessa Obenhuber Ef
Kevin P Grundy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Pipe Inc, Joseph C Fjelstad, Para K Segaram, Inessa Obenhuber Ef, Kevin P Grundy filed Critical Silicon Pipe Inc
Priority to EP04788995A priority Critical patent/EP1671369A4/en
Publication of WO2005031805A2 publication Critical patent/WO2005031805A2/en
Publication of WO2005031805A3 publication Critical patent/WO2005031805A3/en

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    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Abstract

An IC package (400) having multiple surfaces for interconnection with interconnection elements (403) making connections from the IC chip to the I/O terminations (409) of the package assembly which reside on more than one of its surfaces and which make interconnections to other devices or assemblies that are spatially separated.
PCT/US2004/031350 2003-09-24 2004-09-24 Multi-surface ic packaging structures and methods for their manufacture WO2005031805A2 (en)

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US50632203P 2003-09-24 2003-09-24
US60/506,322 2003-09-24
US10/947,686 US7061096B2 (en) 2003-09-24 2004-09-23 Multi-surface IC packaging structures and methods for their manufacture
US10/947,686 2004-09-23

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US20110215475A1 (en) 2011-09-08
WO2005031805A2 (en) 2005-04-07
EP1671369A4 (en) 2011-08-17
US8598696B2 (en) 2013-12-03
US7061096B2 (en) 2006-06-13
US20050093127A1 (en) 2005-05-05
EP1671369A2 (en) 2006-06-21
US7919355B2 (en) 2011-04-05
US7737545B2 (en) 2010-06-15
US20060157846A1 (en) 2006-07-20
US20100221871A1 (en) 2010-09-02

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