WO2005041206A8 - Method, system and circuit for programming a non-volatile memory array - Google Patents

Method, system and circuit for programming a non-volatile memory array

Info

Publication number
WO2005041206A8
WO2005041206A8 PCT/IL2004/000981 IL2004000981W WO2005041206A8 WO 2005041206 A8 WO2005041206 A8 WO 2005041206A8 IL 2004000981 W IL2004000981 W IL 2004000981W WO 2005041206 A8 WO2005041206 A8 WO 2005041206A8
Authority
WO
WIPO (PCT)
Prior art keywords
cells
programming
circuit
volatile memory
nvm
Prior art date
Application number
PCT/IL2004/000981
Other languages
French (fr)
Other versions
WO2005041206A2 (en
WO2005041206A3 (en
Inventor
Guy Cohen
Boaz Eitan
Original Assignee
Saifun Semiconductors Ltd
Guy Cohen
Boaz Eitan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Saifun Semiconductors Ltd, Guy Cohen, Boaz Eitan filed Critical Saifun Semiconductors Ltd
Priority to EP04791843A priority Critical patent/EP1683159A4/en
Priority to JP2006537552A priority patent/JP2007510252A/en
Publication of WO2005041206A2 publication Critical patent/WO2005041206A2/en
Publication of WO2005041206A3 publication Critical patent/WO2005041206A3/en
Publication of WO2005041206A8 publication Critical patent/WO2005041206A8/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628Programming or writing circuits; Data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5671Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge trapping in an insulator
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/3468Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing

Abstract

The present invention is a multi-phase method, circuit and system for programming non-volatile memory ('NVM') cells in an NVM array (100). The present invention may include a controller (110) to determine when, during a first programming phase (2000), one or more NVM cells of a first set of cells reaches or exceeds a first intermediate voltage, and to cause a charge pump circuit (130) to apply to a terminal of the one or more cells (100) in the first set second phase programming (3000) pulses to induce relatively greater threshold voltage changes in cells having less stored charge than in cells having relatively more stored charge.
PCT/IL2004/000981 2003-10-29 2004-10-27 Method, system and circuit for programming a non-volatile memory array WO2005041206A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP04791843A EP1683159A4 (en) 2003-10-29 2004-10-27 Method, system and circuit for programming a non-volatile memory array
JP2006537552A JP2007510252A (en) 2003-10-29 2004-10-27 Method, system and circuit for programming a non-volatile memory array

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/695,449 US7136304B2 (en) 2002-10-29 2003-10-29 Method, system and circuit for programming a non-volatile memory array
US10/695,449 2003-10-29

Publications (3)

Publication Number Publication Date
WO2005041206A2 WO2005041206A2 (en) 2005-05-06
WO2005041206A3 WO2005041206A3 (en) 2005-06-02
WO2005041206A8 true WO2005041206A8 (en) 2005-06-30

Family

ID=34522797

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IL2004/000981 WO2005041206A2 (en) 2003-10-29 2004-10-27 Method, system and circuit for programming a non-volatile memory array

Country Status (6)

Country Link
US (2) US7136304B2 (en)
EP (1) EP1683159A4 (en)
JP (1) JP2007510252A (en)
CN (1) CN1902711A (en)
TW (1) TWI371755B (en)
WO (1) WO2005041206A2 (en)

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