WO2005045633A3 - Nonblocking and deterministic unicast packet scheduling - Google Patents

Nonblocking and deterministic unicast packet scheduling Download PDF

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Publication number
WO2005045633A3
WO2005045633A3 PCT/US2004/035954 US2004035954W WO2005045633A3 WO 2005045633 A3 WO2005045633 A3 WO 2005045633A3 US 2004035954 W US2004035954 W US 2004035954W WO 2005045633 A3 WO2005045633 A3 WO 2005045633A3
Authority
WO
WIPO (PCT)
Prior art keywords
network
packets
interconnection network
operated
nonblocking
Prior art date
Application number
PCT/US2004/035954
Other languages
French (fr)
Other versions
WO2005045633A2 (en
Inventor
Venkat Konda
Original Assignee
Teak Technologies Inc
Venkat Konda
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Teak Technologies Inc, Venkat Konda filed Critical Teak Technologies Inc
Priority to EP04810098A priority Critical patent/EP1690159A2/en
Priority to CA002544219A priority patent/CA2544219A1/en
Priority to JP2006538294A priority patent/JP2007510376A/en
Publication of WO2005045633A2 publication Critical patent/WO2005045633A2/en
Priority to IL175337A priority patent/IL175337A0/en
Publication of WO2005045633A3 publication Critical patent/WO2005045633A3/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H04L47/52—Queue scheduling by attributing bandwidth to queues
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00—Traffic control in data switching networks
    • H04L47/50—Queue scheduling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/111—Switch interfaces, e.g. port details
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/10—Packet switching elements characterised by the switching fabric construction
    • H04L49/112—Switch control, e.g. arbitration
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3018—Input queuing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3027—Output queuing

Abstract

A system for scheduling unicast packets through an interconnection network, comprising r1, input ports with each input port having r2 input queues, r2 output ports with each output port having r1 output queues, and the interconnection network having a speedup of at least with, Formula (I), subnetworks, and each subnetwork comprising at least one first internal link connected to each input port for a total of at least r1 first internal links, each subnetwork further comprising at least one second internal link connected to each output port for a total of at least r2 second internal links is operated in strictly nonblocking manner in accordance with the invention by scheduling, at most r1 packets in each switching time to be switched in at most r1 switching times when r1 ≤ r2 and at most r2 packets in each switching time to be switched in at most r1 switching times when r2 ≤ r1 in deterministic manner, and without the requirement of segmentation and reassembly of packets. The system is also operated at 100% throughput, work conserving, fair, and yet deterministically thereby never congesting the output ports. The system performs only one iteration for arbitration, and with mathematical minimum speedup in the interconnection network. The system operates with absolutely no packet reordering issues, no internal buffering of packets in the interconnection network, and hence in a truly cut-through and distributed manner. In one embodiment, the system is operated in strictly nonblocking manner with only one subnetwork and with double switching rate through the subnetwork. In another embodiment, the system is operated in rearrangeably nonblocking manner with a speedup of at least, Formula (II), in the interconnection network. When the number of input ports r1 is equal to the number of output ports Pi, and r1 = r2 = r , the interconnection network having a speedup of at least, Formula (III), is operated in strictly nonblocking and deterministic manner in accordance with the invention by scheduling at most r packets in each switching time to be switched in at most r switching times. And with a speedup of at least, Formula (IV), in the interconnection network, the system is operated in rear rangeably nonblocking and deterministic manner. The system also offers end to end guaranteed bandwidth and latency for packets from input ports to output ports. In all the embodiments, the interconnection network may be crossbar network, shared memory network, clos network, hypercube network, or any internally nonblocking interconnection network or network of networks.
PCT/US2004/035954 2003-10-30 2004-10-29 Nonblocking and deterministic unicast packet scheduling WO2005045633A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP04810098A EP1690159A2 (en) 2003-10-30 2004-10-29 Nonblocking and deterministic unicast packet scheduling
CA002544219A CA2544219A1 (en) 2003-10-30 2004-10-29 Nonblocking and deterministic unicast packet scheduling
JP2006538294A JP2007510376A (en) 2003-10-30 2004-10-29 Non-blocking and deterministic unicast packet scheduling
IL175337A IL175337A0 (en) 2003-10-30 2006-04-30 Nonblocking and deterministic unicast packet scheduling

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US51605703P 2003-10-30 2003-10-30
US60/516,057 2003-10-30

Publications (2)

Publication Number Publication Date
WO2005045633A2 WO2005045633A2 (en) 2005-05-19
WO2005045633A3 true WO2005045633A3 (en) 2006-08-24

Family

ID=34572866

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2004/035954 WO2005045633A2 (en) 2003-10-30 2004-10-29 Nonblocking and deterministic unicast packet scheduling

Country Status (5)

Country Link
EP (1) EP1690159A2 (en)
JP (1) JP2007510376A (en)
CA (1) CA2544219A1 (en)
IL (1) IL175337A0 (en)
WO (1) WO2005045633A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2461693B (en) 2008-07-07 2012-08-15 Micron Technology Inc Switching method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5787086A (en) * 1995-07-19 1998-07-28 Fujitsu Network Communications, Inc. Method and apparatus for emulating a circuit connection in a cell based communications network
US6212182B1 (en) * 1996-06-27 2001-04-03 Cisco Technology, Inc. Combined unicast and multicast scheduling
US20010043606A1 (en) * 2000-05-19 2001-11-22 Man-Soo Han Cell scheduling method of input and output buffered switch using simple iterative matching algorithm
US6351466B1 (en) * 1998-05-01 2002-02-26 Hewlett-Packard Company Switching systems and methods of operation of switching systems
US20020048280A1 (en) * 2000-09-28 2002-04-25 Eugene Lee Method and apparatus for load balancing in network processing device
US20020191626A1 (en) * 2001-06-19 2002-12-19 Norihiko Moriwaki Packet communication system

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5787086A (en) * 1995-07-19 1998-07-28 Fujitsu Network Communications, Inc. Method and apparatus for emulating a circuit connection in a cell based communications network
US6212182B1 (en) * 1996-06-27 2001-04-03 Cisco Technology, Inc. Combined unicast and multicast scheduling
US6351466B1 (en) * 1998-05-01 2002-02-26 Hewlett-Packard Company Switching systems and methods of operation of switching systems
US20010043606A1 (en) * 2000-05-19 2001-11-22 Man-Soo Han Cell scheduling method of input and output buffered switch using simple iterative matching algorithm
US20020048280A1 (en) * 2000-09-28 2002-04-25 Eugene Lee Method and apparatus for load balancing in network processing device
US20020191626A1 (en) * 2001-06-19 2002-12-19 Norihiko Moriwaki Packet communication system

Also Published As

Publication number Publication date
EP1690159A2 (en) 2006-08-16
JP2007510376A (en) 2007-04-19
CA2544219A1 (en) 2005-05-19
IL175337A0 (en) 2006-09-05
WO2005045633A2 (en) 2005-05-19

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