WO2005073948A1 - Image display screen and method of addressing said screen - Google Patents

Image display screen and method of addressing said screen Download PDF

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Publication number
WO2005073948A1
WO2005073948A1 PCT/FR2004/003104 FR2004003104W WO2005073948A1 WO 2005073948 A1 WO2005073948 A1 WO 2005073948A1 FR 2004003104 W FR2004003104 W FR 2004003104W WO 2005073948 A1 WO2005073948 A1 WO 2005073948A1
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WO
WIPO (PCT)
Prior art keywords
addressing
voltage
modulator
circuit
selection
Prior art date
Application number
PCT/FR2004/003104
Other languages
French (fr)
Inventor
Philippe Le Roy
Christophe Prat
Fabien Ammardji
Original Assignee
Thomson Licensing
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thomson Licensing filed Critical Thomson Licensing
Priority to JP2006546220A priority Critical patent/JP5074769B2/en
Priority to KR1020067012112A priority patent/KR101205912B1/en
Priority to EP04805623.8A priority patent/EP1700290B1/en
Publication of WO2005073948A1 publication Critical patent/WO2005073948A1/en

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Classifications

    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/04Structural and physical details of display devices
    • G09G2300/0404Matrix technologies
    • G09G2300/0417Special arrangements specific to the use of low carrier mobility technology
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0842Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243Details of the generation of driving signals
    • G09G2310/0254Control of polarity reversal in general, other than for liquid crystal displays
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/04Maintaining the quality of display appearance
    • G09G2320/043Preventing or counteracting the effects of ageing

Definitions

  • the invention relates to an image display screen and a method for addressing this screen.
  • the invention relates to a display screen of the type based on organic electroluminescent materials with active matrix etched on amorphous silicon (Si-a).
  • Thin Film Transistor in hydrogenated amorphous silicon have advantages compared to thin film transistors in polycrystalline silicon (p-Si) for the design of screens based on organic electroluminescent materials because they are more easy to manufacture and they exhibit luminance uniformity on relatively large samples.
  • p-Si polycrystalline silicon
  • the trigger threshold voltage of amorphous silicon transistors drifts over time during the prolonged application of a voltage between their gate and their source.
  • a screen of the aforementioned type comprising addressing control means suitable for applying, during each image frame, to the current modulator of each transmitter of this screen and using at least one of the plurality of addressing circuits of this transmitter, an addressing voltage representative of a datum of image always showing the same polarization.
  • the object of the invention is to provide an alternative screen which exhibits small variations in luminance over time.
  • the subject of the invention is an image display screen comprising: - light emitters (4) distributed along rows of emitters and columns of emitters to form a network of emitters, - means for controlling the transmission of the transmitters of the network comprising: a) a first addressing circuit of a transmitter, associated with each transmitter of the network for controlling the current passing through, said circuit comprising: - a first modulator of current capable of supplying said transmitter, said first modulator comprising a gate electrode and two current flow electrodes, - a first storage capacity capable of imposing a potential on the gate electrode of the first current modulator, b) for each transmitter, at least a second addressing circuit of a transmitter, said first and said second addressing circuits being associated in parallel with the same transmitter, said second circuit comprising: - a second modulator current from said transmitter comprising a gate electrode and two current flow electrodes, - a second storage capacity capable of storing a potential at the gate electrode of the second current modulator; c) addressing control means being able
  • the display screen includes one or more of the following characteristics: - the addressing control means are adapted to apply to said first current modulator first the addressing voltage to start an activation phase of the first addressing circuit, then the bias voltage to start a bias phase of the first addressing circuit; the addressing control means are suitable for applying to said second current modulator first the addressing voltage to start an activation phase of the second addressing circuit, then the bias voltage to start a bias phase of the second addressing circuit, the activation phase of the first addressing circuit is synchronous with the polarization phase of the second addressing circuit and the activation phase of the second addressing circuit is synchronous with the polarization phase the first addressing circuit; the control means comprise selection control means comprising: for each first addressing circuit of a transmitter, a first
  • the invention also relates to a method for addressing a display screen of this type, characterized in that it comprises, for the control of each transmitter: - a phase of activation of the first addressing circuit for supply the transmitter with current, - a bias phase of the second addressing circuit to derive the trigger threshold voltage of the second modulator, - an activation phase of the second addressing circuit to supply current to the transmitter, - a bias phase of the first addressing circuit to derive the trigger threshold voltage of the first modulator, and the activation phase of the first addressing circuit is concomitant with the bias phase of the second addressing circuit and the activation phase of the second addressing circuit is concomitant with the bias phase of the first addressing circuit.
  • the display method comprises one or more of the following characteristics: - one or more phases of activation of the first addressing circuit are followed by at least one phase of polarization of the first circuit addressing and one or more activation phases of the second addressing circuit are followed by at least one bias phase of the second addressing circuit; the method comprises: a step of programming the addressing of said first storage capacity by applying to said capacity an addressing voltage representative of an image datum, a step of programming polarization of said first modulator current by applying a bias voltage to said modulator, said bias voltage having a polarity opposite to the polarity of the potential stored by the first storage capacity, - a step for programming the bias of said second current modulator by applying to said modulator of said bias voltage, and - a step of programming the addressing of said second storage capacity by applying said capacity of said addressing voltage to said capacity; the polarization programming step of said first current modulator is followed by the addressing programming step of the second storage capacity and alternatively the programming step of polarization of said second current
  • FIG. 1 is a schematic view showing a transmitter and control means the emission of this screen transmitter according to a first embodiment of the invention
  • FIG. 2A to 2F are graphs representing the evolution over time of different voltages and currents during the addressing process performed by the device according to the invention; in particular, FIG. 2A is a graph representing the selection voltage applied to a first selection electrode; - Figure 2B is a graph showing the voltage applied to a second selection electrode; - Figure 2C is a graph showing the voltage applied to a addressing electrode;
  • FIG. 1 is a schematic view showing a transmitter and control means the emission of this screen transmitter according to a first embodiment of the invention
  • FIG. 2A to 2F are graphs representing the evolution over time of different voltages and currents during the addressing process performed by the device according to the invention; in particular, FIG. 2A is a graph representing the selection voltage applied to a first selection electrode; - Figure 2B is a graph showing the voltage applied to a second selection electrode; - Figure 2C is a graph showing
  • FIG. 2D is a graph representing the voltage applied to the terminals of a first storage capacity and the voltage applied to the terminals of a second storage capacity
  • FIG. 2E is a graph representing the drain current passing through a first current modulator and the drain current passing through a second current modulator
  • - Figure 2F is a graph showing the current flowing through a transmitter
  • - Figure 3 is a schematic view showing a transmitter and means for controlling the transmission of this transmitter from the screen according to a second embodiment of the invention
  • - Figures 4A to 4F are graphs representing the evolution over time of different voltages and currents during the addressing process performed by the device according to the second embodiment of the invention; in particular, FIG.
  • FIG. 4A is a graph representing the selection voltage applied to a selection electrode
  • - Figure 4B is a graph showing the voltage applied to a first addressing electrode
  • - Figure 4C is a graph showing the voltage applied to a second addressing electrode
  • - Figure 4D is a graph showing the voltage across a first storage capacity and the voltage across a second storage capacity
  • FIG. 4E is a graph representing the drain current passing through a first current modulator and the drain current passing through a second current modulator
  • FIG. 4F is a graph representing the current passing through a transmitter.
  • the display screen according to the invention is an active matrix screen comprising light emitters distributed in rows and columns to form a network of emitters.
  • the display screen emitters are organic light emitting diodes known by the acronym OLED.
  • FIG. 1 represents means 2 for controlling the transmission of transmitters 4 from the network according to a first embodiment of the invention.
  • the control means 2 comprise a first addressing circuit 6 connected to a transmitter 4 of the network, addressing control means 8 of a column of transmitters, selection control means 10 of a line of transmitters, a control system 11 and a second addressing circuit 12 also connected to a transmitter 4.
  • the first addressing circuit 6 comprises a current modulator 14, a storage capacity 16 and a selection switch 18.
  • the modulator 14 and the switch 18 are thin film transistors made of hydrogenated amorphous silicon. More precisely, these are n-type transistors.
  • the transistors 14 and 18 are capable of being traversed by a current flowing from their source to their drain.
  • the drain of the modulator 14 is connected to the cathode of the emitter 4.
  • the anode of the emitter 4 is connected to a DC voltage generator V dd capable of supplying it with power.
  • the source of the modulator 14 is connected to a ground electrode or to a negative voltage.
  • the gate of the modulator 1.4 is connected to the source of the switch 18 and to a terminal of the storage capacity 16.
  • the other terminal of the capacity 16 is connected to a ground electrode.
  • the gate of the switch 18 is connected to the selection control means 10 and its drain is connected to the addressing control means 8.
  • the addressing control means 8 of a column of transmitters comprise an electrode addressing 20 by column of transmitters and an addressing control unit 22.
  • the electrode 20 is connected on the one hand to the control unit 22 and, on the other hand to the drain of the switch 18 of the first circuits addressing 6 of a column of transmitters.
  • the selection control means 10 comprise a first selection electrode 24 and a second selection electrode 26 for each row of transmitters as well as a selection control unit 28.
  • the first selection electrode 24 is connected to the control unit 28 and to the grid of the switch 18 of the first addressing circuits 6 of a line of transmitters.
  • the second electrode 26 is connected to the control unit 28 and to the grid of the switch 38 of the second addressing circuits 12 of a line of transmitters.
  • the control system 11 is connected to the addressing control unit 22 and to the selection control unit 28.
  • the second addressing circuit 12 comprises the same components as the first addressing circuit 6, namely a current modulator 34, a storage capacity 36 and a selection switch 38. These components are connected together in the same way as in the first addressing circuit 6 and will not be described in detail.
  • the current modulator 34 of the second addressing circuit 12 is connected to the cathode of the emitter 4 at node 32.
  • the drain of the switch 38 is connected to the same addressing electrode 20 as the switch 18 and its grid is connected to the second selection electrode
  • the control system 11 is able to transmit digital image data and data relating to the bias voltage to the control unit 22 and a periodic selection signal to the control unit 28 at a predefined frequency.
  • the addressing control unit 22 is capable of transmitting an addressing voltage V D representative of image data to all of the emitters of a column via the electrode 20.
  • the control unit d addressing 22 is also capable of applying to the electrode 20 a voltage, called the bias voltage V p , from a reverse bias to the bias of the addressing voltage.
  • This voltage is a predefined negative voltage of a predetermined duration.
  • the bias voltage V p is between - 2 Volts and - 25 Volts.
  • a reverse or negative bias voltage is called a potential difference V gs between the gate and source electrodes of the modulator which is less than 0 Volt: V gs ⁇ 0V. ⁇
  • the control unit 28 is able to apply a periodic selection voltage Vsi, V S 2 to the grid of the switch 18 of the first addressing circuits 6 of a row of transmitters or to the grid of the switch 38 of the second addressing circuits 12 of the same line of transmitters to authorize the application of the addressing voltage V D or of the bias voltage V p to the gate of the modulator 14 of the first addressing circuit 6 or to the gate of the modulator 34 second addressing circuit 12.
  • FIGS. 2A to 2F illustrate the method of addressing a display screen according to the first embodiment of the invention. This method includes a polarization programming step.
  • the selection control unit 28 transmits to the second electrode 26, a selection voltage V s2, as illustrated in FIG. 2B.
  • the selection switch 38 is released by applying this selection voltage V S2 to its gate.
  • the addressing control unit 22 applies to the addressing electrode 20 a bias voltage V p of a negative polarity (V gs ⁇ 0).
  • the bias voltage V p is applied to the grid of the current modulator 34 and to a terminal of the storage capacity 36.
  • the drain current Id2 which passed through the modulator 34 to supply the transmitter 4 during the previous frame, now tends towards 0 during this new frame as shown by the dotted curve in FIG. 2E.
  • the storage capacity 36 having previously stored a voltage V D applied during the previous frame, is biased at the bias voltage V P ⁇ as illustrated in FIG. 2D; as indicated by the dotted curve in this figure, the storage capacity 36 maintains this bias voltage at the gate of the modulator 34 during a bias phase of the second addressing circuit 12 and until the end of the next step programming the modulator 34.
  • the steps B, C and D together constitute a phase of polarization of the second addressing circuit 12.
  • the triggering threshold voltage of the modulator 34 having undergone a drift by the application of a voltage of addressing during the previous image frame, is again derived during the polarization phase and throughout the duration of the new frame, by applying the bias voltage V p but in a direction opposite to its previous drift.
  • the bias voltage applied to the gate of the modulator 34 during the new frame makes it possible to reverse the drift of its trigger threshold voltage and to return it to its initial value, that is to say to the value that 'it had before being derived by applying an addressing voltage to its grid in the previous frame.
  • the selection control unit 28 generates a selection voltage Vsi and applies it to the first electrode 24.
  • the addressing control unit 22 transmits to the addressing electrode 20 an addressing voltage V Da representative of an image datum.
  • the selection switch 18, at the intersection of the addressing electrode 20 and the first selection electrode 24, is released and transmits the addressing voltage V Da to the modulator 14 and to the storage capacity 16 of the first circuit as the addressing voltage Vo a is greater than the triggering threshold voltage of the modulator 14, a drain current Idi is established between the drain and the source of the modulator 14 and therefore crosses the emitter 4 as shown in Figure 2F.
  • the capacitor 16 stores a potential representative of the addressing voltage V Da at the gate of the modulator 14 to maintain the luminance of the transmitter 4 during a time interval corresponding to the duration of an image frame.
  • the emitter 4 emits light during step C until the end of the image frame.
  • steps B, C and D it can therefore be seen that the transmitter 4 is supplied with current by the first addressing circuit 6. Steps B, C and D therefore together form an activation phase of the first circuit addressing 6.
  • the selection control unit 28 transmits to the first electrode 24 a selection voltage Vsi.
  • the addressing control unit 22 applies a bias voltage V p to the electrode 20.
  • the selection switch 18, at the intersection of the first electrode 24 and the addressing electrode 20, is released and this time transmits the bias voltage V p to the modulator 14 and to the storage capacity 16.
  • the capacity of storage discharges and stores the charges transmitted by the bias voltage during a bias phase E, F of the first addressing circuit 6, as illustrated in FIG. 2D.
  • the drain current lai of the previous frame stops passing through the modulator 14.
  • the threshold voltage for triggering the modulator 14 which has drifted and increased during the image frame will decrease during the new frame and in particular during from step F.
  • the following image frame starts with an addressing programming step E of the modulator 34 of the second addressing circuit 12.
  • the selection control unit 28 applies to the electrode 26 a selection voltage V s2 .
  • the addressing control unit 22 applies in parallel to the electrode 20 an addressing voltage V Db -
  • the switch 38 of the second addressing circuit 12 is released and the addressing voltage V D t > , representative d image data is applied to the grid of the modulator 34 and to the terminal of the storage capacity 36.
  • a drain current l d2 is generated between the drain and the source of the modulator 34. This current has a proportional amplitude to the value of the image data to be transmitted during this image frame. This current flows through the light emitter 4 during step F until the end of the image frame. During steps E and F, it can therefore be seen that the transmitter 4 is supplied with current by the second addressing circuit 12. Steps E and F therefore together form an activation phase of the second addressing circuit 12.
  • control system 11 and the control units 22 and 28 control the addressing of the selection, addressing and bias voltages so that: - an addressing voltage of positive polarity is applied to the grid of the modulator 14 of the first addressing circuit 6 to supply the transmitter 4 and consecutively, a bias voltage of negative polarity is applied to the gate of the modulator 34 of the second circuit addressing 12 to compensate for the derivation of its trigger threshold voltage; - then inversely, an addressing voltage of positive polarity is applied to the gate of the modulator 34 of the second addressing circuit 12 to supply the transmitter 4 and, consecutively, a bias voltage of negative polarity is applied to the gate of the modulator 14 of the first addressing circuit 6 to compensate for the derivation of its trigger threshold voltage.
  • the transmitter 4 is supplied with current in turn by the first modulator 14 during an activation phase of the first addressing circuit, then by the second modulator 34 during a phase activation of the second addressing circuit.
  • the trigger threshold voltages of the modulator 14 of the first addressing circuit and of the modulator 34 of the second addressing circuit are increased and then decreased in turn at each image frame.
  • Such a device therefore advantageously makes it possible to compensate for the drift in the triggering threshold voltage of the panel modulators.
  • a transmitter 4 and the control means 40 for its transmission according to a second embodiment of the invention, are shown in FIG. 3.
  • control means 40 comprise first addressing circuits 6 and second addressing circuits 12, each connected to a transmitter 4 of the network, addressing control means 42 of a column of transmitters, selection control means 44 of a row of transmitters and a system 56.
  • the first 6 and the second 12 addressing circuits comprise the same components, connected in the same way as the addressing circuits described in connection with FIG. 1. They are identified by the same references as in the FIG. 1 and will no longer be described below.
  • the addressing control means 42 comprise an addressing control unit 46, a first addressing electrode 48 and a second addressing electrode 50 for each column of transmitters.
  • the first addressing electrode 48 is connected to the control unit 46 and to the drain of the switch 18 of all of the first addressing circuits 6 of a column of transmitters.
  • the second addressing electrode 50 is connected to the control unit 46 and to the drain of the switch 38 of all of the second addressing circuits 12 of a column of transmitters.
  • the addressing control unit 46 is able to send an addressing voltage V D ⁇ to the first electrode 48 and concomitantly an addressing voltage V D2 to the second electrode 50.
  • the control means 44 for selection comprise a selection control unit 54 and for each row of transmitters a single selection electrode 52.
  • the selection electrode 52 is connected to the control unit 54, to the grid of the switch 18 of the first addressing circuits 6 and to the grid of the switch 38 of the second addressing circuits 12 of a line of transmitters.
  • the control system 56 is connected to the control unit 54 as well as to the control unit 46. This control system 56 is able to transmit to the control unit 46 digital image data and data relating to the bias voltage. It is also able to transmit to the control unit 54 a periodic selection signal.
  • FIGS. 4A to 4F The method for addressing a display screen according to the second embodiment of the invention is illustrated in FIGS. 4A to 4F. This method comprises a step G for programming the addressing of the capacitor 16 and for programming the simultaneous polarization of the modulator 34.
  • the control unit 46 transmits an addressing voltage V Da representative of an image datum at the first electrode 48 and a bias voltage V p at the second electrode 50.
  • the control unit 54 transmits a selection voltage V s on the selection electrode 52.
  • the switch 18 of the first addressing circuit and l switch 38 of the second programming circuit are released so that on the one hand, the bias voltage V p is applied to the gate of the modulator 34 and to the terminal of the capacitor 36 and on the other hand, the voltage of Voa addressing is applied to the grid of the modulator 14 and to a terminal of the storage capacity 16.
  • the storage capacity 36 discharges and then charges at a negative potential equal to the bias voltage V p .
  • the drain current I 2 is canceled and remains zero during step H.
  • the capacitor 16 charges at the potential VD 3 and a drain current I d i is established between the drain and the source of the modulator 14.
  • L emitter 4 is supplied with current I d i during step H until the end of the image frame.
  • the transmitter 4 is therefore supplied with current by the first addressing circuit 6; steps G and H therefore together form an activation phase of the first addressing circuit.
  • Steps G and H the bias voltage is applied to the gate of the modulator 34 to compensate for the drift of its trigger threshold voltage. Steps G and H therefore also form a phase of polarization of the second addressing circuit.
  • the control unit 46 transmits a bias voltage V p to the first electrode 48 and an addressing voltage V Db representative of an image datum at the second electrode 50.
  • the switches 18 and 38 are simultaneously open by applying the selection voltage V s to the electrode 52.
  • the bias voltage V p is transmitted to the gate of the modulator 14 and to the terminal of the capacitor 16.
  • the capacitor 16 discharges and then charges negatively.
  • the drain current l d1 is canceled out and remains zero during step J.
  • the bias voltage V p is applied to the gate of the modulator 14. Steps I and J therefore together form a phase of polarization of the first addressing circuit 6.
  • the addressing voltage V D is applied to the gate of the modulator 34 and to a terminal of the capacitor 36 This voltage, maintained at the gate of the modulator 34 by the capacitor 36, generates a drain current I d2 which supplies the transmitter 4 during step J and until the next step of programming new image data.
  • the transmitter 4 is supplied with current by the second addressing circuit 12; these steps therefore together form an activation phase of the second addressing circuit.
  • control system 56 and the control units 46 and 54 control the addressing of the selection, addressing and bias voltages so that: - an addressing voltage of positive polarity is applied to the gate of the modulator 14 of the first addressing circuit 6 to supply the transmitter 4 and simultaneously, a bias voltage of negative polarity is applied to the gate of the modulator 34 of the second addressing circuit 12 to compensate for the drift of its threshold voltage trigger; - then inversely, an addressing voltage of positive polarity is applied to the gate of the modulator 34 of the second addressing circuit 12 to supply the transmitter 4 and simultaneously, a bias voltage of negative polarity is applied to the gate of the modulator 14 of the first addressing circuit 6 to compensate for the drift of its trigger threshold voltage.
  • the transmitter 4 is thus supplied in turn by the modulated current, by the modulator 14, then by the modulator 34.
  • the first 6 and second 12 addressing circuits are alternately activated to supply current to the transmitter 4.
  • the modulator 14 supplies the transmitter 4
  • the modulator 34 is biased by application to its grid of a bias voltage corresponding to a high negative voltage so that the trigger threshold voltage of the modulator 34 derived during the previous phase regains its initial value.
  • the modulator 34 supplies the transmitter 4
  • the modulator 14 is biased by this same negative bias voltage so that its trigger threshold voltage having previously drifted in one direction, drift in an opposite direction.
  • the establishment of two circuits address associated with each transmitter helps to compensate for variations in the trigger threshold of the modulators of a display screen.
  • the polarization and activation phases are carried out simultaneously and have equal durations.
  • the control means are also able to control the modulators 14 and 34 so that the polarization and activation phases of the first and second circuits, although carried out simultaneously, have different durations.
  • the bias voltage applied to one or the other of the modulators of a transmitter varies from one image frame to another, depending on the addressing voltage applied to this modulator during the previous frame; preferably, this bias voltage is equal but of opposite sign to said addressing voltage of the previous frame.

Abstract

The invention relates to a display screen comprising: light emitters (4) which are distributed in rows and columns of emitters; and a first addressing circuit (6, 14, 16, 18) which is associated with each emitter of the network, said circuit (6) comprising a first current modulator (14) which can power the emitter (4) and a first storage capacity (16) which can store a potential at the grid electrode of the first current modulator (14). The inventive screen comprises at least one second emitter addressing circuit (12, 34, 36, 38), said first and second addressing circuits being associated with the same emitter. In addition, the second circuit comprises a second current modulator (34) for the emitter and a second storage capacity (36) which can store a potential at the grid electrode of the second current modulator. The invention also relates to a method of addressing the screen.

Description

Ecran d'affichage d'images et procédé d'adressage de cet écran. L'invention concerne un écran d'affichage d'images et un procédé d'adressage de cet écran. En particulier, l'invention est relative à un écran d'affichage du type à base de matériaux électroluminescents organiques à matrice active gravée sur du Silicium amorphe (Si-a). Les transistors en couches minces (Thin Film Transistor) en Silicium amorphe hydrogéné présentent des avantages par rapport aux transistors en couches minces en Silicium poly-cristallin (p-Si) pour la conception d'écrans à base de matériaux électroluminescents organiques car ils sont plus faciles à fabriquer et ils présentent une uniformité de luminance sur des échantillons de taille relativement importante. Cependant, la tension de seuil de déclenchement des transistors en Silicium amorphe dérive au cours du temps lors de l'application prolongée d'une tension entre leur grille et leur source. Cette dérivation des tensions de seuil de déclenchement se traduit par d'une part, un processus de marquage de l'image sur l'écran et d'autre part, des modifications de luminance de l'écran au cours du temps. II est connu notamment par le document US 2003/052614, un écran du type précité comprenant des moyens de commande d'adressage propres à appliquer, au cours de chaque trame d'image, au modulateur de courant de chaque émetteur de cet écran et à l'aide du même et unique circuit d'adressage de cet émetteur, alternativement une tension d'adressage représentative d'une donnée d'image et une tension de polarité inverse à la polarité de la tension d'adressage. Toutefois, cette architecture et ce mode de pilotage est susceptible d'entraîner une baisse de luminance de l'écran et un phénomène de papillotement sur l'écran, puisque la durée d'émission est réduite au cours de chaque trame. Il est connu notamment par le document US 6 011 529 (voir notamment figure 9) et WO 2004/051617, un écran du type précité comprenant des moyens de commande d'adressage propres à appliquer, au cours de chaque trame d'image, au modulateur de courant de chaque émetteur de cet écran et à l'aide d'au moins un parmi la pluralité de circuits d'adressage de cet émetteur, une tension d'adressage représentative d'une donnée d'image présentant toujours la même polarisation. Le but de l'invention est de proposer un écran alternatif qui présente de faibles variations de luminance au cours du temps. A cet effet, l'invention a pour objet un écran d'affichage d'images comportant : - des émetteurs (4) de lumière répartis selon des lignes d'émetteurs et des colonnes d'émetteurs pour former un réseau d'émetteurs, - des moyens de commande de l'émission des émetteurs du réseau comprenant : a) un premier circuit d'adressage d'un émetteur, associé à chaque émetteur du réseau pour la commande du courant le traversant, ledit circuit comportant : - un premier modulateur de courant apte à alimenter ledit émetteur, ledit premier modulateur comprenant une électrode de grille et deux électrodes de passage du courant, - une première capacité de stockage apte à imposer un potentiel à l'électrode de grille du premier modulateur de courant, b) pour chaque émetteur, au moins un second circuit d'adressage d'un émetteur, ledit premier et ledit second circuits d'adressage étant associés en parallèle au même émetteur, ledit second circuit comprenant : - un second modulateur de courant dudit émetteur comportant une électrode de grille et deux électrodes de passage du courant, - une seconde capacité de stockage apte à stocker un potentiel à l'électrode de grille du second modulateur de courant ; c) des moyens de commande d'adressage étant aptes à appliquer une tension d'adressage à ladite première capacité de stockage, et à ladite seconde capacité de stockage, ladite tension d'adressage étant représentative d'une donnée d'image, et étant adaptés pour activer au choix le premier ou le second circuits d'adressage pour alimenter l'émetteur en courant selon ladite donnée d'image. L'écran est caractérisé en ce que les moyens de commande d'adressage sont aptes à imposer une tension de polarisation au choix audit premier modulateur de courant ou audit second modulateur de courant, ladite tension de polarisation ayant une polarité inverse à la polarité de ladite tension d'adressage. Suivant des modes particuliers de réalisation, l'écran d'affichage comporte l'une ou plusieurs des caractéristiques suivantes : - les moyens de commande d'adressage sont propres à appliquer audit premier modulateur de courant d'abord la tension d'adressage pour démarrer une phase d'activation du premier circuit d'adressage, puis la tension de polarisation pour démarrer une phase de polarisation du premier circuit d'adressage ; - les moyens de commande d'adressage sont propres à appliquer audit second modulateur de courant d'abord la tension d'adressage pour démarrer une phase d'activation du second circuit d'adressage, puis la tension de polarisation pour démarrer une phase de polarisation du second circuit d'adressage, la phase d'activation du premier circuit d'adressage est synchrone à la phase de polarisation du second circuit d'adressage et la phase d'activation du second circuit d'adressage est synchrone à la phase de polarisation du premier circuit d'adressage ; - les moyens de commande comprennent des moyens de commande de sélection comportant : - pour chaque premier circuit d'adressage d'un émetteur, un premier interrupteur de sélection apte à piloter la transmission de ladite tension d'adressage ou de ladite tension de polarisation en fonction d'une tension de sélection vers ladite première capacité de stockage et ladite grille dudit premier modulateur de courant pour sélectionner ledit émetteur, - pour chaque second circuit d'adressage du même émetteur, un second interrupteur de sélection apte à piloter la transmission de ladite tension d'adressage ou de ladite tension de polarisation en fonction de ladite tension de sélection vers ladite seconde capacité de stockage et ladite grille dudit second modulateur de courant pour sélectionner ledit émetteur, et - des moyens de pilotage des premier et second interrupteurs de sélection ; - les moyens de pilotage comportent en outre pour chaque ligne d'émetteurs, une première et une seconde électrodes de sélection raccordées au premier, respectivement au second interrupteurs de sélection pour leur commande, et une unité de pilotage de sélection apte à transmettre alternativement, d'abord ladite tension de sélection à ladite première électrode de sélection, puis ladite tension de sélection à ladite seconde électrode de sélection ; - les moyens de commande d'adressage comportent une électrode d'adressage pour chaque colonne d'émetteurs, le premier et le second interrupteurs de sélection étant raccordés à ladite électrode d'adressage, et une unité de pilotage d'adressage apte à envoyer alternativement ladite tension d'adressage et ladite tension de polarisation sur ladite électrode d'adressage ; - les moyens de pilotage comportent en outre une électrode de sélection pour chaque ligne d'émetteurs, les premier et second interrupteurs de sélection étant raccordés à ladite électrode de sélection pour leur commande, et une unité de pilotage de sélection apte à envoyer ladite tension de sélection concomitamment aux premier et second interrupteurs de sélection ; - les moyens de commande d'adressage comportent pour chaque colonne d'émetteurs, une première et une seconde électrodes d'adressage raccordées au premier, respectivement au second interrupteurs de sélection et une unité de pilotage d'adressage apte à envoyer concomitamment sur la première électrode d'adressage et sur la seconde électrode d'adressage au choix, ladite tension d'adressage ou ladite tension de polarisation. L'invention a également pour objet un procédé d'adressage d'un écran d'affichage de ce type, caractérisé en ce qu'il comporte pour le pilotage de chaque émetteur : - une phase d'activation du premier circuit d'adressage pour alimenter en courant l'émetteur, - une phase de polarisation du second circuit d'adressage pour dériver la tension de seuil de déclenchement du second modulateur, - une phase d'activation du second circuit d'adressage pour alimenter en courant l'émetteur, - une phase de polarisation du premier circuit d'adressage pour dériver la tension de seuil de déclenchement du premier modulateur, et la phase d'activation du premier circuit d'adressage est concomitante à la phase de polarisation du second circuit d'adressage et la phase d'activation du second circuit d'adressage est concomitante à la phase de polarisation premier circuit d'adressage. Suivant des modes particuliers de réalisation, le procédé d'affichage comporte l'une ou plusieurs des caractéristiques suivantes : - une ou plusieurs phases d'activation du premier circuit d'adressage sont suivies par au moins une phase de polarisation du premier circuit d'adressage et une ou plusieurs phases d'activation du second circuit d'adressage sont suivies par au moins une phase de polarisation du second circuit d'adressage ; - le procédé comporte : - une étape de programmation d'adressage de ladite première capacité de stockage par application à ladite capacité d'une tension d'adressage représentative d'une donnée d'image, - une étape de programmation de polarisation dudit premier modulateur de courant par application audit modulateur d'une tension de polarisation, ladite tension de polarisation ayant une polarité inverse à la polarité du potentiel stocké par la première capacité de stockage, - une étape de programmation de polarisation dudit second modulateur de courant par application audit modulateur de ladite tension de polarisation, et - une étape de programmation d'adressage de ladite seconde capacité de stockage par application à ladite capacité de ladite tension d'adressage ; - l'étape de programmation de polarisation dudit premier modulateur de courant est suivie par l'étape de programmation d'adressage de la seconde capacité de stockage et alternativement l'étape de programmation de polarisation dudit second modulateur de courant est suivie par l'étape de programmation d'adressage de la première capacité de stockage ; et - ladite étape de programmation de polarisation dudit second modulateur de courant est concomitante à ladite étape de programmation d'adressage de ladite première capacité de stockage et ladite étape de programmation de polarisation dudit premier modulateur de courant est concomitante à ladite étape de programmation d'adressage de ladite seconde capacité de stockage. L'invention sera mieux comprise à la lecture de la description qui va suivre, donnée uniquement à titre d'exemple et faite en se référant aux dessins, sur lesquels : - la figure 1 est une vue schématique représentant un émetteur et des moyens de commande de l'émission de cet émetteur de l'écran selon un premier mode de réalisation de l'invention ; - les figures 2A à 2F sont des graphes représentant l'évolution au cours du temps de différents tensions et courants au cours du procédé d'adressage réalisé par le dispositif selon l'invention ; en particulier, - la figure 2A est un graphe représentant la tension de sélection appliquée à une première électrode de sélection ; - la figure 2B est un graphe représentant la tension appliquée à une seconde électrode de sélection ; - la figure 2C est un graphe représentant la tension appliquée à une électrode d'adressage ; - la figure 2D est un graphe représentant la tension appliquée aux bornes d'une première capacité de stockage et la tension appliquée aux bornes d'une seconde capacité de stockage ; - la figure 2E est un graphe représentant le courant de drain traversant un premier modulateur de courant et le courant de drain traversant un second modulateur de courant ; - la figure 2F est un graphe représentant le courant traversant un émetteur ; - la figure 3 est une vue schématique représentant un émetteur et des moyens de commande de l'émission de cet émetteur de l'écran selon un second mode de réalisation de l'invention ; - les figures 4A à 4F sont des graphes représentant l'évolution au cours du temps de différents tensions et courants au cours du procédé d'adressage réalisé par le dispositif selon le second mode de réalisation de l'invention ; en particulier, - la figure 4A est un graphe représentant la tension de sélection appliquée à une électrode de sélection ; - la figure 4B est un graphe représentant la tension appliquée à une première électrode d'adressage ; - la figure 4C est un graphe représentant la tension appliquée à une seconde électrode d'adressage ; - la figure 4D est un graphe représentant la tension aux bornes d'une première capacité de stockage et la tension aux bornes d'une seconde capacité de stockage ; - la figure 4E est un graphe représentant le courant de drain traversant un premier modulateur de courant et le courant de drain traversant un second modulateur de courant ; et - la figure 4F est un graphe représentant le courant traversant un émetteur. L'écran d'affichage selon l'invention est un écran à matrice active comportant des émetteurs de lumière répartis selon des lignes et des colonnes pour former un réseau d'émetteurs. Les émetteurs de l'écran d'affichage sont des diodes électroluminescentes organiques connues sous l'acronyme OLED. Ils sont chacun associé à un pixel lorsque l'écran est monochrome ou à un sous pixel lorsque l'écran est polychrome. Ils émettent une intensité lumineuse directement proportionnelle au courant qui les traverse. La figure 1 représente des moyens de commande 2 de l'émission des émetteurs 4 du réseau selon un premier mode de réalisation de l'invention.Image display screen and method for addressing this screen. The invention relates to an image display screen and a method for addressing this screen. In particular, the invention relates to a display screen of the type based on organic electroluminescent materials with active matrix etched on amorphous silicon (Si-a). Thin Film Transistor in hydrogenated amorphous silicon have advantages compared to thin film transistors in polycrystalline silicon (p-Si) for the design of screens based on organic electroluminescent materials because they are more easy to manufacture and they exhibit luminance uniformity on relatively large samples. However, the trigger threshold voltage of amorphous silicon transistors drifts over time during the prolonged application of a voltage between their gate and their source. This derivation of the trigger threshold voltages results on the one hand, in a process of marking the image on the screen and on the other hand, changes in the luminance of the screen over time. It is known in particular from document US 2003/052614, a screen of the aforementioned type comprising addressing control means suitable for applying, during each image frame, to the current modulator of each transmitter of this screen and to using the same and unique addressing circuit of this transmitter, alternately an addressing voltage representative of an image datum and a voltage of reverse polarity to the polarity of the addressing voltage. However, this architecture and this control mode is likely to cause a drop in luminance of the screen and a phenomenon of flickering on the screen, since the transmission time is reduced during each frame. It is known in particular from document US Pat. No. 6,011,529 (see in particular FIG. 9) and WO 2004/051617, a screen of the aforementioned type comprising addressing control means suitable for applying, during each image frame, to the current modulator of each transmitter of this screen and using at least one of the plurality of addressing circuits of this transmitter, an addressing voltage representative of a datum of image always showing the same polarization. The object of the invention is to provide an alternative screen which exhibits small variations in luminance over time. To this end, the subject of the invention is an image display screen comprising: - light emitters (4) distributed along rows of emitters and columns of emitters to form a network of emitters, - means for controlling the transmission of the transmitters of the network comprising: a) a first addressing circuit of a transmitter, associated with each transmitter of the network for controlling the current passing through, said circuit comprising: - a first modulator of current capable of supplying said transmitter, said first modulator comprising a gate electrode and two current flow electrodes, - a first storage capacity capable of imposing a potential on the gate electrode of the first current modulator, b) for each transmitter, at least a second addressing circuit of a transmitter, said first and said second addressing circuits being associated in parallel with the same transmitter, said second circuit comprising: - a second modulator current from said transmitter comprising a gate electrode and two current flow electrodes, - a second storage capacity capable of storing a potential at the gate electrode of the second current modulator; c) addressing control means being able to apply an addressing voltage to said first storage capacity, and to said second storage capacity, said addressing voltage being representative of image data, and being adapted to optionally activate the first or second addressing circuits to supply the transmitter with current according to said image data. The screen is characterized in that the addressing control means are able to impose a bias voltage of choice on said first current modulator or on said second current modulator, said bias voltage having a polarity opposite to the polarity of said addressing voltage. According to particular embodiments, the display screen includes one or more of the following characteristics: - the addressing control means are adapted to apply to said first current modulator first the addressing voltage to start an activation phase of the first addressing circuit, then the bias voltage to start a bias phase of the first addressing circuit; the addressing control means are suitable for applying to said second current modulator first the addressing voltage to start an activation phase of the second addressing circuit, then the bias voltage to start a bias phase of the second addressing circuit, the activation phase of the first addressing circuit is synchronous with the polarization phase of the second addressing circuit and the activation phase of the second addressing circuit is synchronous with the polarization phase the first addressing circuit; the control means comprise selection control means comprising: for each first addressing circuit of a transmitter, a first selection switch able to control the transmission of said addressing voltage or of said bias voltage in function of a selection voltage to said first storage capacity and said grid of said first current modulator for selecting said transmitter, - for each second addressing circuit of the same transmitter, a second selection switch capable of controlling the transmission of said addressing voltage or said bias voltage as a function of said selection voltage towards said second storage capacity and said grid of said second current modulator for selecting said transmitter, and - means for controlling the first and second selection switches; - the control means also comprise, for each line of transmitters, a first and a second selection electrodes connected to the first, respectively to the second selection switches for their control, and a selection control unit capable of transmitting alternately, d firstly said selection voltage at said first selection electrode, then said selection voltage at said second selection electrode; the addressing control means comprise an addressing electrode for each column of transmitters, the first and second selection switches being connected to said addressing electrode, and an addressing control unit capable of sending alternately said addressing voltage and said bias voltage on said addressing electrode; the piloting means also comprise a selection electrode for each row of transmitters, the first and second selection switches being connected to said selection electrode for their control, and a selection piloting unit capable of sending said voltage of selection concomitantly with the first and second selection switches; the addressing control means comprise, for each column of transmitters, a first and a second addressing electrodes connected to the first, respectively to the second selection switches and an addressing piloting unit able to send simultaneously to the first addressing electrode and on the second addressing electrode of your choice, said addressing voltage or said bias voltage. The invention also relates to a method for addressing a display screen of this type, characterized in that it comprises, for the control of each transmitter: - a phase of activation of the first addressing circuit for supply the transmitter with current, - a bias phase of the second addressing circuit to derive the trigger threshold voltage of the second modulator, - an activation phase of the second addressing circuit to supply current to the transmitter, - a bias phase of the first addressing circuit to derive the trigger threshold voltage of the first modulator, and the activation phase of the first addressing circuit is concomitant with the bias phase of the second addressing circuit and the activation phase of the second addressing circuit is concomitant with the bias phase of the first addressing circuit. According to particular embodiments, the display method comprises one or more of the following characteristics: - one or more phases of activation of the first addressing circuit are followed by at least one phase of polarization of the first circuit addressing and one or more activation phases of the second addressing circuit are followed by at least one bias phase of the second addressing circuit; the method comprises: a step of programming the addressing of said first storage capacity by applying to said capacity an addressing voltage representative of an image datum, a step of programming polarization of said first modulator current by applying a bias voltage to said modulator, said bias voltage having a polarity opposite to the polarity of the potential stored by the first storage capacity, - a step for programming the bias of said second current modulator by applying to said modulator of said bias voltage, and - a step of programming the addressing of said second storage capacity by applying said capacity of said addressing voltage to said capacity; the polarization programming step of said first current modulator is followed by the addressing programming step of the second storage capacity and alternatively the programming step of polarization of said second current modulator is followed by the step of programming the addressing of the first storage capacity; and said polarization programming step of said second current modulator is concomitant with said addressing programming step of said first storage capacity and said polarization programming step of said first current modulator is concomitant with said programming step of addressing of said second storage capacity. The invention will be better understood on reading the description which follows, given solely by way of example and made with reference to the drawings, in which: - Figure 1 is a schematic view showing a transmitter and control means the emission of this screen transmitter according to a first embodiment of the invention; - Figures 2A to 2F are graphs representing the evolution over time of different voltages and currents during the addressing process performed by the device according to the invention; in particular, FIG. 2A is a graph representing the selection voltage applied to a first selection electrode; - Figure 2B is a graph showing the voltage applied to a second selection electrode; - Figure 2C is a graph showing the voltage applied to a addressing electrode; FIG. 2D is a graph representing the voltage applied to the terminals of a first storage capacity and the voltage applied to the terminals of a second storage capacity; FIG. 2E is a graph representing the drain current passing through a first current modulator and the drain current passing through a second current modulator; - Figure 2F is a graph showing the current flowing through a transmitter; - Figure 3 is a schematic view showing a transmitter and means for controlling the transmission of this transmitter from the screen according to a second embodiment of the invention; - Figures 4A to 4F are graphs representing the evolution over time of different voltages and currents during the addressing process performed by the device according to the second embodiment of the invention; in particular, FIG. 4A is a graph representing the selection voltage applied to a selection electrode; - Figure 4B is a graph showing the voltage applied to a first addressing electrode; - Figure 4C is a graph showing the voltage applied to a second addressing electrode; - Figure 4D is a graph showing the voltage across a first storage capacity and the voltage across a second storage capacity; FIG. 4E is a graph representing the drain current passing through a first current modulator and the drain current passing through a second current modulator; and FIG. 4F is a graph representing the current passing through a transmitter. The display screen according to the invention is an active matrix screen comprising light emitters distributed in rows and columns to form a network of emitters. The display screen emitters are organic light emitting diodes known by the acronym OLED. They are each associated with a pixel when the screen is monochrome or with a sub-pixel when the screen is polychrome. They emit a light intensity directly proportional to the current flowing through them. FIG. 1 represents means 2 for controlling the transmission of transmitters 4 from the network according to a first embodiment of the invention.
Dans un souci de simplification, seuls les moyens de commande de l'adressage d'un unique émetteur ont été illustrés sur cette figure. Les moyens de commande 2 comprennent un premier circuit d'adressage 6 relié à un émetteur 4 du réseau, des moyens de commande d'adressage 8 d'une colonne d'émetteurs, des moyens de commande de sélection 10 d'une ligne d'émetteurs, un système de commande 11 et un second circuit d'adressage 12 relié également à un émetteur 4. Le premier circuit d'adressage 6 comprend un modulateur de courant 14, une capacité de stockage 16 et un interrupteur de sélection 18. Le modulateur 14 et l'interrupteur 18 sont des transistors en couches minces en Silicium amorphe hydrogéné. Plus précisément, ce sont des transistors de type n. Ils comportent un drain, une grille et une source et sont aptes à être traversés par un courant circulant de leur drain vers leur source, lorsqu'une tension supérieure ou égale à leur tension de seuil de déclenchement est appliquée entre leur grille et leur source. Alternativement, des transistors de type p peuvent également être utilisés. Dans ce cas, les transistors 14 et 18 sont aptes à être traversés par un courant circulant de leur source vers leur drain. Le drain du modulateur 14 est connecté à la cathode de l'émetteur 4. L'anode de l'émetteur 4 est connectée à un générateur de tension continue Vdd propre à l'alimenter en puissance. La source du modulateur 14 est raccordée à une électrode de masse ou à une tension négative. La grille du modulateur 1.4 est raccordée à la source de l'interrupteur 18 et à une borne de la capacité de stockage 16. L'autre borne de la capacité 16 est connectée à une électrode de masse. La grille de l'interrupteur 18 est branchée aux moyens de commande de sélection 10 et son drain est raccordé aux moyens de commande d'adressage 8. Les moyens de commande d'adressage 8 d'une colonne d'émetteurs comprennent une électrode d'adressage 20 par colonne d'émetteurs et une unité de pilotage d'adressage 22. L'électrode 20 est branchée d'une part à l'unité de pilotage 22 et, d'autre part au drain de l'interrupteur 18 des premiers circuits d'adressage 6 d'une colonne d'émetteurs. Les moyens de commande de sélection 10 comprennent une première électrode de sélection 24 et une seconde électrode de sélection 26 pour chaque ligne d'émetteurs ainsi qu'une unité de pilotage de sélection 28. La première électrode de sélection 24 est reliée à l'unité de pilotage 28 et à la grille de l'interrupteur 18 des premiers circuits d'adressage 6 d'une ligne d'émetteurs. La seconde électrode 26 est connectée à l'unité de pilotage 28 et à la grille de l'interrupteur 38 des seconds circuits d'adressage 12 d'une ligne d'émetteurs. Le système de commande 11 est connecté à l'unité de pilotage d'adressage 22 et à l'unité de pilotage de sélection 28. Le second circuit d'adressage 12 comporte les mêmes composants que le premier circuit d'adressage 6 à savoir un modulateur de courant 34, une capacité de stockage 36 et un interrupteur de sélection 38. Ces composants sont connectés entre eux de la même manière que dans le premier circuit d'adressage 6 et ne seront pas décrits de manière détaillée. Spécifiquement, le modulateur de courant 34 du second circuit d'adressage 12 est raccordé à la cathode de l'émetteur 4 au noeud 32. Le drain de l'interrupteur 38 est raccordé à la même électrode d'adressage 20 que l'interrupteur 18 et sa grille est connectée à la seconde électrode de sélectionFor the sake of simplification, only the means for controlling the addressing of a single transmitter have been illustrated in this figure. The control means 2 comprise a first addressing circuit 6 connected to a transmitter 4 of the network, addressing control means 8 of a column of transmitters, selection control means 10 of a line of transmitters, a control system 11 and a second addressing circuit 12 also connected to a transmitter 4. The first addressing circuit 6 comprises a current modulator 14, a storage capacity 16 and a selection switch 18. The modulator 14 and the switch 18 are thin film transistors made of hydrogenated amorphous silicon. More precisely, these are n-type transistors. They have a drain, a gate and a source and are capable of being traversed by a current flowing from their drain to their source, when a voltage greater than or equal to their trigger threshold voltage is applied between their gate and their source. Alternatively, p-type transistors can also be used. In this case, the transistors 14 and 18 are capable of being traversed by a current flowing from their source to their drain. The drain of the modulator 14 is connected to the cathode of the emitter 4. The anode of the emitter 4 is connected to a DC voltage generator V dd capable of supplying it with power. The source of the modulator 14 is connected to a ground electrode or to a negative voltage. The gate of the modulator 1.4 is connected to the source of the switch 18 and to a terminal of the storage capacity 16. The other terminal of the capacity 16 is connected to a ground electrode. The gate of the switch 18 is connected to the selection control means 10 and its drain is connected to the addressing control means 8. The addressing control means 8 of a column of transmitters comprise an electrode addressing 20 by column of transmitters and an addressing control unit 22. The electrode 20 is connected on the one hand to the control unit 22 and, on the other hand to the drain of the switch 18 of the first circuits addressing 6 of a column of transmitters. The selection control means 10 comprise a first selection electrode 24 and a second selection electrode 26 for each row of transmitters as well as a selection control unit 28. The first selection electrode 24 is connected to the control unit 28 and to the grid of the switch 18 of the first addressing circuits 6 of a line of transmitters. The second electrode 26 is connected to the control unit 28 and to the grid of the switch 38 of the second addressing circuits 12 of a line of transmitters. The control system 11 is connected to the addressing control unit 22 and to the selection control unit 28. The second addressing circuit 12 comprises the same components as the first addressing circuit 6, namely a current modulator 34, a storage capacity 36 and a selection switch 38. These components are connected together in the same way as in the first addressing circuit 6 and will not be described in detail. Specifically, the current modulator 34 of the second addressing circuit 12 is connected to the cathode of the emitter 4 at node 32. The drain of the switch 38 is connected to the same addressing electrode 20 as the switch 18 and its grid is connected to the second selection electrode
26. Le système de commande 11 est apte à transmettre des données numériques d'image et des données relatives à la tension de polarisation à l'unité de pilotage 22 et un signal périodique de sélection à l'unité de pilotage 28 à une fréquence prédéfinie. L'unité de pilotage d'adressage 22 est apte à transmettre une tension d'adressage VD représentative d'une donnée d'image à l'ensemble des émetteurs d'une colonne via l'électrode 20. L'unité de pilotage d'adressage 22 est également apte à appliquer à l'électrode 20 une tension, dite tension de polarisation Vp, d'une polarisation inverse à la polarisation de la tension d'adressage. Cette tension est une tension négative prédéfinie d'une durée prédéterminée. Préférentiellement, la tension de polarisation Vp est comprise entre - 2 Volts et - 25 Volts. D'une manière générale, on appelle tension de polarisation inverse ou négative, une différence de potentiel Vgs entre les électrodes de grille et de source du modulateur qui est inférieure à 0 Volt : Vgs < 0V. ιυ26. The control system 11 is able to transmit digital image data and data relating to the bias voltage to the control unit 22 and a periodic selection signal to the control unit 28 at a predefined frequency. . The addressing control unit 22 is capable of transmitting an addressing voltage V D representative of image data to all of the emitters of a column via the electrode 20. The control unit d addressing 22 is also capable of applying to the electrode 20 a voltage, called the bias voltage V p , from a reverse bias to the bias of the addressing voltage. This voltage is a predefined negative voltage of a predetermined duration. Preferably, the bias voltage V p is between - 2 Volts and - 25 Volts. In general, a reverse or negative bias voltage is called a potential difference V gs between the gate and source electrodes of the modulator which is less than 0 Volt: V gs <0V. ιυ
L'unité de pilotage 28 est apte à appliquer une tension de sélection périodique Vsi, VS2 à la grille de l'interrupteur 18 des premiers circuits d'adressage 6 d'une ligne d'émetteurs ou à la grille de l'interrupteur 38 des seconds circuits d'adressage 12 de la même ligne d'émetteurs pour autoriser l'application de la tension d'adressage VD ou de la tension de polarisation Vp à la grille du modulateur 14 du premier circuit d'adressage 6 ou à la grille du modulateur 34 second circuit d'adressage 12. Les figures 2A à 2F illustrent le procédé d'adressage d'un écran d'affichage selon le premier mode de réalisation de l'invention. Ce procédé comprend une étape de programmation de polarisationThe control unit 28 is able to apply a periodic selection voltage Vsi, V S 2 to the grid of the switch 18 of the first addressing circuits 6 of a row of transmitters or to the grid of the switch 38 of the second addressing circuits 12 of the same line of transmitters to authorize the application of the addressing voltage V D or of the bias voltage V p to the gate of the modulator 14 of the first addressing circuit 6 or to the gate of the modulator 34 second addressing circuit 12. FIGS. 2A to 2F illustrate the method of addressing a display screen according to the first embodiment of the invention. This method includes a polarization programming step.
A du modulateur 34 du second circuit d'adressage 12. L'unité de pilotage de sélection 28 transmet à la seconde électrode 26, une tension de sélection Vs2, tel qu'illustré sur la figure 2B. L'interrupteur de sélection 38 est débloqué par l'application à sa grille de cette tension de sélection VS2. Simultanément, l'unité de pilotage d'adressage 22 applique à l'électrode d'adressage 20 une tension de polarisation Vp d'une polarité négative (Vgs < 0). La tension de polarisation Vp est appliquée à la grille du modulateur de courant 34 et à une borne de la capacité de stockage 36. Le courant de drain Id2 qui traversait le modulateur 34 pour alimenter l'émetteur 4 durant la trame précédente, tend maintenant vers 0 lors de cette nouvelle trame ainsi que le montre la courbe en pointillés de la figure 2E. Parallèlement, la capacité de stockage 36 ayant préalablement stockée une tension VD appliquée lors de la trame précédente, se polarise à la tension de polarisation V tel qu'illustré sur la figure 2D ; comme l'indique la courbe en pointillés de cette figure, la capacité de stockage 36 maintient cette tension de polarisation à la grille du modulateur 34 pendant une phase de polarisation du second circuit d'adressage 12 et jusqu'à la fin de la prochaine étape de programmation du modulateur 34. Les étapes B, C et D constituent ensemble une phase de polarisation du second circuit d'adressage 12. La tension de seuil de déclenchement du modulateur 34 ayant subi une dérive par l'application d'une tension d'adressage au cours de la trame d'image précédente, est à nouveau dérivée pendant la phase de polarisation et durant toute la durée de la nouvelle trame, par l'application de la tension de polarisation Vp mais dans un sens opposé à sa dérive précédente. La tension de polarisation appliquée à la grille du modulateur 34 pendant la nouvelle trame permet d'inverser la dérive de sa tension de seuil de déclenchement et de replacer celle-ci à sa valeur initiale, c'est-à-dire à la valeur qu'elle avait avant d'avoir été dérivée par l'application d'une tension d'adressage à sa grille lors de la trame précédente. Au cours de l'étape B de programmation d'adressage du modulateur 14 du premier circuit d'adressage 6, l'unité de pilotage de sélection 28 génère une tension de sélection Vsi et l'applique à la première électrode 24. En même temps, l'unité de pilotage d'adressage 22 transmet à l'électrode d'adressage 20 une tension d'adressage VDa représentative d'une donnée d'image. L'interrupteur de sélection 18, au croisement de l'électrode d'adressage 20 et de la première électrode de sélection 24, est débloqué et transmet la tension d'adressage VDa au modulateur 14 et à la capacité de stockage 16 du premier circuit d'adressage 6. Comme la tension d'adressage Voa est supérieure à la tension de seuil de déclenchement du modulateur 14, un courant de drain Idi s'établit entre le drain et la source du modulateur 14 et traverse donc l'émetteur 4 comme illustré à la figure 2F. La capacité 16 stocke un potentiel représentatif de la tension d'adressage VDa à la grille du modulateur 14 pour maintenir la luminance de l'émetteur 4 pendant un intervalle de temps correspondant à la durée d'une trame d'image. Ainsi, l'émetteur 4 émet de la lumière pendant l'étape C jusqu'à la fin de la trame d'image. Pendant les étapes B, C et D, on voit donc que l'émetteur 4 est alimenté en courant par le premier circuit d'adressage 6. Les étapes B, C et D forment donc ensemble une phase d'activation du premier circuit d'adressage 6. Pendant une étape de programmation de polarisation D du modulateur 14 du premier circuit d'adressage 6, l'unité de pilotage 28 de sélection transmet à la première électrode 24 une tension de sélection Vsi. Conjointement à l'application d'une tension de sélection, l'unité de pilotage 22 d'adressage applique à l'électrode 20 une tension de polarisation Vp. L'interrupteur de sélection 18, au croisement de la première électrode 24 et de l'électrode d'adressage 20, est débloqué et transmet cette fois la tension de polarisation Vp au modulateur 14 et à la capacité de stockage 16. La capacité de stockage se décharge et stocke les charges transmises par la tension de polarisation pendant une phase de polarisation E, F du premier circuit d'adressage 6, tel qu'illustré sur la figure 2D. Le courant de drain lai de la trame précédente cesse de traverser le modulateur 14. La tension de seuil du déclenchement du modulateur 14 qui a dérivé et augmenté au cours de la trame d'image va diminuer au cours de la nouvelle trame et notamment au cours de l'étape F. La trame d'image suivante démarre par une étape de programmation d'adressage E du modulateur 34 du second circuit d'adressage 12. Pendant cette étape, l'unité de pilotage 28 de sélection applique à l'électrode 26 une tension de sélection Vs2. L'unité de pilotage d'adressage 22 applique parallèlement à l'électrode 20 une tension d'adressage VDb- L'interrupteur 38 du second circuit d'adressage 12 est débloqué et la tension d'adressage VDt>, représentative d'une donnée d'image, est appliquée à la grille du modulateur 34 et à la borne de la capacité de stockage 36. Un courant de drain ld2 est généré entre le drain et la source du modulateur 34. Ce courant a une amplitude proportionnelle à la valeur de la donnée d'image à émettre pendant cette trame d'image. Ce courant traverse l'émetteur de lumière 4 pendant l'étape F jusqu'à la fin de la trame d'image. Pendant les étapes E et F, on voit donc que l'émetteur 4 est alimenté en courant par le second circuit d'adressage 12. Les étapes E et F forment donc ensemble une phase d'activation du second circuit d'adressage 12. En conséquence, le système de commande 11 et les unités de pilotage 22 et 28 commandent l'adressage des tensions de sélection, d'adressage et de polarisation de sorte que : - une tension d'adressage de polarité positive, est appliquée à la grille du modulateur 14 du premier circuit d'adressage 6 pour alimenter l'émetteur 4 et consécutivement, une tension de polarisation de polarité négative est appliquée à la grille du modulateur 34 du second circuit d'adressage 12 pour compenser la dérivation de sa tension de seuil de déclenchement ; - puis inversement, une tension d'adressage de polarité positive, est appliquée à la grille du modulateur 34 du second circuit d'adressage 12 pour alimenter l'émetteur 4 et consécutivement, une tension de polarisation de polarité négative est appliquée à la grille du modulateur 14 du premier circuit d'adressage 6 pour compenser la dérivation de sa tension de seuil de déclenchement. D'une trame d'image à l'autre, l'émetteur 4 est alimenté en courant tour à tour par le premier modulateur 14 pendant une phase d'activation du premier circuit d'adressage, puis par le second modulateur 34 pendant une phase d'activation du second circuit d'adressage. Les tensions de seuil de déclenchement du modulateur 14 du premier circuit d'adressage et du modulateur 34 du second circuit d'adressage sont augmentées puis diminuées tour à tour à chaque trame d'image. Un tel dispositif permet donc avantageusement de compenser la dérive de tension de seuil de déclenchement des modulateurs du panneau. Un émetteur 4 et les moyens de commande 40 de son émission selon un second mode de réalisation de l'invention, sont représentés sur la figure 3. Dans ce mode de réalisation, les moyens de commande 40 comprennent des premiers circuits d'adressage 6 et des seconds circuits d'adressage 12, reliés chacun à une émetteur 4 du réseau, des moyens de commande d'adressage 42 d'une colonne d'émetteurs, des moyens de commande de sélection 44 d'une ligne d'émetteurs et un système de commande 56. Les premiers 6 et les seconds 12 circuits d'adressage comprennent les mêmes composants, reliés de la même façon que les circuits d'adressage décrits en relation avec la figure 1. Ils sont identifiés par les mêmes références que sur la figure 1 et ne seront plus décrits ci-après. Les moyens de commande 42 d'adressage comprennent une unité de pilotage d'adressage 46, une première électrode 48 d'adressage et une seconde électrode 50 d'adressage pour chaque colonne d'émetteurs. La première électrode 48 d'adressage est reliée à l'unité de pilotage 46 et au drain de l'interrupteur 18 de l'ensemble des premiers circuits d'adressage 6 d'une colonne d'émetteurs. La seconde électrode 50 d'adressage est reliée à l'unité de pilotage 46 et au drain de l'interrupteur 38 de l'ensemble des seconds circuits d'adressage 12 d'une colonne d'émetteurs. L'unité de pilotage 46 d'adressage est apte à envoyer une tension d'adressage VDι sur la première électrode 48 et de manière concomitante une tension d'adressage VD2 sur la seconde électrode 50. Les moyens de commande 44 de sélection comprennent une unité de pilotage 54 de sélection et pour chaque ligne d'émetteurs une unique électrode 52 de sélection. L'électrode 52 de sélection est connectée à l'unité de pilotage 54, à la grille de l'interrupteur 18 des premiers circuits d'adressage 6 et à la grille de l'interrupteur 38 des seconds circuits d'adressage 12 d'une ligne d'émetteurs. Le système de commande 56 est connecté à l'unité de pilotage 54 ainsi qu'à l'unité de pilotage 46. Ce système de commande 56 est apte à transmettre à l'unité de pilotage 46 des données numériques d'images et des données relatives à la tension de polarisation. Il est également apte à transmettre à l'unité de pilotage 54 un signal périodique de sélection. Le procédé d'adressage d'un écran d'affichage selon le second mode de réalisation de l'invention est illustré sur les figures 4A à 4F. Ce procédé comprend une étape G de programmation d'adressage de la capacité 16 et de programmation de polarisation simultanée du modulateur 34. L'unité de pilotage 46 transmet une tension d'adressage VDa représentative d'une donnée d'image à la première électrode 48 et une tension de polarisation Vp à la seconde électrode 50. Parallèlement, l'unité de pilotage 54 transmet une tension de sélection Vs sur l'électrode de sélection 52. L'interrupteur 18 du premier circuit d'adressage et l'interrupteur 38 du second circuit de programmation sont débloqués de sorte que d'une part, la tension de polarisation Vp est appliquée à la grille du modulateur 34 et à la borne de la capacité 36 et d'autre part, la tension d'adressage Voa est appliquée à la grille du modulateur 14 et à une borne de la capacité de stockage 16. La capacité de stockage 36 se décharge puis se charge à un potentiel négatif égal à la tension de polarisation Vp. Cette tension maintenue à la grille du modulateur 34 par la capacité de stockage 36, vise à diminuer progressivement la tension de seuil de déclenchement du modulateur 34 notamment au cours de l'étape H. Comme l'indique la courbe en pointillés de la figure 4E, le courant de drain I 2 s'annule et reste nul pendant l'étape H. La capacité 16 se charge au potentiel VD3 et un courant de drain Idi s'établit entre le drain et la source du modulateur 14. L'émetteur 4 est alimenté par le courant Idi pendant l'étape H jusqu'à la fin de la trame d'image. Pendant les étapes G et H, l'émetteur 4 est donc alimenté en courant par le premier circuit d'adressage 6; les étapes G et H forment donc ensemble une phase d'activation du premier circuit d'adressage. Par ailleurs, pendant les étapes G et H, la tension de polarisation est appliquée à la grille du modulateur 34 pour compenser la dérive de sa tension de seuil de déclenchement. Les étapes G et H forment donc également une phase de polarisation du second circuit d'adressage. Pendant une étape I de programmation d'adressage de la capacité de stockage 36 et de programmation de polarisation simultanée du modulateurA of the modulator 34 of the second addressing circuit 12. The selection control unit 28 transmits to the second electrode 26, a selection voltage V s2, as illustrated in FIG. 2B. The selection switch 38 is released by applying this selection voltage V S2 to its gate. Simultaneously, the addressing control unit 22 applies to the addressing electrode 20 a bias voltage V p of a negative polarity (V gs <0). The bias voltage V p is applied to the grid of the current modulator 34 and to a terminal of the storage capacity 36. The drain current Id2 which passed through the modulator 34 to supply the transmitter 4 during the previous frame, now tends towards 0 during this new frame as shown by the dotted curve in FIG. 2E. In parallel, the storage capacity 36 having previously stored a voltage V D applied during the previous frame, is biased at the bias voltage V as illustrated in FIG. 2D; as indicated by the dotted curve in this figure, the storage capacity 36 maintains this bias voltage at the gate of the modulator 34 during a bias phase of the second addressing circuit 12 and until the end of the next step programming the modulator 34. The steps B, C and D together constitute a phase of polarization of the second addressing circuit 12. The triggering threshold voltage of the modulator 34 having undergone a drift by the application of a voltage of addressing during the previous image frame, is again derived during the polarization phase and throughout the duration of the new frame, by applying the bias voltage V p but in a direction opposite to its previous drift. The bias voltage applied to the gate of the modulator 34 during the new frame makes it possible to reverse the drift of its trigger threshold voltage and to return it to its initial value, that is to say to the value that 'it had before being derived by applying an addressing voltage to its grid in the previous frame. During the programming programming step B of the modulator 14 of the first addressing circuit 6, the selection control unit 28 generates a selection voltage Vsi and applies it to the first electrode 24. At the same time , the addressing control unit 22 transmits to the addressing electrode 20 an addressing voltage V Da representative of an image datum. The selection switch 18, at the intersection of the addressing electrode 20 and the first selection electrode 24, is released and transmits the addressing voltage V Da to the modulator 14 and to the storage capacity 16 of the first circuit as the addressing voltage Vo a is greater than the triggering threshold voltage of the modulator 14, a drain current Idi is established between the drain and the source of the modulator 14 and therefore crosses the emitter 4 as shown in Figure 2F. The capacitor 16 stores a potential representative of the addressing voltage V Da at the gate of the modulator 14 to maintain the luminance of the transmitter 4 during a time interval corresponding to the duration of an image frame. Thus, the emitter 4 emits light during step C until the end of the image frame. During steps B, C and D, it can therefore be seen that the transmitter 4 is supplied with current by the first addressing circuit 6. Steps B, C and D therefore together form an activation phase of the first circuit addressing 6. During a polarization programming step D of the modulator 14 of the first addressing circuit 6, the selection control unit 28 transmits to the first electrode 24 a selection voltage Vsi. In conjunction with the application of a selection voltage, the addressing control unit 22 applies a bias voltage V p to the electrode 20. The selection switch 18, at the intersection of the first electrode 24 and the addressing electrode 20, is released and this time transmits the bias voltage V p to the modulator 14 and to the storage capacity 16. The capacity of storage discharges and stores the charges transmitted by the bias voltage during a bias phase E, F of the first addressing circuit 6, as illustrated in FIG. 2D. The drain current lai of the previous frame stops passing through the modulator 14. The threshold voltage for triggering the modulator 14 which has drifted and increased during the image frame will decrease during the new frame and in particular during from step F. The following image frame starts with an addressing programming step E of the modulator 34 of the second addressing circuit 12. During this step, the selection control unit 28 applies to the electrode 26 a selection voltage V s2 . The addressing control unit 22 applies in parallel to the electrode 20 an addressing voltage V Db - The switch 38 of the second addressing circuit 12 is released and the addressing voltage V D t > , representative d image data is applied to the grid of the modulator 34 and to the terminal of the storage capacity 36. A drain current l d2 is generated between the drain and the source of the modulator 34. This current has a proportional amplitude to the value of the image data to be transmitted during this image frame. This current flows through the light emitter 4 during step F until the end of the image frame. During steps E and F, it can therefore be seen that the transmitter 4 is supplied with current by the second addressing circuit 12. Steps E and F therefore together form an activation phase of the second addressing circuit 12. In Consequently, the control system 11 and the control units 22 and 28 control the addressing of the selection, addressing and bias voltages so that: - an addressing voltage of positive polarity is applied to the grid of the modulator 14 of the first addressing circuit 6 to supply the transmitter 4 and consecutively, a bias voltage of negative polarity is applied to the gate of the modulator 34 of the second circuit addressing 12 to compensate for the derivation of its trigger threshold voltage; - then inversely, an addressing voltage of positive polarity is applied to the gate of the modulator 34 of the second addressing circuit 12 to supply the transmitter 4 and, consecutively, a bias voltage of negative polarity is applied to the gate of the modulator 14 of the first addressing circuit 6 to compensate for the derivation of its trigger threshold voltage. From one image frame to another, the transmitter 4 is supplied with current in turn by the first modulator 14 during an activation phase of the first addressing circuit, then by the second modulator 34 during a phase activation of the second addressing circuit. The trigger threshold voltages of the modulator 14 of the first addressing circuit and of the modulator 34 of the second addressing circuit are increased and then decreased in turn at each image frame. Such a device therefore advantageously makes it possible to compensate for the drift in the triggering threshold voltage of the panel modulators. A transmitter 4 and the control means 40 for its transmission according to a second embodiment of the invention, are shown in FIG. 3. In this embodiment, the control means 40 comprise first addressing circuits 6 and second addressing circuits 12, each connected to a transmitter 4 of the network, addressing control means 42 of a column of transmitters, selection control means 44 of a row of transmitters and a system 56. The first 6 and the second 12 addressing circuits comprise the same components, connected in the same way as the addressing circuits described in connection with FIG. 1. They are identified by the same references as in the FIG. 1 and will no longer be described below. The addressing control means 42 comprise an addressing control unit 46, a first addressing electrode 48 and a second addressing electrode 50 for each column of transmitters. The first addressing electrode 48 is connected to the control unit 46 and to the drain of the switch 18 of all of the first addressing circuits 6 of a column of transmitters. The second addressing electrode 50 is connected to the control unit 46 and to the drain of the switch 38 of all of the second addressing circuits 12 of a column of transmitters. The addressing control unit 46 is able to send an addressing voltage V D ι to the first electrode 48 and concomitantly an addressing voltage V D2 to the second electrode 50. The control means 44 for selection comprise a selection control unit 54 and for each row of transmitters a single selection electrode 52. The selection electrode 52 is connected to the control unit 54, to the grid of the switch 18 of the first addressing circuits 6 and to the grid of the switch 38 of the second addressing circuits 12 of a line of transmitters. The control system 56 is connected to the control unit 54 as well as to the control unit 46. This control system 56 is able to transmit to the control unit 46 digital image data and data relating to the bias voltage. It is also able to transmit to the control unit 54 a periodic selection signal. The method for addressing a display screen according to the second embodiment of the invention is illustrated in FIGS. 4A to 4F. This method comprises a step G for programming the addressing of the capacitor 16 and for programming the simultaneous polarization of the modulator 34. The control unit 46 transmits an addressing voltage V Da representative of an image datum at the first electrode 48 and a bias voltage V p at the second electrode 50. At the same time, the control unit 54 transmits a selection voltage V s on the selection electrode 52. The switch 18 of the first addressing circuit and l switch 38 of the second programming circuit are released so that on the one hand, the bias voltage V p is applied to the gate of the modulator 34 and to the terminal of the capacitor 36 and on the other hand, the voltage of Voa addressing is applied to the grid of the modulator 14 and to a terminal of the storage capacity 16. The storage capacity 36 discharges and then charges at a negative potential equal to the bias voltage V p . This voltage maintained at the gate of the modulator 34 by the storage capacity 36, aims to gradually decrease the trigger threshold voltage of the modulator 34 in particular during step H. As indicated by the dotted curve of FIG. 4E , the drain current I 2 is canceled and remains zero during step H. The capacitor 16 charges at the potential VD 3 and a drain current I d i is established between the drain and the source of the modulator 14. L emitter 4 is supplied with current I d i during step H until the end of the image frame. During steps G and H, the transmitter 4 is therefore supplied with current by the first addressing circuit 6; steps G and H therefore together form an activation phase of the first addressing circuit. Furthermore, during steps G and H, the bias voltage is applied to the gate of the modulator 34 to compensate for the drift of its trigger threshold voltage. Steps G and H therefore also form a phase of polarization of the second addressing circuit. During a step I of programming the addressing of the storage capacity 36 and programming the simultaneous polarization of the modulator
14, l'unité de pilotage 46 transmet une tension de polarisation Vp à la première électrode 48 et une tension d'adressage VDb représentative d'une donnée d'image à la seconde électrode 50. Les interrupteurs 18 et 38 sont simultanément ouverts par application de la tension de sélection Vs à l'électrode 52. La tension de polarisation Vp est transmise à la grille du modulateur 14 et à la borne de la capacité 16. La capacité 16 se décharge puis se charge négativement. Comme l'indique la courbe en trait plein de la figure 4E, le courant de drain ld1 s'annule et reste nul pendant l'étape J. Pendant les étapes I et J, la tension de polarisation Vp est appliquée à la grille du modulateur 14. Les étapes I et J, forment donc ensemble une phase de polarisation du premier circuit d'adressage 6. Conjointement, la tension d'adressage VD est appliquée à la grille du modulateur 34 et à une borne de la capacité 36. Cette tension, maintenue à la grille du modulateur 34 par la capacité 36, génère un courant de drain Id2 qui alimente l'émetteur 4 pendant l'étape J et jusqu'à la prochaine étape de programmation d'une nouvelle donnée d'image. Pendant les étapes I et J, l'émetteur 4 est alimenté en courant par le second circuit d'adressage 12 ; ces étapes forment donc ensemble une phase d'activation du second circuit d'adressage. En conséquence, le système de commande 56 et les unités de pilotage 46 et 54 commandent l'adressage des tensions de sélection, d'adressage et de polarisation de sorte que : - une tension d'adressage de polarité positive, est appliquée à la grille du modulateur 14 du premier circuit d'adressage 6 pour alimenter l'émetteur 4 et simultanément, une tension de polarisation de polarité négative est appliquée à la grille du modulateur 34 du second circuit d'adressage 12 pour compenser la dérive de sa tension de seuil de déclenchement ; - puis inversement, une tension d'adressage de polarité positive est appliquée à la grille du modulateur 34 du second circuit d'adressage 12 pour alimenter l'émetteur 4 et simultanément, une tension de polarisation de polarité négative est appliquée à la grille du modulateur 14 du premier circuit d'adressage 6 pour compenser la dérive de sa tension de seuil de déclenchement. L'émetteur 4 est ainsi alimenté tour à tour par le courant modulé, par le modulateur 14, puis par le modulateur 34. Les premier 6 et second 12 circuits d'adressage sont alternativement activés pour alimenter en courant l'émetteur 4. Quand le modulateur 14 alimente l'émetteur 4, le modulateur 34 est polarisé par application à sa grille d'une tension de polarisation correspondant à une tension négative élevée pour que la tension de seuil de déclenchement du modulateur 34 dérivée au cours de la phase précédente retrouve sa valeur initiale. Inversement, quand le modulateur 34 alimente l'émetteur 4, le modulateur 14 est polarisé par cette même tension de polarisation négative pour que sa tension de seuil de déclenchement ayant au préalable dérivé dans un sens, dérive dans un sens opposé. Ainsi, l'implantation de deux circuits d'adressage associé à chaque émetteur contribue à compenser les variations de seuil de déclenchement des modulateurs d'un écran d'affichage. Dans les modes de réalisation qui viennent d'être décrits, c'est à chaque trame d'image qu'on inverse l'activation de l'un et de l'autre circuit d'adressage de l'écran selon l'invention ; on peut, sans se départir de l'invention, procéder à cette alternance non pas à chaque trame d'image, mais entre des séries de trames d'images. Dans les modes de réalisation décrits, les phases de polarisation et d'activation sont réalisées simultanément et ont des durées égales. En variante, les moyens de commandes sont également aptes à commander les modulateurs 14 et 34 pour que les phases de polarisation et d'activation des premier et second circuits, bien que réalisées simultanément, aient des durées différentes. Selon un mode de réalisation préférentiel, la tension de polarisation appliquée à l'un ou à l'autre des modulateurs d'un émetteur varie d'une trame d'image à l'autre, en fonction de la tension d'adressage appliquée à ce modulateur lors de la trame précédente ; de préférence, cette tension de polarisation est égale mais de signe opposé à ladite tension d'adressage de la trame précédente. 14, the control unit 46 transmits a bias voltage V p to the first electrode 48 and an addressing voltage V Db representative of an image datum at the second electrode 50. The switches 18 and 38 are simultaneously open by applying the selection voltage V s to the electrode 52. The bias voltage V p is transmitted to the gate of the modulator 14 and to the terminal of the capacitor 16. The capacitor 16 discharges and then charges negatively. As indicated by the solid line curve in FIG. 4E, the drain current l d1 is canceled out and remains zero during step J. During steps I and J, the bias voltage V p is applied to the gate of the modulator 14. Steps I and J therefore together form a phase of polarization of the first addressing circuit 6. Jointly, the addressing voltage V D is applied to the gate of the modulator 34 and to a terminal of the capacitor 36 This voltage, maintained at the gate of the modulator 34 by the capacitor 36, generates a drain current I d2 which supplies the transmitter 4 during step J and until the next step of programming new image data. During steps I and J, the transmitter 4 is supplied with current by the second addressing circuit 12; these steps therefore together form an activation phase of the second addressing circuit. Consequently, the control system 56 and the control units 46 and 54 control the addressing of the selection, addressing and bias voltages so that: - an addressing voltage of positive polarity is applied to the gate of the modulator 14 of the first addressing circuit 6 to supply the transmitter 4 and simultaneously, a bias voltage of negative polarity is applied to the gate of the modulator 34 of the second addressing circuit 12 to compensate for the drift of its threshold voltage trigger; - then inversely, an addressing voltage of positive polarity is applied to the gate of the modulator 34 of the second addressing circuit 12 to supply the transmitter 4 and simultaneously, a bias voltage of negative polarity is applied to the gate of the modulator 14 of the first addressing circuit 6 to compensate for the drift of its trigger threshold voltage. The transmitter 4 is thus supplied in turn by the modulated current, by the modulator 14, then by the modulator 34. The first 6 and second 12 addressing circuits are alternately activated to supply current to the transmitter 4. When the modulator 14 supplies the transmitter 4, the modulator 34 is biased by application to its grid of a bias voltage corresponding to a high negative voltage so that the trigger threshold voltage of the modulator 34 derived during the previous phase regains its initial value. Conversely, when the modulator 34 supplies the transmitter 4, the modulator 14 is biased by this same negative bias voltage so that its trigger threshold voltage having previously drifted in one direction, drift in an opposite direction. Thus, the establishment of two circuits address associated with each transmitter helps to compensate for variations in the trigger threshold of the modulators of a display screen. In the embodiments which have just been described, it is with each image frame that the activation of one and the other addressing circuit of the screen according to the invention is reversed; it is possible, without departing from the invention, to carry out this alternation not with each image frame, but between series of image frames. In the embodiments described, the polarization and activation phases are carried out simultaneously and have equal durations. As a variant, the control means are also able to control the modulators 14 and 34 so that the polarization and activation phases of the first and second circuits, although carried out simultaneously, have different durations. According to a preferred embodiment, the bias voltage applied to one or the other of the modulators of a transmitter varies from one image frame to another, depending on the addressing voltage applied to this modulator during the previous frame; preferably, this bias voltage is equal but of opposite sign to said addressing voltage of the previous frame.

Claims

REVENDICATIONS 1. Ecran d'affichage d'images comportant : - des émetteurs (4) de lumière répartis selon des lignes d'émetteurs et des colonnes d'émetteurs pour former un réseau d'émetteurs, - des moyens de commande (2, 6, 8, 10, 12 ; 40, 42, 44) de l'émission des émetteurs du réseau comprenant : a) un premier circuit d'adressage (6, 14, 16, 18) d'un émetteur (4), associé à chaque émetteur du réseau pour la commande du courant le traversant, ledit circuit (6) comportant : - un premier modulateur de courant (14) apte à alimenter ledit émetteur (4), ledit premier modulateur (14) comprenant une électrode de grille et deux électrodes de passage du courant, - une première capacité de stockage (16) apte à imposer un potentiel à l'électrode de grille du premier modulateur de courant (14), b) pour chaque émetteur (4), au moins un second circuit d'adressage (12, 34, 36, 38) d'un émetteur, ledit premier (6) et ledit second (12) circuits d'adressage étant associés en parallèle au même émetteur (4), ledit second circuit (12) comprenant : - un second modulateur de courant (34) dudit émetteur (4) comportant une électrode de grille et deux électrodes de passage du courant, - une seconde capacité de stockage (36) apte à stocker un potentiel à l'électrode de grille du second modulateur de courant (34); c) des moyens de commande d'adressage (8, 11 , 20, 22 ; 42, 46, 48, 50, 56) étant aptes à appliquer une tension d'adressage (VD ; DDι, VD2) à ladite première capacité de stockage (16), et à ladite seconde capacité de stockage (16), ladite tension d'adressage étant représentative d'une donnée d'image, et étant adaptés pour activer au choix le premier (6) ou le second (12) circuits d'adressage pour alimenter l'émetteur (4) en courant selon ladite donnée d'image, caractérisé en ce que les moyens de commande d'adressage (8, 11 ,CLAIMS 1. Image display screen comprising: - light emitters (4) distributed along lines of emitters and columns of emitters to form a network of emitters, - control means (2, 6 , 8, 10, 12; 40, 42, 44) of the transmission of the transmitters of the network comprising: a) a first addressing circuit (6, 14, 16, 18) of a transmitter (4), associated with each transmitter in the network for controlling the current flowing through it, said circuit (6) comprising: - a first current modulator (14) capable of supplying said transmitter (4), said first modulator (14) comprising a gate electrode and two current flow electrodes, - a first storage capacity (16) capable of imposing a potential on the gate electrode of the first current modulator (14), b) for each transmitter (4), at least a second circuit d addressing (12, 34, 36, 38) of a transmitter, said first (6) and said second (12) addressing circuits being associated in pa parallel to the same transmitter (4), said second circuit (12) comprising: - a second current modulator (34) of said transmitter (4) comprising a gate electrode and two electrodes for passing current, - a second storage capacity ( 36) able to store a potential at the gate electrode of the second current modulator (34); c) addressing control means (8, 11, 20, 22; 42, 46, 48, 50, 56) being able to apply an addressing voltage (V D ; D D ι, V D2 ) to said first storage capacity (16), and said second storage capacity (16), said addressing voltage being representative of image data, and being adapted to activate the first (6) or second ( 12) addressing circuits for supplying the transmitter (4) with current according to said image data, characterized in that the addressing control means (8, 11,
20, 22 ; 42, 46, 48, 50, 56) sont aptes à imposer une tension de polarisation (Vp) au choix audit premier modulateur de courant (14) ou audit second modulateur de courant (34), ladite tension de polarisation ayant une polarité inverse à la polarité de ladite tension d'adressage. 20, 22; 42, 46, 48, 50, 56) are capable of imposing a bias voltage (V p ) of choice on said first current modulator (14) or on said second current modulator (34), said bias voltage having a polarity opposite to the polarity of said addressing voltage.
2. Ecran d'affichage selon la revendication 1 , caractérisé en ce que les moyens de commande d'adressage (8, 11 , 20, 22 ; 42, 46, 48, 50, 56) sont propres à appliquer audit premier modulateur de courant (14) d'abord la tension d'adressage (VD ; DD-I, VD2) pour démarrer une phase (B, C, D ; G, H) d'activation du premier circuit d'adressage (6), puis la tension de polarisation (Vp) pour démarrer une phase (E, F ; I, J) de polarisation du premier circuit d'adressage (6). 2. Display screen according to claim 1, characterized in that the addressing control means (8, 11, 20, 22; 42, 46, 48, 50, 56) are suitable for applying to said first current modulator (14) first the addressing voltage (VD; DD-I, V D 2) to start a phase (B, C, D; G, H) of activation of the first addressing circuit (6), then the bias voltage (V p ) to start a phase (E, F; I, J) of bias of the first addressing circuit (6).
3. Ecran d'affichage selon la revendication 2, caractérisé en ce que les moyens de commande d'adressage (8, 11 , 20, 22 ; 42, 46, 48, 50, 56) sont propres à appliquer audit second modulateur de courant (34) d'abord la tension d'adressage (VD ; DDι, VD2) pour démarrer une phase (E, F ; I, J) d'activation du second circuit d'adressage (12), puis la tension de polarisation (Vp) pour démarrer une phase (B, C, D ; G, H) de polarisation du second circuit d'adressage (12) ; en ce que la phase d'activation du premier circuit d'adressage (6) est synchrone à la phase de polarisation du second circuit d'adressage (12) et en ce que la phase d'activation du second circuit d'adressage (12) est synchrone à la phase de polarisation du premier circuit d'adressage (6). 3. Display screen according to claim 2, characterized in that the addressing control means (8, 11, 20, 22; 42, 46, 48, 50, 56) are suitable for applying to said second current modulator (34) first the addressing voltage (V D ; D D ι, V D 2) to start a phase (E, F; I, J) of activation of the second addressing circuit (12), then the bias voltage (V p ) for starting a phase (B, C, D; G, H) of bias of the second addressing circuit (12); in that the activation phase of the first addressing circuit (6) is synchronous with the polarization phase of the second addressing circuit (12) and in that the activation phase of the second addressing circuit (12 ) is synchronous to the polarization phase of the first addressing circuit (6).
4. Ecran d'affichage selon l'une quelconque des revendications précédentes, caractérisé en ce que les moyens de commande comprennent des moyens de commande de sélection (10, 11 , 24, 26, 28; 44, 52, 54, 56) comportant : - pour chaque premier circuit d'adressage (6) d'un émetteur, un premier interrupteur de sélection (18) apte à piloter la transmission de ladite tension d'adressage (VD ; VD-I , VD2) OU de ladite tension de polarisation en fonction d'une tension de sélection (VS1, VS2 ; Vs) vers ladite première capacité de stockage (16) et ladite grille dudit premier modulateur de courant (14) pour sélectionner ledit émetteur (4) ; - pour chaque second circuit d'adressage (12) du même émetteur, un second interrupteur de sélection (38) apte à piloter la transmission de ladite tension d'adressage (VD ; VDι, VD2) ou de ladite tension de polarisation en fonction de ladite tension de sélection (Vsi, VS2 ; Vs) vers ladite seconde capacité de stockage (36) et ladite grille dudit second modulateur de courant (34) pour sélectionner ledit émetteur (4) ; et - des moyens de pilotage (11 , 24, 26, 28 ; 52, 54, 56) des premier (18) et second (38) interrupteurs de sélection. 4. Display screen according to any one of the preceding claims, characterized in that the control means comprise selection control means (10, 11, 24, 26, 28; 44, 52, 54, 56) comprising : - for each first addressing circuit (6) of a transmitter, a first selection switch (18) capable of controlling the transmission of said addressing voltage (VD; VD-I, V D 2) OR of said bias voltage as a function of a selection voltage (V S1 , V S2 ; V s ) to said first storage capacity (16) and said grid of said first current modulator (14) for selecting said transmitter (4); - for each second addressing circuit (12) of the same transmitter, a second selection switch (38) capable of controlling the transmission of said addressing voltage (VD; V D ι, V D2 ) or of said bias voltage in a function of said selection voltage (Vsi, V S2 ; V s ) to said second storage capacity (36) and said grid of said second current modulator (34) for selecting said transmitter (4); and - control means (11, 24, 26, 28; 52, 54, 56) of the first (18) and second (38) selection switches.
5. Ecran d'affichage selon la revendication 4, caractérisé en ce que les moyens de pilotage (11 , 24, 26, 28 ; 52, 54, 56) comportent en outre : - pour chaque ligne d'émetteurs, une première (24) et une seconde (26) électrodes de sélection raccordées au premier (18), respectivement au second (38) interrupteurs de sélection pour leur commande ; et - une unité de pilotage (28) de sélection apte à transmettre alternativement, d'abord ladite tension de sélection (Vsi) à ladite première électrode (24) de sélection, puis ladite tension de sélection (Vs2) à ladite seconde électrode (26) de sélection. 5. Display screen according to claim 4, characterized in that the control means (11, 24, 26, 28; 52, 54, 56) further comprise: - for each line of transmitters, a first (24 ) and a second (26) selection electrodes connected to the first (18), respectively to the second (38) selection switches for their control; and a selection piloting unit (28) capable of transmitting alternately, firstly said selection voltage (Vsi) to said first selection electrode (24), then said selection voltage (Vs 2 ) to said second electrode ( 26) selection.
6. Ecran d'affichage selon la revendication 5, caractérisé en ce que les moyens de commande d'adressage (8, 20, 22 ; 42, 46, 48, 50) comportent : - une électrode d'adressage (20) pour chaque colonne d'émetteurs, le premier (18) et le second (38) interrupteurs de sélection étant raccordés à ladite électrode d'adressage (20) ; et - une unité de pilotage (22) d'adressage apte à envoyer alternativement ladite tension d'adressage (VD) et ladite tension de polarisation (Vp) sur ladite électrode d'adressage (20). 6. Display screen according to claim 5, characterized in that the addressing control means (8, 20, 22; 42, 46, 48, 50) comprise: - an addressing electrode (20) for each column of transmitters, the first (18) and the second (38) selector switches being connected to said addressing electrode (20); and - an addressing control unit (22) capable of alternately sending said addressing voltage (VD) and said bias voltage (V p ) to said addressing electrode (20).
7. Ecran d'affichage selon la revendication 4, caractérisé en ce que les moyens de pilotage (11 , 24, 26, 28 ; 52, 54, 56) comportent en outre : - une électrode de sélection (52) pour chaque ligne d'émetteurs, les premier (18) et second (38) interrupteurs de sélection étant raccordés à ladite électrode de sélection (52) pour leur commande ; et - une unité de pilotage (54) de sélection apte à envoyer ladite tension de sélection (Vs) concomitamment aux premier (18) et second (38) interrupteurs de sélection. 7. Display screen according to claim 4, characterized in that the control means (11, 24, 26, 28; 52, 54, 56) further comprise: - a selection electrode (52) for each line d transmitters, the first (18) and second (38) selection switches being connected to said selection electrode (52) for their control; and - a selection control unit (54) able to send said selection voltage (V s ) concomitantly to the first (18) and second (38) selection switches.
8. Ecran d'affichage selon la revendication 7, caractérisé en ce que les moyens de commande d'adressage (8, 20, 22 ; 42, 46, 48, 50) comportent : - pour chaque colonne d'émetteurs, une première (48) et une seconde (50) électrodes d'adressage raccordées au premier (18), respectivement au second (38) interrupteurs de sélection ; et - une unité de pilotage (46) d'adressage apte à envoyer concomitamment sur la première électrode (48) d'adressage et sur la seconde électrode (50) d'adressage au choix, ladite tension d'adressage (VDI) OU ladite tension de polarisation (Vp). 8. Display screen according to claim 7, characterized in that the addressing control means (8, 20, 22; 42, 46, 48, 50) comprise: - for each column of transmitters, a first (48) and a second (50) addressing electrodes connected to the first (18), respectively to the second (38) selection switches; and - an addressing control unit (46) able to send simultaneously to the first addressing electrode (48) and to the second addressing electrode (50) as desired, said addressing voltage (VDI) OR said bias voltage (V p ).
9. Procédé d'adressage d'un écran d'affichage d'images comportant des émetteurs de lumière (4), un premier (6) et un second (12) circuits d'adressage, le premier circuit d'adressage (6) comprenant un premier (14) modulateur de courant connecté à un émetteur (4), une première (16) capacité de stockage apte à stocker un potentiel à la grille du premier (14) modulateur de courant, ledit second circuit d'adressage (12) comprenant un second (34) modulateur de courant connecté audit émetteur (4), une seconde (36) capacité de stockage apte à stocker un potentiel à la grille du second (14) modulateur de courant ; chaque modulateur (14, 34) comportant notamment une électrode de grille et une électrode de source ; chaque modulateur étant traversé par un courant quand une tension supérieure à une tension de seuil de déclenchement est appliquée entre son électrode de grille et son électrode de source, caractérisé en que le procédé comporte, pour le pilotage de chaque émetteur (4) : - une phase d'activation (B, C, D ; G, H) du premier circuit d'adressage (6) pour alimenter en courant l'émetteur (4) ; - une phase de polarisation (B, C, D ; G, H) du second circuit d'adressage (12) pour dériver la tension de seuil de déclenchement du second modulateur (34) ; - une phase d'activation (E, F ; I, J) du second circuit d'adressage (12) pour alimenter en courant l'émetteur (4) ; et - une phase de polarisation (E, F ; I, J) du premier circuit d'adressage9. Method for addressing an image display screen comprising light emitters (4), a first (6) and a second (12) addressing circuits, the first addressing circuit (6) comprising a first (14) current modulator connected to a transmitter (4), a first (16) storage capacity capable of storing a potential at the gate of the first (14) current modulator, said second addressing circuit (12 ) comprising a second (34) current modulator connected to said transmitter (4), a second (36) storage capacity capable of storing a potential at the gate of the second (14) current modulator; each modulator (14, 34) comprising in particular a gate electrode and a source electrode; each modulator being traversed by a current when a voltage greater than a triggering threshold voltage is applied between its gate electrode and its source electrode, characterized in that the method comprises, for controlling each emitter (4): - a activation phase (B, C, D; G, H) of the first addressing circuit (6) for supplying current to the transmitter (4); - a bias phase (B, C, D; G, H) of the second addressing circuit (12) to derive the trigger threshold voltage of the second modulator (34); - an activation phase (E, F; I, J) of the second addressing circuit (12) for supplying current to the transmitter (4); and - a bias phase (E, F; I, J) of the first addressing circuit
(6) pour dériver la tension de seuil de déclenchement du premier modulateur (34), et en ce que la phase d'activation du premier circuit d'adressage (6) est concomitante à la phase de polarisation du second circuit d'adressage (12) et la phase d'activation du second circuit d'adressage (12) est concomitante à la phase de polarisation premier circuit d'adressage (6). (6) to derive the trigger threshold voltage of the first modulator (34), and in that the activation phase of the first addressing circuit (6) is concomitant with the polarization phase of the second addressing circuit (12) and the activation phase of the second addressing circuit (12) is concomitant with the polarization phase first addressing circuit (6).
10. Procédé d'adressage selon la revendication 9, caractérisé en ce que une ou plusieurs phases d'activation du premier circuit d'adressage (6) sont suivies par au moins une phase de polarisation du premier circuit d'adressage (6) et une ou plusieurs phases d'activation du second circuit d'adressage (12) sont suivies par au moins une phase de polarisation du second circuit d'adressage (12). 10. Addressing method according to claim 9, characterized in that one or more phases of activation of the first addressing circuit (6) are followed by at least one phase of biasing of the first addressing circuit (6) and one or more activation phases of the second addressing circuit (12) are followed by at least one bias phase of the second addressing circuit (12).
11. Procédé d'adressage selon la revendication 9 ou 10, caractérisé en ce qu'il comporte : - une étape de programmation d'adressage (B ; G) de ladite première capacité de stockage par application à ladite capacité d'une tension d'adressage (VD ; VD-ι, VD2) représentative d'une donnée d'image ; - une étape de programmation de polarisation (D ; I) dudit premier modulateur (14) de courant par application audit modulateur d'une tension de polarisation (Vp), ladite tension de polarisation ayant une polarité inverse à la polarité du potentiel stocké par la première capacité de stockage (16) ; - une étape de programmation de polarisation (A ; G) dudit second modulateur (34) de courant par application audit modulateur de ladite tension de polarisation (Vp) ; et - une étape de programmation d'adressage (E ; I) de ladite seconde capacité de stockage (36) par application à ladite capacité de ladite tension d'adressage (VD ; VDι, VD2). 11. Addressing method according to claim 9 or 10, characterized in that it comprises: - an addressing programming step (B; G) of said first storage capacity by application to said capacity of a voltage d addressing (VD; V D -ι, V D 2) representative of image data; a polarization programming step (D; I) of said first current modulator (14) by applying to said modulator a polarization voltage (V p ), said polarization voltage having a polarity opposite to the polarity of the potential stored by the first storage capacity (16); - a polarization programming step (A; G) of said second current modulator (34) by applying said polarization voltage (V p ) to said modulator; and - an addressing programming step (E; I) of said second storage capacity (36) by applying to said capacity of said addressing voltage (V D ; V D ι, V D 2).
12. Procédé d'adressage selon la revendication 11 , caractérisé en ce que l'étape (D) de programmation de polarisation dudit premier modulateur (14) de courant est suivie par l'étape (E) de programmation d'adressage de la seconde capacité de stockage (36) et alternativement l'étape de programmation de polarisation (A) dudit second modulateur de courant (34) est suivie par l'étape de programmation d'adressage (B) de la première capacité de stockage (16). 12. Addressing method according to claim 11, characterized in that the step (D) of polarization programming of said first current modulator (14) is followed by the step (E) of programming of addressing of the second storage capacity (36) and alternatively the polarization programming step (A) of said second current modulator (34) is followed by the addressing programming step (B) of the first storage capacity (16).
13. Procédé d'adressage selon la revendication 11 , caractérisé en ce que ladite étape de programmation de polarisation (G) dudit second modulateur (34) de courant est concomitante à ladite étape de programmation d'adressage (G) de ladite première capacité de stockage (16) et ladite étape de programmation de polarisation (I) dudit premier modulateur (14) de courant est concomitante à ladite étape de programmation d'adressage (I) de ladite seconde capacité de stockage (36). 13. Addressing method according to claim 11, characterized in that said polarization programming step (G) of said second current modulator (34) is concomitant with said addressing programming step (G) of said first capacitance storage (16) and said bias programming step (I) of said first current modulator (14) is concomitant with said addressing programming step (I) of said second storage capacity (36).
PCT/FR2004/003104 2003-12-31 2004-12-02 Image display screen and method of addressing said screen WO2005073948A1 (en)

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