WO2005081748A3 - Semiconductor structure having strained semiconductor and method therefor - Google Patents

Semiconductor structure having strained semiconductor and method therefor Download PDF

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Publication number
WO2005081748A3
WO2005081748A3 PCT/US2005/001532 US2005001532W WO2005081748A3 WO 2005081748 A3 WO2005081748 A3 WO 2005081748A3 US 2005001532 W US2005001532 W US 2005001532W WO 2005081748 A3 WO2005081748 A3 WO 2005081748A3
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WO
WIPO (PCT)
Prior art keywords
layer
semiconductor structure
silicon
semiconductor
strained
Prior art date
Application number
PCT/US2005/001532
Other languages
French (fr)
Other versions
WO2005081748A2 (en
Inventor
Alexander L Barr
Dejan Jovanovic
Bich-Yen Nguyen
Mariam G Sadaka
Voon-Yew Thean
Ted R White
Original Assignee
Freescale Semiconductor Inc
Alexander L Barr
Dejan Jovanovic
Bich-Yen Nguyen
Mariam G Sadaka
Voon-Yew Thean
Ted R White
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Publication date
Application filed by Freescale Semiconductor Inc, Alexander L Barr, Dejan Jovanovic, Bich-Yen Nguyen, Mariam G Sadaka, Voon-Yew Thean, Ted R White filed Critical Freescale Semiconductor Inc
Publication of WO2005081748A2 publication Critical patent/WO2005081748A2/en
Publication of WO2005081748A3 publication Critical patent/WO2005081748A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body

Abstract

A first semiconductor structure (10) has a silicon substrate (12), a first silicon germanium layer (14) grown on the silicon, a second silicon germanium layer (16) on the first silicon germanium layer (14), and a strained silicon layer (18) on the second silicon germanium layer (16). A second semiconductor structure (22) has a silicon substrate (24) and an insulating top layer (26). The silicon layer (18) of the first semiconductor structure (10) is bonded to the insulator layer (26) to form a third semiconductor structure (30). The second silicon germanium layer (16) is cut to separate most of the first semiconductor structure (10) from the third semiconductor structure (30). The silicon germanium layer (16) is removed to expose the strained silicon layer (18) where transistors (32 & 34) are subsequently formed, which is then the only layer remaining from the first semiconductor structure (10). The transistors (32 & 34) are oriented along the <100> direction and at a 45 degree angle to the <100> direction of the base silicon layer (24) of the second semiconductor structure.
PCT/US2005/001532 2004-02-17 2005-01-12 Semiconductor structure having strained semiconductor and method therefor WO2005081748A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/780,143 2004-02-17
US10/780,143 US7205210B2 (en) 2004-02-17 2004-02-17 Semiconductor structure having strained semiconductor and method therefor

Publications (2)

Publication Number Publication Date
WO2005081748A2 WO2005081748A2 (en) 2005-09-09
WO2005081748A3 true WO2005081748A3 (en) 2006-06-08

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PCT/US2005/001532 WO2005081748A2 (en) 2004-02-17 2005-01-12 Semiconductor structure having strained semiconductor and method therefor

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US (1) US7205210B2 (en)
WO (1) WO2005081748A2 (en)

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US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
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US20070054467A1 (en) * 2005-09-07 2007-03-08 Amberwave Systems Corporation Methods for integrating lattice-mismatched semiconductor structure on insulators
US7986029B2 (en) * 2005-11-08 2011-07-26 Taiwan Semiconductor Manufacturing Company, Ltd. Dual SOI structure
US7777250B2 (en) 2006-03-24 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures and related methods for device fabrication
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US20080187018A1 (en) 2006-10-19 2008-08-07 Amberwave Systems Corporation Distributed feedback lasers formed via aspect ratio trapping
US7482209B2 (en) * 2006-11-13 2009-01-27 International Business Machines Corporation Hybrid orientation substrate and method for fabrication of thereof
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US7205210B2 (en) 2007-04-17
US20050181549A1 (en) 2005-08-18
WO2005081748A2 (en) 2005-09-09

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