WO2005088716A3 - Treatment method and device of the working layer of a multilayer structure - Google Patents

Treatment method and device of the working layer of a multilayer structure Download PDF

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Publication number
WO2005088716A3
WO2005088716A3 PCT/IB2005/000832 IB2005000832W WO2005088716A3 WO 2005088716 A3 WO2005088716 A3 WO 2005088716A3 IB 2005000832 W IB2005000832 W IB 2005000832W WO 2005088716 A3 WO2005088716 A3 WO 2005088716A3
Authority
WO
WIPO (PCT)
Prior art keywords
working layer
layer
multilayer structure
working
constitute
Prior art date
Application number
PCT/IB2005/000832
Other languages
French (fr)
Other versions
WO2005088716A2 (en
Inventor
Frederic Allibert
Francois Brunier
Original Assignee
Soitec Silicon On Insulator
Frederic Allibert
Francois Brunier
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator, Frederic Allibert, Francois Brunier filed Critical Soitec Silicon On Insulator
Priority to JP2007502438A priority Critical patent/JP4510876B2/en
Priority to CN200580012304.9A priority patent/CN1947248B/en
Priority to EP05708800A priority patent/EP1723671A2/en
Publication of WO2005088716A2 publication Critical patent/WO2005088716A2/en
Priority to US11/433,713 priority patent/US7790048B2/en
Publication of WO2005088716A3 publication Critical patent/WO2005088716A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604—Chemical etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

According to a first embodiment, the invention relates to a method for treating an electrically conductive working layer of a multilayer structure made from semiconductor materials, the structure including under said working layer an electrically insulating layer, said treatment being destined to constitute in said working layer at least one island surrounded by material of the electrically insulating layer, method including a wet chemical etching step of the working layer, method characterised in that prior to the wet etching step selective masking is realised on several regions of said working layer in order to constitute in this working layer several islands, each region masked from the layer corresponding to a respective island. The invention also proposes the application of such a method to the characterisation of the electrical properties of a structure, and an associated device.
PCT/IB2005/000832 2004-03-10 2005-03-10 Treatment method and device of the working layer of a multilayer structure WO2005088716A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2007502438A JP4510876B2 (en) 2004-03-10 2005-03-10 Processing method and processing device for working layer of multilayer structure
CN200580012304.9A CN1947248B (en) 2004-03-10 2005-03-10 Treatment of service layer of a multi-layer structure and its device
EP05708800A EP1723671A2 (en) 2004-03-10 2005-03-10 Treatment method and device of the working layer of a multilayer structure
US11/433,713 US7790048B2 (en) 2004-03-10 2006-05-12 Treatment of the working layer of a multilayer structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0402473A FR2867606B1 (en) 2004-03-10 2004-03-10 METHOD AND DEVICE FOR PROCESSING THE USEFUL LAYER OF A MULTILAYER STRUCTURE
FR0402473 2004-03-10

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11/433,713 Continuation US7790048B2 (en) 2004-03-10 2006-05-12 Treatment of the working layer of a multilayer structure

Publications (2)

Publication Number Publication Date
WO2005088716A2 WO2005088716A2 (en) 2005-09-22
WO2005088716A3 true WO2005088716A3 (en) 2006-09-21

Family

ID=34896418

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2005/000832 WO2005088716A2 (en) 2004-03-10 2005-03-10 Treatment method and device of the working layer of a multilayer structure

Country Status (7)

Country Link
US (1) US7790048B2 (en)
EP (1) EP1723671A2 (en)
JP (1) JP4510876B2 (en)
KR (1) KR100828113B1 (en)
CN (1) CN1947248B (en)
FR (1) FR2867606B1 (en)
WO (1) WO2005088716A2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2867606B1 (en) 2004-03-10 2006-06-02 Soitec Silicon On Insulator METHOD AND DEVICE FOR PROCESSING THE USEFUL LAYER OF A MULTILAYER STRUCTURE
EP1770788A3 (en) 2005-09-29 2011-09-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having oxide semiconductor layer and manufacturing method thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5519336A (en) * 1992-03-03 1996-05-21 Honeywell Inc. Method for electrically characterizing the insulator in SOI devices
US5786231A (en) * 1995-12-05 1998-07-28 Sandia Corporation Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer
US6159829A (en) * 1996-09-16 2000-12-12 Warren; William L. Memory device using movement of protons

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE550885A (en) * 1955-09-09
JPS56123376A (en) 1980-02-28 1981-09-28 Fujitsu Ltd Etching method
JPS5948945A (en) 1982-09-14 1984-03-21 Hitachi Cable Ltd Manufacture of lead frame for semiconductor
US4668083A (en) * 1985-11-18 1987-05-26 The Perkin-Elmer Corporation Contact lithographic fabrication of patterns on large optics
US5433821A (en) * 1994-02-25 1995-07-18 International Business Machines Corporation Direct patternization device and method
US5489792A (en) * 1994-04-07 1996-02-06 Regents Of The University Of California Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility
KR100333155B1 (en) * 1994-09-16 2002-11-21 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Thin film semiconductor device and manufacturing method
US6191007B1 (en) * 1997-04-28 2001-02-20 Denso Corporation Method for manufacturing a semiconductor substrate
DE19828969A1 (en) * 1998-06-29 1999-12-30 Siemens Ag Manufacturing integrated semiconductor components
AT408158B (en) 1998-12-28 2001-09-25 Kroener Friedrich Dr Mask for the patterned, electrochemical processing of a silicon chip for solar cell production
JP2003173951A (en) * 2001-12-04 2003-06-20 Tokyo Electron Ltd Method for manufacturing electron beam lithography mask and mask blanks for electron beam lithography
FR2867606B1 (en) 2004-03-10 2006-06-02 Soitec Silicon On Insulator METHOD AND DEVICE FOR PROCESSING THE USEFUL LAYER OF A MULTILAYER STRUCTURE

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5519336A (en) * 1992-03-03 1996-05-21 Honeywell Inc. Method for electrically characterizing the insulator in SOI devices
US5786231A (en) * 1995-12-05 1998-07-28 Sandia Corporation Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer
US6159829A (en) * 1996-09-16 2000-12-12 Warren; William L. Memory device using movement of protons

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
CRISTOLOVEANU S ET AL: "A REVIEW OF THE PSEUDO-MOS TRANSISTOR IN SOI WAFERS: OPERATION, PARAMETERS EXTRACTION, AND APPLICATIONS", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE INC. NEW YORK, US, vol. 47, no. 5, May 2000 (2000-05-01), pages 1018 - 1027, XP000928623, ISSN: 0018-9383 *
SORIN CRISTOLOVEANU ET AL: "POINT-CONTACT PSEUDO-MOSFET FOR IN-SITU CHARACTERIZATION OF AS-GROWN SILICON-ON-INSULATOR WAFERS", IEEE ELECTRON DEVICE LETTERS, IEEE INC. NEW YORK, US, vol. 13, no. 2, 1 February 1992 (1992-02-01), pages 102 - 104, XP000246200, ISSN: 0741-3106 *

Also Published As

Publication number Publication date
US7790048B2 (en) 2010-09-07
WO2005088716A2 (en) 2005-09-22
JP4510876B2 (en) 2010-07-28
EP1723671A2 (en) 2006-11-22
CN1947248A (en) 2007-04-11
FR2867606A1 (en) 2005-09-16
KR20060118604A (en) 2006-11-23
CN1947248B (en) 2010-07-21
FR2867606B1 (en) 2006-06-02
KR100828113B1 (en) 2008-05-08
JP2007528597A (en) 2007-10-11
US20060201907A1 (en) 2006-09-14

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