WO2005092070A2 - Vertically stacked semiconductor device - Google Patents
Vertically stacked semiconductor device Download PDFInfo
- Publication number
- WO2005092070A2 WO2005092070A2 PCT/US2005/009809 US2005009809W WO2005092070A2 WO 2005092070 A2 WO2005092070 A2 WO 2005092070A2 US 2005009809 W US2005009809 W US 2005009809W WO 2005092070 A2 WO2005092070 A2 WO 2005092070A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- chip
- chips
- metal
- standoffs
- substrate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 50
- 239000002184 metal Substances 0.000 claims abstract description 50
- 238000000034 method Methods 0.000 claims abstract description 30
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 27
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 25
- 230000008569 process Effects 0.000 claims abstract description 17
- 238000002161 passivation Methods 0.000 claims abstract description 15
- 239000000853 adhesive Substances 0.000 claims description 20
- 230000001070 adhesive effect Effects 0.000 claims description 20
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 4
- 238000012545 processing Methods 0.000 abstract description 16
- 238000004519 manufacturing process Methods 0.000 abstract description 13
- 230000008901 benefit Effects 0.000 abstract description 7
- 238000000059 patterning Methods 0.000 abstract description 3
- 235000012431 wafers Nutrition 0.000 description 16
- 239000000463 material Substances 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 230000008021 deposition Effects 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000010354 integration Effects 0.000 description 4
- 230000002452 interceptive effect Effects 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000000712 assembly Effects 0.000 description 2
- 238000000429 assembly Methods 0.000 description 2
- 239000011231 conductive filler Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000003993 interaction Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000004634 thermosetting polymer Substances 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000002648 laminated material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000011165 process development Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
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Definitions
- VERTICALLY STACKED SEMICONDUCTOR DEVICE Field Of The Invention This invention relates to a semiconductor circuit device; and more particularly to a vertically stacked semiconductor chip device and a method of fabrication.
- Background Of The Invention In the ongoing search for higher levels of circuit integration to support system level requirements, many avenues have been explored. In particular, chip feature sizes have been substantially reduced; wafer processing technologies have been altered to allow different types of circuits on the same chip; and package sizes and foot prints have been minimized. Each approach is limited by state-of- the-art technology and cost constraints, both from the device manufacturer and the end user. An approach for integration of functions and reduction of device size which facilitates more compact, higher performance systems is the assembly of multiple chips in a single package.
- multiple chips of the same or of different device technologies are included on an interconnecting substrate and/or in a single package which provides contacts to the next level of interconnection . Integration of multiple chips in the same package has been developed both in the horizontal and vertical planes. Historically, the vertical integration of memory circuits has provided a stacked device 10 having an increased memory capacity within the same footprint as a single device, as shown in FIG. 1. A number of similar chips 11 of relatively low pin count are connected to individual interposers 13. The assemblies are stacked atop each other, and interconnected to each other, and to external contacts 12. More recently, as shown in FIG. 2, multiple silicon chips 21 of different types have been assembled in a vertical stack with standoffs 24 between each of the active devices 21 to separate and allow interconnections to be made to substrate 23.
- Chips 21 are interconnected by conductive traces on substrate 23. Typically each chip 21 is separated from the vertically successive chip by an insulating material 24.
- a stacked chip assembly is of particular importance for coupling an integrated circuit to a memory device, such as a random access memory, E2prom, flash memory or buffer storage, where rapid interaction between chips is crucial. Wafer fabrication of memory circuits is not readily compatible with other IC wafer fabrication technologies, and is difficult and costly to integrate. Therefore, the assembly of stacked chips for providing a rapid interaction with functional chips is cost effective. Materials which have been used as stand-offs to separate the vertically stacked chips include polymeric films, laminate materials, adhesives, bare silicon chips, and/or a combination of such materials.
- Polymeric films may be applied to the wafer and photo patterned to expose the bonding pads, thereby offering the advantage of processing as wafers with multiple chips, rather than as individual chips during final assembly of the devices.
- each additional processing step adds significantly to the wafer cost and increases the probability of introducing defects which contribute to costly yield losses.
- Other types of materials used as standoffs most frequently require insertion into individual packages during assembly.
- Wire bonding is a widely used method to connect each semiconductor chip to the substrate or package.
- the bond pad is an electrically conductive metal area on the surface of the IC where bonding wires, typically of gold are connected. Copper has become commonly used for some interconnects 311 in integrated circuits, replacing aluminum.
- bond pads 31 for chips with copper interconnection technology often utilize an aluminum layer 33 to cap the exposed copper bond pads 31 as illustrated in a cross- sectional view of a portion of a chip 30 in FIG. 3.
- the aluminum cap 33 covers the copper pad 31 and overlaps onto the passivation layer 32, thereby allowing use of the same wire bonding tools and processes as those used for chips having aluminum interconnect technologies. It is well known that as the size of brittle silicon chips has increased, and the chips are adhered to substrates of different materials, thermal and mechanical stresses develop which can result in yield and reliability failures .
- a semiconductor device including a vertical assembly of semiconductor chips interconnected on a substrate.
- Metal standoffs patterned on the supporting chips provide a fixed space between the supporting chip and a successive vertically stacked chip. Wire bonds connect each chip to the substrate, and a polymeric adhesive secures the first chip to the substrate, and successive chips to their respective supporting chip.
- a supporting chip is any chip having another chip disposed atop it in a vertical device assembly. There may be more than one supporting chip and more than one second or stacked chip in a given device. Preferably, the device is within the footprint of a single semiconductor package.
- the standoffs are patterned islands comprising aluminum which has been deposited and patterned atop the passivation layer on the active surface of each supporting chip, simultaneously with processing steps used to form bond pad caps.
- the fabrication process adds no additional cost, and has the advantage of providing standoffs for a plurality of chips by processing in wafer form, thereby avoiding additional cost.
- a device with vertically stacked chips offers advantages both in device density, thereby minimizing circuit board space, and in increased operating speed for closely spaced interactive chips.
- the use of patterned aluminum islands as spacers between stacked chips offers additional advantages in providing good thermal conductivity to dissipate and spread heat through the chip stack and in avoiding additional processing steps.
- a method for fabrication of metal islands atop the passivation layer of semiconductor chips in wafer form preferably includes deposition of a metal comprising aluminum simultaneously with processing to form bond pad caps.
- a photoresist is applied, a photo mask which includes patterns for both the bond pad caps and the standoff islands is aligned, and the resist is exposed and developed. As in the existing cap process, the unwanted metal is removed by etching.
- a wafer having a plurality of chips with patterned metal islands atop the passivation is separated into individual chips for assembly into a packaged device. The preferred method incurs no additional cost or yield loss to wafer fabrication .
- chips having aluminum interconnection metallization and/or bond pads which do not require cap metal, stand-off islands are processed either by deposition of metal, patterning, and etching, by deposition of metal through a mask with openings for the islands, or by plating.
- a preferred method for assembly of a stacked chip device having patterned metal standoffs includes adhering a supporting chip with metal standoffs to an interconnecting substrate, applying a polymeric adhesive material to the top surface of the standoffs and area between standoffs, aligning, and placing a second chip atop the standoffs. If more than two chips are included in the stack, the process is repeated.
- the adhesive preferably a thermosetting polymer such as an epoxy filled with thermally conductive filler, is cured and each of the chips is wire bonded to the substrate.
- the adhesive forms a very thin layer on top of the standoffs, thereby allowing good thermal conductivity and stability to the assembly.
- FIG. 1 is a known device including vertically stacked chips connected to individual interposers.
- FIG. 2 is a known device having vertically stacked chips separated by an insulating layer.
- FIG. 3 is a cross sectional view of a portion of a known chip having a metal cap atop the bond pad.
- FIG. 4 is a cross section of a stacked chip device having aluminum island separators on a substrate, in accordance with the invention .
- FIG. 5a is a cross sectional view of one embodiment of the invention, including a pair of stacked chips having aluminum islands as separators.
- FIG. 1 is a known device including vertically stacked chips connected to individual interposers.
- FIG. 2 is a known device having vertically stacked chips separated by an insulating layer.
- FIG. 3 is a cross sectional view of a portion of a known chip having a metal cap atop the bond pad.
- FIG. 4 is a cross section of a stacked chip device having aluminum island separators on
- FIG. 5b illustrates three vertically stacked chips with metal island stand-offs between each successive chip.
- FIG. 5c is a cross section of a stacked chip device having aluminum island stand-offs and side by side stacked chips.
- FIG. ⁇ a is a top view of a chip having patterned bond pad caps and islands.
- FIG. 6b is a cross section of a chip having patterned bond pad caps and islands.
- FIG. 7 is a process flow diagram for the fabrication of circuit chips having island stand-offs according to the invention .
- FIG. 8 is a process flow diagram for the fabrication of stacked assemblies in accordance with the invention. Detailed Description In FIG.
- semiconductor device 40 includes a substrate 44 and vertically stacked chips 401 and 402, wherein a plurality of metal island standoffs 41 provide uniform separation space between the active front side of the supporting chip 401 and the inactive backside of successive chips 402.
- a polymeric material 45 adheres the supporting chip 401 to substrate 44 and the second chip 402 to the top surface of supporting chip 401.
- the polymeric adhesive 45 is preferably a thermosetting polymer such as an epoxy filled with a thermally conductive material.
- Adhesive 45 forms a thin bond line atop and between the metal islands and the second chip 402, thereby allowing good thermal conductivity and a stable assembly for wire bonding.
- Wire bonds 42 and 43 connect chips 401 and 402 to bonding lands on substrate 44.
- Conductive interconnections (not shown) on substrate 44, such as the base of a BGA (ball grid array) package, provide connections between the chips.
- a device having vertically stacked chips offers advantages both in reduced device density to minimize circuit board space needs, and increased operating speed between closely spaced interactive chips.
- the use of aluminum or other metal islands as spacers offers additional advantages in providing increased thermal conductivity to dissipate and spread heat through the chip stack.
- Aluminum islands avoid additional processing steps for devices having copper interconnections and bond pads with aluminum bond pad caps.
- Aluminum caps facilitate wire bonding with gold wire bonds using existing techniques and equipment. Further, because the island spacers preferably are discontinuous on large chips, stresses arising from dissimilar coefficients of thermal expansion of the active semiconductor components and the metal islands can be relieved and mitigated.
- FIG. 5 is a more detailed cross sectional view of a pair of vertically stacked chips 501 and 502 having patterned metal island standoffs 51 between the chips. Caps 52 cover bond pads 53 and overlap onto the passivation layer 511. Metal islands 51 on supporting chip 501 preferably are deposited and patterned simultaneously, thereby requiring no additional processing steps or complexity to existing wafer fabrication. In the preferred embodiment, supporting chip 501 with metal islands 51 has bond pads 53 comprising copper with caps 52 comprising aluminum.
- Passivation layer 511 atop the chip is typically a silicon nitride, silicon oxynitride, or a polymeric film such as one of the polyimide family.
- FIG. 5a provides an example of a vertically stacked chip pair, but the invention is not limited to a two chip stack and may include three or more chips, as illustrated in FIGS. 5b and 5c.
- Each supporting chip 503, 504 and 506 includes metal standoffs 51, 510 and 516, respectively. It can be seen that the largest and first supporting chip 503 has multiple island standoffs 51, whereas the smaller supporting chip 504 has a single standoff 510. In FIG.
- two chips 507 stacked horizontally atop a supporting chip 506 preferably are supported on separate standoffs 516. Discontinuity between the islands 51 on the large chip 503 allows thermally induced stresses to be relieved, whereas smaller chips 505 and 507 may not require a stress relief mechanism. Uppermost chips 505 and 507 in a stack require no metal islands. However, metal islands may be added for process simplification, for heat spreading, and/or if the chip potentially is used in an application requiring standoffs. In another embodiment, a semiconductor chip having metal islands on the first surface is provided. FIGS.
- FIGS. 6a and 6b are cross sectional views of a chip 601 having a plurality of bond pads 63, each of which is covered by a cap 62 of aluminum which extends onto the passivation layer 611 on the first surface of chip 601.
- One or more islands 61 of aluminum are defined inside the area bounded by bond pads. Islands are defined inside the bond pad area in order to avoid interference with the wire bonding process on a supporting chip in a vertical stack, and because the heat generated by the circuit typically is centrally located.
- the area of the islands is a function of the size of both the supporting and stacked second chips. Multiple islands having space between them are preferable for large chips wherein thermal expansion mismatches may need relief. However, for small chips, a single island is acceptable.
- the metal standoff is large enough to provide a balanced support for the second chip.
- the preferred process for fabrication of metal islands to provide separation between stacked chips and/or to increase thermal conductivity of a semiconductor device is in wafer form using existing metal deposition, photo processing and etching techniques.
- a wafer having bond pads comprising copper and having a passivation layer with openings for wire bonding is provided.
- the process steps outlined in FIG. 7 include deposition of a layer of metal, preferably aluminum having a thickness of 5 to 20kA, over the passivated first surface of the wafer; applying a layer of photoresist and exposing it through a photo mask which defines a cap atop each bond pad and overlaps onto the passivation.
- the mask further defines one or more islands inside the area of bond pads.
- the excess metal is removed by etching to leave islands elevated in the range of 5 to 20 kA above the passivation surface.
- the deposited metal may be aluminum or an alternate low cost, readily deposited metal having good thermal conductivity and stability.
- Assembly of the stacked chip device includes providing integrated circuit chips having metal islands standoffs atop the supporting chips, aligning and placing a supporting chip to a substrate by a die attach adhesive, applying a polymeric material, preferably a thermosetting adhesive filled with a thermally conductive filler such as alumina, to the prescribed area atop the standoffs on the supporting chip, aligning and placing the back of a second chip on the adhesive, and cross linking all chip attach adhesives.
- each chip is wire bonded to the substrate.
- mechanical protection is provided for the assembly by known packaging methods.
- each chip is wire bonded to the substrate prior to stacking the second chip and bonding. If more than two vertically stacked chips are included in the device, the first and second chips are assembled as described above, an adhesive is applied to standoffs and the top of the second chip, the adhesive is cured and the wire bonds attached. In those devices having more than one chip placed side by side on a supporting chip, the assembly is as described for a two chip stack; i.e., a single cure and wire bond process .
- Each of the process steps for assembly of the vertically stacked chip device having metal standoffs on the supporting chips are known in the industry and require no additional equipment or process development.
Abstract
Description
Claims
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US6642136B1 (en) | 2001-09-17 | 2003-11-04 | Megic Corporation | Method of making a low fabrication cost, high performance, high reliability chip scale package |
US7099293B2 (en) * | 2002-05-01 | 2006-08-29 | Stmicroelectronics, Inc. | Buffer-less de-skewing for symbol combination in a CDMA demodulator |
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US7245003B2 (en) * | 2004-06-30 | 2007-07-17 | Intel Corporation | Stacked package electronic device |
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US7279363B2 (en) | 2007-10-09 |
WO2005092070A3 (en) | 2006-05-04 |
CN1957462A (en) | 2007-05-02 |
US20060216858A1 (en) | 2006-09-28 |
US20050212109A1 (en) | 2005-09-29 |
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