WO2005098629A3 - Memory hub and method for providing memory sequencing hints - Google Patents

Memory hub and method for providing memory sequencing hints Download PDF

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Publication number
WO2005098629A3
WO2005098629A3 PCT/US2005/009524 US2005009524W WO2005098629A3 WO 2005098629 A3 WO2005098629 A3 WO 2005098629A3 US 2005009524 W US2005009524 W US 2005009524W WO 2005098629 A3 WO2005098629 A3 WO 2005098629A3
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WO
WIPO (PCT)
Prior art keywords
memory
hub
hints
sequencing
providing
Prior art date
Application number
PCT/US2005/009524
Other languages
French (fr)
Other versions
WO2005098629A2 (en
Inventor
Joseph M Jeddeloh
Original Assignee
Micron Technology Inc
Joseph M Jeddeloh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc, Joseph M Jeddeloh filed Critical Micron Technology Inc
Priority to JP2007506239A priority Critical patent/JP2007535737A/en
Priority to EP05730210A priority patent/EP1738265A4/en
Publication of WO2005098629A2 publication Critical patent/WO2005098629A2/en
Publication of WO2005098629A3 publication Critical patent/WO2005098629A3/en

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1684Details of memory controller using multiple buses
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0215Addressing or allocation; Relocation with look ahead addressing means
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1694Configuration of memory controller to different memory types

Abstract

A memory module (130a-30n) includes a memory hub (140) coupled to several memory devies (130). The memory hub is also couple to receive a memory packe from a system controller containing memory hint (301) of the subsequent operation of the memory devices. The meory module uses the hint to adjust the operation of the memory module, such as the number of pates to remain open or cache lines to befetched.
PCT/US2005/009524 2004-03-29 2005-03-23 Memory hub and method for providing memory sequencing hints WO2005098629A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007506239A JP2007535737A (en) 2004-03-29 2005-03-23 Memory hub and method providing memory ordering hints
EP05730210A EP1738265A4 (en) 2004-03-29 2005-03-23 Memory hub and method for providing memory sequencing hints

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/812,950 US7213082B2 (en) 2004-03-29 2004-03-29 Memory hub and method for providing memory sequencing hints
US10/812,950 2004-03-29

Publications (2)

Publication Number Publication Date
WO2005098629A2 WO2005098629A2 (en) 2005-10-20
WO2005098629A3 true WO2005098629A3 (en) 2009-05-28

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/009524 WO2005098629A2 (en) 2004-03-29 2005-03-23 Memory hub and method for providing memory sequencing hints

Country Status (6)

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US (2) US7213082B2 (en)
EP (1) EP1738265A4 (en)
JP (1) JP2007535737A (en)
KR (1) KR100860956B1 (en)
CN (1) CN101427224A (en)
WO (1) WO2005098629A2 (en)

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EP1738265A4 (en) 2010-05-26
KR100860956B1 (en) 2008-09-30
US20060212666A1 (en) 2006-09-21
EP1738265A2 (en) 2007-01-03
WO2005098629A2 (en) 2005-10-20
US7418526B2 (en) 2008-08-26
JP2007535737A (en) 2007-12-06
KR20060133071A (en) 2006-12-22
US7213082B2 (en) 2007-05-01
CN101427224A (en) 2009-05-06
US20050216678A1 (en) 2005-09-29

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