WO2005116815A1

WO2005116815A1 - Method and apparatus for passing messages and data between subsystems in a system-on-a-chip

Info

Publication number: WO2005116815A1
Application number: PCT/IB2005/051696
Authority: WO
Inventors: Scott Guo (Shaori); Thomas Bodmer
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 2004-05-25
Filing date: 2005-05-25
Publication date: 2005-12-08

Abstract

Methods and apparatus provide for efficient message passing communication between subsystems. In one aspect of the present invention FIFOs (202, 203, 204, 212, 216) are disposed between the subsystems (102, 104, 110) to buffer the messages passed therebetween. When such a FIFO (202, 203, 204, 212, 216) is filled to a predetermined level, additional incoming messages are transferred (410) to an associated external memory buffer, rather than to the FIFO. When the FIFO (202, 203, 204, 212, 216) has a predetermined amount of space available, the message that was transferred to the external memory buffer is retrieved and placed in the FIFO. The threshold for the internal FIFOs can be individually programmed. A status indicator is made available which indicates that a FIFO (202, 203, 204, 212, 216) is available to receive data as long as that FIFO (202, 203, 204, 212, 216) and its associated external memory buffer, taken together, have sufficient capacity to receive a message.

Description

METHOD AND APPARATUS FOR PASSING MESSAGES AND DATA BETWEEN SUBSYSTEMS IN A SYSTEM-ON-A-CHIP The present invention relates generally to methods and apparatus for improving communication between subsystems in a system on a chip, and more particularly relates to the use of both on-chip and off-chip memory in buffering messages passed between subsystems. Advances in semiconductor manufacturing technologies have resulted in the ability to include millions of circuit elements, such as transistors, onto a single integrated circuit. In turn, this high-level of integration has resulted in changes in architectural approach to designing integrated circuits. One such architectural change can be seen in the development of a class of integrated circuit that is referred to as a System-On-A-Chip. In such an integrated circuit, various blocks, which in complexity are equivalent to subsystems, are interfaced with each other in an architectural manner similar to that used previously to interface separately packaged integrated circuits. More particularly, these subsystem blocks are often interfaced by means of various busses, and must communicate with each other during the course of their operation. In a system-on-a-chip (SOC), one common way of exchanging information between subsystems is through pre-defined messages. These message exchanges require a flexible technique that is economical and efficient in terms of memory requirements and information exchange time. Any inefficiency due to message passing directly results in larger memory use and longer system latency, leading to higher cost and lower system performance. When the amount of data and messages is large, memory access becomes a bottleneck. The use of high-speed static random access memories for storing entire messages is often prohibitively expensive. What is needed are methods and apparatus for providing an efficient and versatile technique for performing information exchanges between subsystems, particularly in an SOC. Briefly, methods and apparatus provide for efficient message passing communication between subsystems. In one aspect of the present invention FIFOs are disposed between the subsystems to buffer the messages passed therebetween. When such a FIFO is filled to a predetermined level, that is, reaches a predetermined threshold of usage, additional incoming messages are transferred to an associated external memory buffer, rather than to the FIFO. When the FIFO has a predetermined amount of space available, the message that was transferred to the external memory buffer is retrieved and placed in the FIFO. In a further aspect of the present invention, the threshold for the internal FIFOs can be individually programmed. In a still further aspect of the present invention, a status indicator is made available which indicates that a FIFO is available to receive data as long as that FIFO and its associated external memory buffer, taken together, have sufficient capacity to receive a message. In a still further aspect of the present invention, the size of the associated external memory buffer is programmable. Fig. 1 is a block diagram of a wired and wireless broadband access gateway System On A Chip. Fig. 2 is a block diagram of a Memory Intelligent Module in accordance with the present invention. Fig. 3 is a block diagram illustrating the format of a RX data message. Fig. 4 is a flow diagram illustrating a method of communicating in accordance with the present invention. Fig. 5 is a flow diagram illustrating passing messages between subsystems in accordance with the present invention. Generally, the present invention relates to methods and apparatus for implementing an architecture for passing messages between subsystems of a system-on-a-chip; a process of allocating memory for data storage among the subsystems; and an interrupt mechanism. Other aspects of the present invention include offloading the internal memory to external memory; a system independent interface for system connection; and multiple transmit queues for quality of service (QoS) support. It is an object of the present invention to provide a significantly improved way of passing the messages between subsystems of an SOC, whereby the efficiency of memory access can be improved. To this end, the present invention provides methods and apparatus for communication between subsystems of an SOC. Reference herein to "one embodiment", "an embodiment", or similar formulations, means that a particular feature, structure, operation, or characteristic described in connection with the embodiment, is included in at least one embodiment of the present invention. Thus, the appearances of such phrases or formulations herein are not necessarily all referring to the same embodiment. Furthermore, various particular features, structures, operations, or characteristics may be combined in any suitable manner in one or more embodiments. The present invention applies to integrated circuits, which are also commonly referred to in this field as chips, microelectronic devices, and similarly well-known terms. As shown in Fig. 1 , an illustrative SOC 100 in accordance with the present invention includes the following major modules, or subsystems: a system processor 102 that executes a real-time operating system, system bus management software, wireless LAN MAC protocol and driver software, and application software; a packet processor 104 that executes per-packet processing software and an application for security; an IPsec engine 106 for implementing various security algorithms including 3DES and AES; six Ethernet Media Access Controllers (MAC) 109 that support six 10/100 Mil interfaces; a Wireless LAN (WLAN) baseband module 110 that implements standards of HiperLAN/2 and IEEE 802.1 la/b/g; an SDRAM interface with direct memory access (DMA) controllers 112 of up to 32 channels; various system interfaces including PCI 120 and USB 122 interfaces. As noted, SOC 100 of Fig. 1 is used to provide context for a description of an embodiment of the present invention. More particularly, descriptions of communication between WLAN baseband 110, system processor 102, and packet processor 104 are provided for an understanding of the present invention. The present invention is not limited to the particular example of the SOC of Fig.1, nor is the present invention limited to the functional specifics of this example. As used herein, the terms "packet processor" and "system processor" are both also referred to more generically as "host processors". As far as the wireless LAN functionality is concerned, illustrative SOC 100 is arranged in such a way that the physical layer, and part of the MAC layer, are implemented in WLAN baseband subsystem 110. All other layers, i.e., the rest of MAC layer, LLC layer, IP layer, and above, are implemented in host processors 102, 104. Consequently, interactions and communications between WLAN baseband 110 and host processors 102, 104 take place with high frequency during wireless transmission and reception. Presented immediately below, is an overview of the communication between host processors 102, 104 and WLAN baseband subsystem 110 in an illustrative embodiment of the present invention. In one illustrative embodiment of the present invention, all communication between host processors 102, 104 and the WLAN baseband subsystem 110 is performed by the exchange of messages. These messages are pre-defined information packages, covering all aspects of required information exchange between host processors 102, 104 and WLAN baseband subsystem 110. The following description outlines the four types of messages (TX control, Data TX request, RX control, and RX data) that are exchanged between host processors 102, 104 and WLAN baseband subsystem 110 in this illustrative embodiment of the present invention. Transmit (TX) control messages are initiated by one of the host processors 102, 104, and sent to the DSP of WLAN baseband subsystem 110. Examples of this type of message include: request for station initialization, request for power saving mode, request for PLL setting, request for beacon configuration, request for beacon update and so on. The size of each transmit control message in this illustrative embodiment is 16 bytes. Data TX request messages are initiated by a host processor and sent to WLAN baseband subsystem 110 if a data packet needs to be transmitted via wireless LAN. The size of each data TX request message, in this illustrative embodiment, is 32 bytes. Receive (RX) control messages are initiated by WLAN baseband subsystem 110 and sent to one of host processors 102, 104. Examples of this type of message include: messages to confirm the messages of all TX control and TX request, error indication messages when errors occur in WLAN baseband subsystem 110, and so on. The size of each RX control message, in this illustrative embodiment, is 16 bytes. RX data messages are messages that WLAN baseband subsystem 110 sends to one of the host processors 110 when it receives a data packet. The size of each RX data message, in this illustrative embodiment, is 20 bytes. In order to achieve improved system performance at reduced cost, embodiments of the present invention pass messages between subsystems, such as host processors 102, 104 and WLAN baseband subsystem 110 of the illustrative embodiment, efficiently, and in a cost effective manner. Inefficiencies due to message passing in previous architectures disadvantageously resulted in larger memory use and longer system latency, leading to higher cost and lower system performance. Existing methods for passing messages between host processors and a WLAN baseband subsystem employ the concept of shared memory, wherein the shared memory is allocated in the external system memory. In such existing methods, message queues are pre-allocated in the external system memory. The host processors and the WLAN baseband subsystem each have a copy of the write pointer and the read pointer so that the queue conditions can be obtained by both of them. For example, there is a queue for storing transmission request messages, of which the host processors are writers and the WLAN baseband subsystem is the reader. When a host processor writes a message to the queue, it updates the write pointer on its own side as well as the WLAN baseband subsystem side. When the WLAN baseband subsystem reads a message out of that queue, it updates the read pointer of its own side as well as that of the host processors. The roles are swapped for the receive control queue, as the WLAN baseband subsystem updates the write pointer of both sides when a message is written and the host processors update the read pointer of both sides when a message is read. One problem with the existing method is that the message passing operation normally becomes the bottleneck of overall system performance. This is caused by the inefficiency of memory access due to small burst size, as each message is at most 32 bytes in size. Disadvantages due to the memory access inefficiency include an increased requirement on memory bandwidth and system clock frequency, leading to higher system cost, and higher power consumption. Additionally, maintaining the write and read pointers of the message FIFOs by the host processors and WLAN baseband subsystem is inefficient, and is a direct waste of computation power and communication bandwidth. To address the disadvantages of previous approaches to communication between subsystems of an SOC, embodiments of the present invention provide a message intelligent module (MIM), which interfaces subsystems such as WLAN baseband subsystem 110, and the other parts of SOC 100. The illustrative embodiment of an MIM described herein includes several aspects of the present invention. In one aspect, messages exchanged between host processors 102, 104 and WLAN baseband subsystem 110 are all stored in FIFOs, which are internal to SOC 100. In another aspect of the present invention, all FIFOs support a yoyo mode, so that the size of the internal memory is kept minimal; yoyo mode allows the transparent offloading of the internal memory to external memory; thereby virtually increasing the capacity of the internal FIFOs without the notice of either WLAN baseband subsystem 110, or host processors 102, 104. In another aspect, a system independent interface, known as DTL, is used to connect MIM with the system buses of SOC 100. Such a system independent interface, e.g., the DTL interface, offers the flexibility of connecting to different system buses using bus adaptors and thus provides high reusability. The DTL protocol is a synchronous interface protocol owned by Philips Semiconductor and Philips Research. In a still further aspect, a unified buffer management scheme in which a buffer allocation for received data frames is managed the same way as other I/O devices, such as Ethernet MAC of SOC 100, is used. Prior to the storing of a received data frame, RX free buffer pointers are requested from the buffer manager of SOC 100 and the received frame data is thus stored in the memory location where the free buffer pointer is pointing. Large received data frames are fragmented into small segments by the MIM and each segment is stored in one data buffer. In a still further aspect of the present invention, a watermark-based interrupt scheme is used to support interrupt mitigation. In a still further aspect of the present invention, multiple transmit request FIFOs are supported for quality of service (QoS). The number of transmit requests is programmable; for example the number of transmit requests can be either 2, 3 or 5. As shown in the illustrative embodiment of MIM 200 in Fig. 2, there are eight FIFOs in total, each storing different types of messages that are exchanged between host processors 102, 104, and WLAN baseband subsystem 110. The FIFOs in this illustrative embodiment can operate in two modes: basic mode and yoyo mode. The mode in which each FIFO operates may be programmed independently. When in basic mode, a message FIFO has a fixed capacity for storing a designated number of messages. For example, a TX control message FIFO 202 has a capacity of storing 16 messages while a TX multicast request message FIFO 204 has a capacity of storing 8 messages. The capacity of each FIFO is described below, and is also shown in Fig. 2. When the capacity of a message FIFO reaches its limit, host processors 102, 104 can no longer store additional messages into that FIFO until enough space in the FIFO has been freed up. It is noted that the capacity of each FIFO needs to be determined based on the desired overall system performance. The present invention does not limit the capacity of any FIFO, and the present invention is applicable to any size FIFO. When in yoyo mode, a FIFO uses external memory to increase its capacity to store messages. The amount of external memory used in conjunction with each FIFO may be programmed independently. The threshold that triggers the memory offloading of each FIFO may also be updated, or programmed, independently. The threshold may be determined based at least in part on the characteristics of the external memory, such as, but not limited to access speed, access method, and latency. In accordance with the present invention, the yoyo read/write interface is configured in such a way that the offloading of an internal FIFO to external memory is transparent to both WLAN baseband subsystem 110 and host processors 102, 104. TX control message FIFO 202, which includes a yoyo interface, is the FIFO where host processors 102, 104 store TX control messages. The TX control messages are fetched by WLAN baseband subsystem 110 when there is enough space in the internal buffer of WLAN baseband subsystem 110. In basic mode, TX control message FIFO 202 has the capacity of storing 16 messages, and each TX control message is 16 bytes in size. In yoyo mode, TX control messages are stored in an external memory when the number of messages stored in the internal memory reaches a predetermined threshold. In this illustrative embodiment of the present invention the threshold is programmable. TX control message FIFO 202, together with the other message FIFOs, which are described below, are interfaced to a DTL target interface. The DTL target interface is then interfaced to a device control and status bus. Through the device control and status bus, host processors 102, 104 write TX control messages to TX control message FIFO 202. In this illustrative embodiment, two status registers, referred to as WLAN NT_STATUS and HOST NT STATUS, are included to report FIFO conditions to the WLAN baseband subsystem 110 and host processors 102, 104 respectively. The following FIFO conditions are indicated in register WLAN_INT_STATUS: TX control message FIFO empty (so that WLAN baseband subsystem 110 may go to sleep mode), TX control message FIFO transition from empty to not empty (so that WLAN baseband subsystem 110 may wake up from sleep mode), TX control message FIFO has new message available (so that WLAN baseband subsystem 110 may fetch more messages if possible). TX control message FIFO full condition is indicated in the register HOST_INT_STATUS. For each bit defined in WLAN_INT_STATUS, there is a corresponding bit defined in an interrupt enable register, WLAN_INT_ENABLE. An interrupt is raised to the WLAN baseband subsystem 110 only if both the enable bit and the status bit are asserted. The level of the FIFO is stored in a register, FIFO_LEVEL, which can be read by both WLAN baseband subsystem 110 and by host processors 102, 104. When one of host processors 102, 104 has a TX control message to write, it first checks if the FIFO full status bit is asserted in HOSTJNTJSTATUS. If the FIFO full status bit is asserted, then that host processor must wait until this bit is de-asserted. If the FIFO full status bit is not asserted, then that host processor writes the message to TX control message FIFO 202. It will be appreciated that the present invention is not limited to communicating the FIFO status as a bit in a register, but rather any suitable signal may be used, as long as that signal is indicative of the information intended to be conveyed. When the write is finished, the level of the TX control message FIFO is updated by MIM 200 in a register referred to as FIFO_LEVEL. The "new message available" status bit in register WLAN_INT_STATUS is also updated. WLAN baseband subsystem 110 knows that there are messages available either by interrupt or by polling. Subsequently, WLAN baseband subsystem 110 fetches the messages from TX control message FIFO 202 if there is free space in the corresponding queue in its internal buffer. In some embodiments of the present invention, a debugging mode is provided in which memory-write request messages and memory-read request messages are also stored in this FIFO. The yoyo interface allows messages stored in this FIFO to be stored to external memory when the number of messages reaches a predetermined threshold. In some embodiments of the present invention, this threshold is programmable. A buffer in the external memory, known as an extended TX control message FIFO, is allocated for this purpose, typically during system initialization. The base address, start and end addresses are all stored in MMIO registers 222, which can be read and written by host processors 102, 104. In this illustrative embodiment, the current pointer, and FIFO full and empty conditions of the extended TX control message FIFO, can also be read by host processors 102, 104 for diagnostic purposes only. The definition of a FIFO full condition for TX control message FIFO 202 in basic mode is different from that in yoyo mode. In basic mode, TX control message FIFO 202 becomes full when no more space is available in the TX control message FIFO 202. However, in yoyo mode, TX control message FIFO 202 becomes full when no more space is available in the extended TX control message FIFO. Various embodiments of the present invention may include at least one TX unicast request message FIFO 203. In this illustrative embodiment, the number of TX unicast request message FIFOs 203 is programmable, and can be programmed to one, two or four. The present invention is not limited to any particular number of unicast request message FIFOs 203. No matter how many TX unicast request message FIFOs 203 there are, the total capacity of the TX unicast request message FIFOs 203 is fixed, in this illustrative embodiment, to 32 messages, each of which is 32 bytes in size. For example, when the number of TX unicast request message FIFOs 203 is one, the FIFO has a capacity of storing 32 messages. When the number of TX unicast request message FIFOs 203 is two, each of the two FIFOs has a capacity of storing 16 messages. When the number of TX unicast request message FIFOs 203 is four, each of the four FIFOs has a capacity of storing 8 messages. In yoyo mode, the capacity of each of the TX unicast request message FIFOs 203 can be virtually increased by storing the messages to external system memory. The following FIFO conditions are each indicated in a register referred to as WLANJNT_STATUS: TX unicast request message FIFO empty, TX unicast request message FIFO transition from empty to not empty, and TX unicast request message FIFO has new messages available. The TX unicast request message FIFO full condition is indicated in the register HOSTJNTJSTATUS. The level of the TX unicast request message FIFO 203 is stored in the register referred to as FIFO_LEVEL, which can be read by both WLAN baseband subsystem 110 and host processors 102, 104. Similar to other message FIFOs, there is a yoyo interface that allows messages stored in this FIFO to be transferred to or from external memory automatically. When a host processor 102, 104 wants to have a unicast frame transmitted, it first prepares a TX unicast request message and stores that message in one of the TX unicast request message FIFOs 203, if the FIFO is not full. Usually, the data frame is fragmented in the external memory. The host processor thus needs to provide a DMA descriptor table that provides the fragmentation information and pointers to memory locations where the data frame is stored. Further, host processors 102, 104 may put into the TX request message a pointer that indicates the location of the DMA descriptor table in the external memory. When a host processor writes a message to the TX unicast request message FIFO 203, the level of the TX unicast request message FIFO is updated by MIM 200 in the register referred to as FIFOJ EVEL. The "new message available" status bit in the register referred to as WLANJNTJSTATUS is also updated. WLAN baseband subsystem 110 becomes aware of the new messages available either by an interrupt or by polling. WLAN baseband subsystem 110 subsequently fetches the messages from TX unicast request FIFO 203 if there is free space in the corresponding queue in its internal buffer. The TX multicast request message FIFO 204 is where a host processor stores TX request messages when it wants to transmit a multicast data frame. Usually, the data frame is fragmented in more than one segment in the external memory. Each TX request message has a pointer which points to a DMA descriptor table in external memory. The DMA descriptor table consists of pointers, each of which points to a segment of the multicast data frame to be transmitted. Each TX request message is 32 bytes in size, and the TX request message FIFO has the capacity of storing 8 messages. In yoyo mode, TX request messages are stored in the external memory when the number of messages stored in the internal memory reaches a predetermined threshold. In various embodiments of the present invention this predetermined threshold is programmable. The present invention is not limited to any particular threshold. A Host DMARW 206 is a single word DMA module for host processors 102, 104 to access registers and memories in WLAN baseband subsystem 110. The way in which the host processors read and write registers and memory of WLAN baseband subsystem 110 are described in greater detail below. A WLAN DMARW 208 is a DMA that WLAN baseband subsystem 110 uses to access both the message FIFOs of MIM 200, and the external system memory. Since the data flow of WLAN baseband subsystem 110 of this illustrative embodiment of the present invention is arranged in such a way that only one data access is programmed at a time, one DMA channel should be sufficient and is therefore shared by all data transfers. The DMA operation is described in greater detail below. Since Host DMARW 206 and WLAN baseband subsystem DMARW1 208 share a bus interface, these two DMA engines may have simultaneous requests for the bus interface. An arbiter 210 is therefore included, and performs the necessary arbitration between these two DMA engines 206, 208. An RX control message FIFO 212 with yoyo interface is where WLAN baseband subsystem 110 stores RX control messages meant for host processors 102, 104. In basic mode, RX control message FIFO 212 can store up to 16 control messages, and each control message is 16 bytes. In yoyo mode, RX control messages may be stored in the external memory when the number of messages stored in the internal memory reaches a predetermined threshold. In various embodiments of the present invention the threshold is programmable. The present invention is not limited to any particular threshold. Each RX control message is to confirm the status of a corresponding TX control message, which WLAN baseband subsystem 110 has fetched from TX Control message FIFO 202. This means that for each TX control message fetched by WLAN baseband subsystem 110, there is a corresponding RX control message sent back to the host. The following FIFO conditions are each indicated in a register referred to as HOSTJNTJSTATUS: RX control message FIFO empty, RX control message FIFO transition from empty to not empty, RX control message FIFO has new message available. RX control message FIFO full condition is indicated in the register referred to as WLANJNTJSTATUS. The level of RX control message FIFO 212 is stored in the register referred to as FIFO_LEVEL, which can be read by both WLAN baseband subsystem 110 and by host processors 102, 104. In operation, WLAN baseband subsystem 110 determines whether RX control message FIFO 212 is full before it transfers a message to RX control message FIFO 212. WLAN baseband subsystem 110 only transfers messages to RX control message FIFO 212 when this FIFO is not full. Host processors 102, 104 read the RX control messages through the device control and status bus , which is connected to RX control message FIFO 212 via a DTL adaptor and a DTL target interface. Yoyo DMARW 214 is a DMA that is used for offloading message FIFOs by transferring messages from the FIFOs to external memory. There is a predetermined threshold associated with each message FIFO. In various embodiments, the threshold for the various message FIFOs may be programmable. In accordance with the present invention, the predetermined threshold for the various message FIFOs may be the same, or may be set individually. When the threshold is reached, Yoyo DMARW module 214 automatically transfers the RX control messages to external memory. When the number of messages in the message FIFO is below the predetermined threshold, Yoyo DMARW will automatically fetch the messages from external memory (if there are any) and store them back to the associated message FIFO. The start address and end address of the external memory for the extension of each message FIFO are pre-configured by software during system initialization in this illustrative embodiment. However, the present invention is not limited to setting the start and end addresses by initialization software, and any suitable means of setting such memory boundaries may be used within the scope of the present invention. A RX data message FIFO 216 with yoyo interface is where the RX data messages are stored. A data message contains information about the reception of a data frame, and specifies the memory location, in terms of buffer pointers, where a data frame is stored. If the data frame can be saved in one data buffer, one buffer pointer is contained in the RX data message. If the data frame is too large to fit into one data buffer, then two data buffers can be used. In such a case, the RX data message contains two buffer pointers. The invention is not limited to any particular number of data buffers. In this illustrative embodiment, all of the data buffers have the same size, which size is programmed by software in the MMIO register referred to as DATAJ5UFFER SIZE. Such programming may take place during system initialization, but the invention is not limited to programming at system initialization. Register DATA J3UFFERJSIZE can be read and written by host processors 102, 104, and is readable by WLAN baseband subsystem 110. The buffer size has a typical value of 2K bytes. To program this value, the following factors are typically considered. First, the size must be large enough so that the largest WLAN MAC frame can be stored in no more than two such buffers. Second, for best memory utilization, the size needs to be as small as possible. Prior to the creation of an RX data message, WLAN baseband subsystem 110 fetches the free data buffer pointers from MIM 200, which in turn requests buffer pointers from the buffer manager. The format of the RX data frame is described in Fig. 3. WLAN DMARW2 218 is a DMA that is used to read data from, and write data to, the external memory. Prior to the start of a DMA operation, WLAN baseband subsystem 110 needs to program WLAN DMARW2 218 with the DMA start addresses (both source and destination) and the DMA burst size. For design re-use, a DTL interface is used for connection to the system bus so that MIM 200 can be used for different system buses with an appropriate adaptor. For the case of the memory bus, a DTL-to-memory-bus adaptor is used. Both YOYO DMARW 214 and WLAN DMARW2 218 access the external memory using the same DTL initiator interface, and an arbiter 220 performs the arbitration between these two DMA engines. Host MMIO registers 222 are the registers that can only be accessed by host processors 102, 104. Host processors 102, 104 get access to these registers via the device control and status bus. WLAN MMIO registers 224 are the registers that can only be accessed by WLAN baseband subsystem 110. WLAN baseband subsystem 110 gets access to these registers via the slave interface of MIM 200. Before an RX data frame is stored into the external memory, MIM 200 requests a free data buffer pointer from the buffer manager. A free data buffer pointer is the start address of a memory buffer where a data frame, or part of a data frame, can be stored. The buffer manager interface facilitates the interaction between MIM 200 and the buffer manager. For design reuse, a DTL initiator interface is introduced between the parse and demux module, and the DTL to buffer interface adaptor. In the case where WLAN baseband subsystem 110 is used in a SOC where there is no buffer manager, the DTL interface can be connected to other system buses, possibly through an appropriate adaptor. Host interrupt registers module 226 contains interrupt-related registers that can be accessed by host processors 102, 104. These registers include an interrupt-enable register, an interrupt-clear register, an interrupt-status register and an interrupt-set register. WLAN interrupt registers module 228 contains interrupt-related registers that can be accessed by WLAN baseband subsystem 110. There are two interrupt generation modules 230, 232. A host interrupt generation module 230, which generates interrupts to host processors 102, 104; and a WLAN interrupt generation module 232,which generates interrupts to WLAN baseband subsystem 110. Externally, MIM 200 interfaces to WLAN baseband subsystem 110 via two AHB buses. MIM 200 interfaces to the host through a memory bus and a device control and status bus, for external system memory access and host MMIO programming. There is a buffer manager interface through which MIM 200 communicates with the Buffer Manager. Internally, MIM 200 has three DTL interfaces and three adaptors for converting the DTL interfaces to a Buffer manager interface, a device control and status bus interface, and a memory bus interface respectively. In some embodiments of the present invention, the clock domains are separated in adaptors of the DTL to device control and status bus, and the DTL to memory bus, and in the DTL to BM interface adaptor. In this way, the entire MIM module may run at the clock speed of the WLAN baseband subsystem, which is slower than other parts of the SOC, and can thus reduce of the cost of the module accordingly. Host processors 102, 104 read and write to memory and registers in WLAN baseband subsystem 110 through three MMIO registers. These registers are defined in Tables 1, 2 and 3 as presented below.

Table 1 read/write address register (HOST2WLAN RW_ADDR)

Table 2 read/write data register (HOST2 WLAN JIWJD ATA)

Table 3 Host command and status register (HOST_COM_STATUS)

In the illustrative embodiment of the present invention, the following is the procedure host processors 102, 104 use to read from memory or registers in WLAN baseband subsystem 110. Host processors 102, 104 write the memory or register address into the read/write address register. Host processors 102, 104 write 0x1 to bit 0 of the command/status register to indicate a read operation. Host processors 102, 104 poll bit 2, i.e., the "read data ready" bit, of the command/status register till the state of this bit is a 1. Alternatively, host processors 102, 104 wait for a "read data ready" interrupt. Finally, host processors 102, 104 read data from the read/write data register. In the illustrative embodiment of the present invention, the following is the procedure host processors 102, 104 use to read from memory or registers in WLAN baseband subsystem 110. Host processors 102, 104 write the memory or register address in the read/write address register. Host processors 102, 104 write the data to be transferred to the read/write data register. Host processors 102, 104 write 0x1 to bit 1 of the command/status register to indicate the write operation. If the write-tag mode is enabled, this step can be skipped. Otherwise, host processors 102, 104 poll bit 3, i.e., the "write data ready" bit, of the command/status register till the state of this bit is a 1. Alternatively, host processors 102, 104 wait for a "write data ready" interrupt. When one of host processors 102, 104 has a frame to be transmitted, it first creates a DMA descriptor table in the external system memory, and a TX request message in TX Unicast Request Message FIFO 203 or TX Multicast Request Message FIFO 204, depending on the data frame type. Besides other information related to the transmission, the TX request message contains a pointer that points to a DMA descriptor table. Such a DMA descriptor table consists of pointers that point to all segments of the data frame to be transmitted (assuming the data frame is fragmented). When host processors 102, 104 write a TX request message in the TX request message FIFOs, an interrupt is raised to WLAN baseband subsystem 110. WLAN baseband subsystem 110 recognizes which FIFOs contain messages (empty flag not set in FIFOJSTATUS for the corresponding FIFO) and transfers such messages into its internal buffer. The following describes the procedure WLAN baseband subsystem 110 takes to transfer a unicast frame from external system memory to its internal memory. The same procedure applies to the transfer of a multicast frame, although the request message is from TX request message (multicast) FIFO 204 instead of TX request message (unicast) FIFO 203. When WLAN baseband subsystem 110 sees TXJJnicast request message FIFO 203 is not empty, and there is space in the internal memory of WLAN baseband subsystem 110, it fetches a TX request message from this message FIFO. WLAN baseband subsystem 110 obtains the pointer of a DMA descriptor table from the TX request message. WLAN baseband subsystem 110 fetches the DMA descriptor table, and, based on the DMA descriptor table, WLAN baseband subsystem 110 programs the DMA in MIM 200 to prefetch the first few data of the unicast data frame from the external memory through WLAN DMARW 1 208. When there is a TX opportunity, the pre-fetched data is sent and the remaining frame data will be fetched from host memory. When a data frame has been transmitted, host processors 102, 104 return the free buffer pointers back to the buffer manager for reuse. Host processors 102, 104, however, cannot release or give back the buffer pointer to the buffer manager immediately after the TX request message has been fetched by WLAN baseband subsystem 110, because the frame data has not been transferred to WLAN baseband subsystem 110 yet. Host processors 102, 104 can only release, or give back, the buffer pointer after a RX control message which confirms that the TX data frame has been successfully transmitted by the WLAN baseband subsystem 110 is received. It is therefore the responsibility of software to keep track of RX control messages and RX request messages so as to determine when a TX data frame buffer pointer can be returned to the buffer manager. For each TX control message that has been processed by WLAN baseband subsystem 110, a confirmation message, also known as RX control message, is created which is then transferred to RX control message FIFO 212. The following describes the procedure for storing an RX control message. WLAN baseband subsystem 110 programs the source and destination DMA addresses in WLAN MMIO registers 224,and starts the WLAN DMARWl module 208. An interrupt is raised to host processors 102, 104 when an RX control message is completely stored to RX control message FIFO 212. The data flow for transferring RX data messages to RX data message FIFO 216, and data frames to external system memory is now described. More particularly, when WLAN baseband subsystem 110 receives an RX frame and decides to store it in the system memory, it will first create an RX data message and store it in RX data message FIFO 216, following the steps below: The WLAN baseband subsystem 110 obtains one or two free buffer pointers by reading the free buffer pointer registers in MIM 200. If the RX data frame can be stored in one data buffer, one free buffer pointer is obtained. If the RX data frame is too large to fit into one data buffer, two free buffer pointers are obtained. WLAN baseband subsystem 110 obtains the buffer size from the register referred to as DATA_BUFFER_SIZE. WLAN baseband subsystem 110 creates a RX data message that includes the buffer pointer. WLAN baseband subsystem 110 transfers the RX data message to RX data message FIFO 216. Based on the free buffer pointers obtained, WLAN baseband subsystem 110 programs WLAN DMARWl 208 and WLAN DMARW2 218, and stores the RX data frame to external system memory. The Rx data message combines information from the Rx indication message header and the free buffer pointer obtained from the buffer manager. When one data buffer is not large enough to store a complete data frame, two data buffers, and therefore two free buffer pointers, are used. The fragmentation information is also provided in the Rx data message. The format of an illustrative RX data message is shown in Fig. 3. As can be seen in Fig. 3, this RX data message includes five words. The nature of the content of these five words is presented in detail in Tables 4, 5, 6, 7, and 8. Table 4 First word of the RX data message

Table 5 Second word of the RX data message

Table 6 Third word of the Rx data message

Table 8 - Fifth word of the RX data message for the first segment of an RX data frame

It is noted that when one of host processors 102, 104 has finished processing a received data frame, it should return the buffer pointers embedded in the data messages to the buffer manager. Referring to Fig. 4, a method of communicating between subsystems in an electronic system is described. The method shown in Fig. 4 includes writing 402 a first address from a first subsystem to a first register of a module in a second subsystem; writing 404 first data from the first subsystem to a second register of the module in the second subsystem; determining 406 whether there is sufficient available memory in a first FIFO disposed in the module for the data from the first subsystem to be written into the FIFO; transferring 408, the data from the second register to the first FIFO if the determination is affirmative; and transferring 410, the data from the second register to a memory external to the module if the determination is negative. Referring to Fig. 5, a method of message passing between subsystems incorporated on an integrated circuit is described. The method shown in Fig. 5 includes comparing 502 a predetermined threshold value to a number of messages stored in a first FIFO disposed on the integrated circuit; determining 504, based at least in part on comparing 502 whether the first FIFO can receive at least one more message; storing 506, if determination 504 is affirmative, a first message in the first FIFO; and storing 508, if determination 504 is negative, the first message in a memory external to the integrated circuit. Various embodiments of the present invention include methods and apparatus for exchanging messages between subsystems of an electronic system. In specific embodiments the subsystems are incorporated in an SOC. An advantage of some embodiments of the present invention, is that memory access bottlenecks are reduced. It is to be understood that the present invention is not limited to the embodiments described above, but encompasses any and all embodiments within the scope of the subjoined Claims.

Claims

What is claimed is: 1. An electronic system, comprising: a plurality of subsystems (102, 104, 110), the plurality of subsystems (102, 104, 110) operable to communicate with each other via message passing, and the plurality of subsystems (102, 104, 110) integrated onto a single chip (100); at least one bus coupled to the plurality of subsystems; a first FIFO (202) disposed between a first one of the plurality of subsystems (102, 104) and a second one of the plurality of subsystems (110), the first FIFO operable to buffer messages passed from the first subsystem (102, 104) to the second subsystem (110); first circuitry coupled to the first FIFO (202), and further coupled to second circuitry from which a predetermined threshold value can be obtained, for detennining whether sufficient memory is available in the first FIFO (202) to receive at least one additional message in the first FIFO (202); third circuitry, coupled to the first circuitry, operable to transfer message data addressed to the first FIFO (202) to an external memory buffer when it is determined that sufficient memory is not available in the first FIFO (202) to receive the at least one additional message in the first FIFO (202); and fourth circuitry, coupled to the external memory buffer and to the first FIFO (202), operable to indicate that the first FIFO (202) can not accept at least one additional message when the external memory buffer is full and the first FIFO (202) is filled to a level specified by the predetermined threshold value.

2. The electronic system of Claim 1, wherein the third circuitry is further operable to transfer at least one message from the external memory buffer to the first FIFO (202) when sufficient memory becomes available in the first FIFO (202) to store the at least one message.

3. The electronic system of Claim 2, wherein the third circuitry comprises a direct memory access (DMA) circuit (214).

4. The electronic system of Claim 1, wherein the second circuitry is operable to receive threshold value updates.

5. The electronic system of Claim 4, further comprising a register disposed between the first FIFO (202) and the first subsystem (102, 104).

6. The electronic system of Claim 5, further comprising: a first plurality of FIFOs (203, 204) disposed between the first subsystem (102, 104) and the second subsystem (110) for buffering messages sent from the first subsystem (102, 104) to the second subsystem (110); and a second plurality of FIFOs (212, 216) disposed between the first subsystem and the second subsystem for buffering messages sent from the second subsystem to the first subsystem.

7. The electronic system of Claim 6, further comprising WLAN baseband subsystem circuitry coupled to the first FIFO, the first plurality of FIFOs, and the second plurality of FIFOs.

8. A method of communicating between subsystems in an electronic system, comprising: a) writing (402) a first address from a first subsystem to a first register of a module in a second subsystem; b) writing (404) first data from the first subsystem to a second register of the module in the second subsystem; c) determining (406) whether there is sufficient available memory in a first FIFO disposed in the module for the data from the first subsystem to be written into the FIFO; d) transferring (408), if the determination of (c) is affirmative, the data from the second register to the first FIFO; and e) transferring (410), if the determination of (c) is negative, the data from the second register to a memory external to the module.

9. The method of Claim 8, wherein determining whether there is sufficient available memory in the first FIFO comprises comparing the amount of the FIFO memory that has been filled to a predetermined threshold.

10. The method of Claim 9, further comprising setting a value for the predetermined threshold.

11. The method of Claim 10. further comprising transferring message data from the external memory and storing that message data in the first FIFO.

12. The method of Claim 11, wherein transferring message to and from the external memory is performed by direct memory access (DMA).

13. A method of message passing between subsystems incorporated on an integrated circuit, comprising: a) comparing (502) a predetermined threshold value to a number of messages stored in a first FIFO disposed on the integrated circuit; b) determining (504), based at least in part on the comparing of (a), whether the first FIFO can receive at least one more message; c) storing (506), if the determination of (b) is affirmative, a first message in the first FIFO; and d) storing (508), if the determination of (b) is negative, the first message in a memory external to the integrated circuit.

14. The method of Claim 13, further comprising programming the predetermined threshold value.

15. The method of Claim 13, further comprising: e) determining, if the first message was stored in the memory external to the integrated circuit, whether to fetch the first message from external memory and store the first message in the first FIFO.

16. The method o f Claim 14, wherein the predetermined threshold value is based, at least in part, on the access characteristics of the external memory.

17. The method of Claim 13, further comprising: generating one or more signals indicative of whether there is sufficient capacity in the first FIFO and the external memory to store a message.

18. The method of Claim 17, wherein the storing the first message in the external memory is performed by DMA.

19. The method of Claim 13, wherein the external memory where the messages are stored is of a known size, and that size is programmable.