WO2005122027A3 - Local preferred direction routing and layout generation - Google Patents

Local preferred direction routing and layout generation Download PDF

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Publication number
WO2005122027A3
WO2005122027A3 PCT/US2005/019359 US2005019359W WO2005122027A3 WO 2005122027 A3 WO2005122027 A3 WO 2005122027A3 US 2005019359 W US2005019359 W US 2005019359W WO 2005122027 A3 WO2005122027 A3 WO 2005122027A3
Authority
WO
WIPO (PCT)
Prior art keywords
local preferred
preferred direction
layout generation
direction routing
regions
Prior art date
Application number
PCT/US2005/019359
Other languages
French (fr)
Other versions
WO2005122027A2 (en
Inventor
Asmus Hetzel
Anish Malhotra
Deepak Cherukuri
Etienne Jacques
Jon Frankle
Original Assignee
Cadence Design Systems Inc
Asmus Hetzel
Anish Malhotra
Deepak Cherukuri
Etienne Jacques
Jon Frankle
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/005,169 external-priority patent/US7412682B2/en
Priority claimed from US11/005,162 external-priority patent/US7707537B2/en
Priority claimed from US11/005,448 external-priority patent/US7340711B2/en
Application filed by Cadence Design Systems Inc, Asmus Hetzel, Anish Malhotra, Deepak Cherukuri, Etienne Jacques, Jon Frankle filed Critical Cadence Design Systems Inc
Priority to EP05755944A priority Critical patent/EP1756741A4/en
Publication of WO2005122027A2 publication Critical patent/WO2005122027A2/en
Publication of WO2005122027A3 publication Critical patent/WO2005122027A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing

Abstract

A method for defining routes in a design layout with at least one particular wiring layer that has at least two regions (200, 300) with different local preferred wiring directions (210, 305). The method then uses the differing local preferred wiring directions (205, 215) to define a detailed route on the wiring layer. In some embodiments, the method defines a first route (210) that traverse first (200) and second regions (300) between two layers by using a first via that has a first pad in the second region.
PCT/US2005/019359 2004-06-04 2005-06-04 Local preferred direction routing and layout generation WO2005122027A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP05755944A EP1756741A4 (en) 2004-06-04 2005-06-04 Local preferred direction routing and layout generation

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US57743404P 2004-06-04 2004-06-04
US60/577,434 2004-06-04
US11/005,162 2004-12-06
US11/005,169 US7412682B2 (en) 2004-06-04 2004-12-06 Local preferred direction routing
US11/005,169 2004-12-06
US11/005,448 2004-12-06
US11/005,162 US7707537B2 (en) 2004-06-04 2004-12-06 Method and apparatus for generating layout regions with local preferred directions
US11/005,448 US7340711B2 (en) 2004-06-04 2004-12-06 Method and apparatus for local preferred direction routing

Publications (2)

Publication Number Publication Date
WO2005122027A2 WO2005122027A2 (en) 2005-12-22
WO2005122027A3 true WO2005122027A3 (en) 2006-05-04

Family

ID=35503797

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/019359 WO2005122027A2 (en) 2004-06-04 2005-06-04 Local preferred direction routing and layout generation

Country Status (2)

Country Link
EP (1) EP1756741A4 (en)
WO (1) WO2005122027A2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7441220B2 (en) 2000-12-07 2008-10-21 Cadence Design Systems, Inc. Local preferred direction architecture, tools, and apparatus
US7707537B2 (en) 2004-06-04 2010-04-27 Cadence Design Systems, Inc. Method and apparatus for generating layout regions with local preferred directions
US10331840B2 (en) 2016-01-15 2019-06-25 International Business Machines Corporation Resource aware method for optimizing wires for slew, slack, or noise

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4571451A (en) * 1984-06-04 1986-02-18 International Business Machines Corporation Method for routing electrical connections and resulting product
US4910680A (en) * 1987-03-26 1990-03-20 Kabushiki Kaisha Toshiba Wiring method for semiconductor integrated circuit
US5375069A (en) * 1989-12-18 1994-12-20 Hitachi, Ltd. Wiring routes in a plurality of wiring layers
US5673201A (en) * 1992-09-29 1997-09-30 International Business Machines Corporation Sub-problem extraction method for wiring localized congestion areas in VLSI wiring design
US5798936A (en) * 1996-06-21 1998-08-25 Avant| Corporation Congestion-driven placement method and computer-implemented integrated-circuit design tool
US20040098696A1 (en) * 2002-11-18 2004-05-20 Steven Teig Method and apparatus for routing
US20040098697A1 (en) * 2002-11-18 2004-05-20 Jonathan Frankle Method and apparatus for routing with independent goals on different layers

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0290368A (en) * 1988-09-28 1990-03-29 Fujitsu Ltd Production for automatic lead-out wiring data on terminal of surface mount device parts
US5258920A (en) * 1989-12-26 1993-11-02 General Electric Company Locally orientation specific routing system
US5224022A (en) * 1990-05-15 1993-06-29 Microelectronics And Computer Technology Corporation Reroute strategy for high density substrates
JP2759573B2 (en) * 1992-01-23 1998-05-28 株式会社日立製作所 Circuit board wiring pattern determination method
US6516455B1 (en) * 2000-12-06 2003-02-04 Cadence Design Systems, Inc. Partitioning placement method using diagonal cutlines
US7073150B2 (en) * 2000-12-07 2006-07-04 Cadence Design Systems, Inc. Hierarchical routing method and apparatus that use diagonal routes
US6915500B1 (en) * 2001-06-03 2005-07-05 Cadence Design Systems, Inc. Method and arrangement for layout and manufacture of nonmanhattan semiconductor integrated circuit using simulated Euclidean wiring
US7216308B2 (en) * 2002-11-18 2007-05-08 Cadence Design Systems, Inc. Method and apparatus for solving an optimization problem in an integrated circuit layout

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4571451A (en) * 1984-06-04 1986-02-18 International Business Machines Corporation Method for routing electrical connections and resulting product
US4910680A (en) * 1987-03-26 1990-03-20 Kabushiki Kaisha Toshiba Wiring method for semiconductor integrated circuit
US5375069A (en) * 1989-12-18 1994-12-20 Hitachi, Ltd. Wiring routes in a plurality of wiring layers
US5673201A (en) * 1992-09-29 1997-09-30 International Business Machines Corporation Sub-problem extraction method for wiring localized congestion areas in VLSI wiring design
US5798936A (en) * 1996-06-21 1998-08-25 Avant| Corporation Congestion-driven placement method and computer-implemented integrated-circuit design tool
US20040098696A1 (en) * 2002-11-18 2004-05-20 Steven Teig Method and apparatus for routing
US20040098697A1 (en) * 2002-11-18 2004-05-20 Jonathan Frankle Method and apparatus for routing with independent goals on different layers

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
KOH C ET AL: "Manhattan or Non-Manhattan?, A Study of Alternative VLSI Routing Architectures.", GREAT LAKES SYMPOSIUM ON VLSI., 2000, pages 47 - 52, XP002995026 *
See also references of EP1756741A4 *

Also Published As

Publication number Publication date
EP1756741A2 (en) 2007-02-28
EP1756741A4 (en) 2007-09-05
WO2005122027A2 (en) 2005-12-22

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