WO2006033099A3 - States encoding in multi-bit flash cells for optimizing error rate - Google Patents

States encoding in multi-bit flash cells for optimizing error rate Download PDF

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Publication number
WO2006033099A3
WO2006033099A3 PCT/IL2005/001001 IL2005001001W WO2006033099A3 WO 2006033099 A3 WO2006033099 A3 WO 2006033099A3 IL 2005001001 W IL2005001001 W IL 2005001001W WO 2006033099 A3 WO2006033099 A3 WO 2006033099A3
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WO
WIPO (PCT)
Prior art keywords
bit
bit ordering
error rate
flash cells
bit flash
Prior art date
Application number
PCT/IL2005/001001
Other languages
French (fr)
Other versions
WO2006033099A2 (en
Inventor
Menachem Lasser
Original Assignee
Milsys Ltd
Menachem Lasser
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Milsys Ltd, Menachem Lasser filed Critical Milsys Ltd
Publication of WO2006033099A2 publication Critical patent/WO2006033099A2/en
Publication of WO2006033099A3 publication Critical patent/WO2006033099A3/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5648—Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation

Abstract

Memory Cells are programmed and read (20), at least M=3 data bits per cell, according to a Valid nonserial physical bit ordering (22) with, reference to a logical bit ordering (24). The logical bit ordering is chosen to give a more even distribution of error probabilities of the bits, relative to the probability distributions of the data error and the cell state transition error, than would be provided by the physical bit ordering alone. Preferably, both bit Orderings have 2 M-1 transitions. Preferably, the logical bit ordering is evenly distributed. The translation between the bit orderings is done by software or hardware.
PCT/IL2005/001001 2004-09-22 2005-09-19 States encoding in multi-bit flash cells for optimizing error rate WO2006033099A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US61187304P 2004-09-22 2004-09-22
US60/611,873 2004-09-22
US11/061,634 2005-02-22
US11/061,634 US20050213393A1 (en) 2004-03-14 2005-02-22 States encoding in multi-bit flash cells for optimizing error rate

Publications (2)

Publication Number Publication Date
WO2006033099A2 WO2006033099A2 (en) 2006-03-30
WO2006033099A3 true WO2006033099A3 (en) 2007-05-18

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Application Number Title Priority Date Filing Date
PCT/IL2005/001001 WO2006033099A2 (en) 2004-09-22 2005-09-19 States encoding in multi-bit flash cells for optimizing error rate

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US (3) US20050213393A1 (en)
KR (1) KR20070054659A (en)
WO (1) WO2006033099A2 (en)

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