WO2006065668B1 - Non-volatile memory and method with multi-stream updating - Google Patents

Non-volatile memory and method with multi-stream updating

Info

Publication number
WO2006065668B1
WO2006065668B1 PCT/US2005/044720 US2005044720W WO2006065668B1 WO 2006065668 B1 WO2006065668 B1 WO 2006065668B1 US 2005044720 W US2005044720 W US 2005044720W WO 2006065668 B1 WO2006065668 B1 WO 2006065668B1
Authority
WO
WIPO (PCT)
Prior art keywords
data
page
nonvolatile memory
storage
memory
Prior art date
Application number
PCT/US2005/044720
Other languages
French (fr)
Other versions
WO2006065668A2 (en
WO2006065668A3 (en
Inventor
Peter John Smith
Sergey Anatolievich Gorobets
Alan David Bennett
Original Assignee
Sandisk Corp
Peter John Smith
Sergey Anatolievich Gorobets
Alan David Bennett
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/016,285 external-priority patent/US7315916B2/en
Application filed by Sandisk Corp, Peter John Smith, Sergey Anatolievich Gorobets, Alan David Bennett filed Critical Sandisk Corp
Priority to EP05853602.0A priority Critical patent/EP1839115B1/en
Priority to KR1020077015224A priority patent/KR101202620B1/en
Priority to CN2005800473818A priority patent/CN101124555B/en
Priority to JP2007546782A priority patent/JP4431175B2/en
Publication of WO2006065668A2 publication Critical patent/WO2006065668A2/en
Publication of WO2006065668A3 publication Critical patent/WO2006065668A3/en
Publication of WO2006065668B1 publication Critical patent/WO2006065668B1/en
Priority to IL183978A priority patent/IL183978A0/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0616—Improving the reliability of storage systems in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7203—Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators

Abstract

In a memory that is programmable page by page and each page having multiple sectors that are once-programmable, even if successive writes are sequential, the data recorded to an update block may be fragmented and non-sequential. Instead of recording update data to an update block, the data is being recorded in at least two interleaving streams. When a full page of data is available, it is recorded to the update block. Otherwise, it is temporarily recorded to the scratch pad block until a full page of data becomes available to be transferred to the update block. Preferably, a pipeline operation allows the recording to the update block to be set up as soon as the host write command indicates a full page could be written. If the actual write data is incomplete due to interruptions, the setup will be canceled and recording is made to the scratch pad block instead.

Claims

AMENDED CLAIMS
[received by the International Bureau on 8th December 2006 (08.12.06)]
46. A method as in any one of claims 32-44, wherein said first and second nonvolatile storages are constituted from memory cells that individually store more than one bit of data.
47. A nonvolatile memory comprising: a memory organized into a plurality of blocks, each block being a plurality of memory units that are erasable together, each memory unit for storing a logical unit of data; a controller for controlling operations of said blocks; first and second blocks, each for recording data from a host; a buffer for receiving the data from the host; and said controller controlling loading the data as it is being received to a set of data latches for programming the first storage and to a set of data latches for programming the second storage; addressing either the first or second storage depending on whether or not a predetermined condition is satisfied based on the data received; and programming the data to the addressed storage from its set of data latches.
48. A nonvolatile memory as in claim 47, wherein said nonvolatile memory is in the form of a removable memory card.
49. A nonvolatile memory as in claim 47, wherein: said data from the host is update data for a group of data units; said first block is for storing said update data; and said second block is for buffering said update data before being transferred to the first block.
50. A nonvolatile memory as in claim 47, wherein: the data is organized into data units having a predetermined order; and said first and second blocks are organized into pages, each page for programming together multiple data units having predetermined page offsets.
51. A nonvolatile memory as in claim 49, wherein each page is once- programmable after an erase.
52. A nonvolatile memory as in claim 47, wherein: said predetermined condition is when one of the received data units has a page-end offset; and said controller controlling recording the data to said first block includes recording to a page of said first block said page-end data unit and any preceding data units in the page.
53. A nonvolatile memory as in claim 47, wherein: said controller controlling recording the data to said second storage includes recording to a page thereof at least one index of the data stored in the second storage.
54- A nonvolatile memory as in claim 52, wherein said at least one index of the data stored in the second storage is recorded to a location of said page having a page-end offset,
55. A nonvolatile memory as in claim 47, wherein: said controller controlling recording the data to said second storage includes recording to a page thereof at least one index of the data stored in the first and second storages.
56. A nonvolatile memory as in claim 54, wherein said at least one index of the data stored in the first and second storages is recorded to a location of said page having a page-end offset.
57. A nonvolatile memory as in claim 47, wherein: said controller controlling recording the data to said second storage includes recording to a page thereof a pointer pointing to the next recording location of the first storage.
58. A nonvolatile memory as in claim 56, wherein said, pointer is recorded to a location of a page having said page-end offset.
59. A nonvolatile memory comprising: a memory organized into a plurality of blocks, each block being a plurality of memory units that are erasable together, each memory unit for storing a logical unit of data; first and second blocks, each for sequentially recording data from a host; a buffer for receiving the data from the host; and means for loading the data as it is being received to a set of data latches for programming the first storage and to a set of data latches for programming the second storage; means for addressing either the first or second storage depending on whether or not a predetermined condition is satisfied based on the data received; and means for recording the data to the addressed storage from its set of data latches.
60. A nonvolatile memory as in any one of claims 47-59, wherein the first and second nonvolatile storages are constituted from memory cells that individually store one bit of data-
61. A nonvolatile memory as in any one of claims 47-59, wherein said first and second nonvolatile storages are constituted from memory cells that individually store more than one bit of data.
PCT/US2005/044720 2004-12-16 2005-12-08 Non-volatile memory and method with multi-stream updating WO2006065668A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP05853602.0A EP1839115B1 (en) 2004-12-16 2005-12-08 Non-volatile memory and method with multi-stream updating
KR1020077015224A KR101202620B1 (en) 2004-12-16 2005-12-08 Non-volatile memory and method with multi-stream updating
CN2005800473818A CN101124555B (en) 2004-12-16 2005-12-08 Non-volatile memory and method with multi-stream updating
JP2007546782A JP4431175B2 (en) 2004-12-16 2005-12-08 Non-volatile memory and method with multi-stream update
IL183978A IL183978A0 (en) 2004-12-16 2007-06-17 Non-volatile memory and method with multi-stream updating

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/016,285 US7315916B2 (en) 2004-12-16 2004-12-16 Scratch pad block
US11/016,285 2004-12-16
US11/191,686 2005-07-27
US11/191,686 US7412560B2 (en) 2004-12-16 2005-07-27 Non-volatile memory and method with multi-stream updating

Publications (3)

Publication Number Publication Date
WO2006065668A2 WO2006065668A2 (en) 2006-06-22
WO2006065668A3 WO2006065668A3 (en) 2006-12-07
WO2006065668B1 true WO2006065668B1 (en) 2007-02-22

Family

ID=36127498

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/044720 WO2006065668A2 (en) 2004-12-16 2005-12-08 Non-volatile memory and method with multi-stream updating

Country Status (7)

Country Link
US (2) US7412560B2 (en)
EP (2) EP1839115B1 (en)
JP (1) JP4431175B2 (en)
KR (1) KR101202620B1 (en)
IL (1) IL183978A0 (en)
TW (1) TWI417717B (en)
WO (1) WO2006065668A2 (en)

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