WO2006073829A3 - Bonding method for reducing stress in multilayered wafer - Google Patents

Bonding method for reducing stress in multilayered wafer Download PDF

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Publication number
WO2006073829A3
WO2006073829A3 PCT/US2005/046376 US2005046376W WO2006073829A3 WO 2006073829 A3 WO2006073829 A3 WO 2006073829A3 US 2005046376 W US2005046376 W US 2005046376W WO 2006073829 A3 WO2006073829 A3 WO 2006073829A3
Authority
WO
WIPO (PCT)
Prior art keywords
different
items
bonded
bonding method
reducing stress
Prior art date
Application number
PCT/US2005/046376
Other languages
French (fr)
Other versions
WO2006073829A2 (en
Inventor
Robert D Horning
Original Assignee
Honeywell Int Inc
Robert D Horning
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Int Inc, Robert D Horning filed Critical Honeywell Int Inc
Priority to JP2007550390A priority Critical patent/JP2008526537A/en
Priority to EP05855006A priority patent/EP1833754A2/en
Publication of WO2006073829A2 publication Critical patent/WO2006073829A2/en
Publication of WO2006073829A3 publication Critical patent/WO2006073829A3/en

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Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C3/00—Assembling of devices or systems from individually processed components
    • B81C3/001—Bonding of two components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00—Forming microstructural systems
    • B81C2203/03—Bonding two components
    • B81C2203/031—Anodic bondings

Abstract

An approach where items of different temperatures are bonded to each other such that upon cooling down they contract in size resulting in zero residual stress between the bonded items at an ambient temperature. If materials of the bonded items have different thermal expansion coefficients and the items are put together at different bonding temperatures, then they may have insignificant residual stress upon cooling down to the ambient temperature (e.g., room temperature) because the different ranges of the temperature drops compensate for the different contractions.
PCT/US2005/046376 2005-01-07 2005-12-21 Bonding method for reducing stress in multilayered wafer WO2006073829A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007550390A JP2008526537A (en) 2005-01-07 2005-12-21 Bonding system with stress control
EP05855006A EP1833754A2 (en) 2005-01-07 2005-12-21 Bonding method for reducing stress in multilayered wafer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/031,276 US7691723B2 (en) 2005-01-07 2005-01-07 Bonding system having stress control
US11/031,276 2005-01-07

Publications (2)

Publication Number Publication Date
WO2006073829A2 WO2006073829A2 (en) 2006-07-13
WO2006073829A3 true WO2006073829A3 (en) 2006-08-24

Family

ID=36577423

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2005/046376 WO2006073829A2 (en) 2005-01-07 2005-12-21 Bonding method for reducing stress in multilayered wafer

Country Status (4)

Country Link
US (1) US7691723B2 (en)
EP (1) EP1833754A2 (en)
JP (1) JP2008526537A (en)
WO (1) WO2006073829A2 (en)

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US20070264796A1 (en) * 2006-05-12 2007-11-15 Stocker Mark A Method for forming a semiconductor on insulator structure
KR20100052167A (en) * 2008-11-10 2010-05-19 삼성전자주식회사 Method and apparatus for bonding wafers
KR101589897B1 (en) * 2009-05-18 2016-01-29 박기용 Submount Bonding Method and the Apparatus
JP5882939B2 (en) * 2013-05-01 2016-03-09 東京エレクトロン株式会社 Joining method, joining apparatus and joining system
JP2017530378A (en) * 2014-06-26 2017-10-12 イェノプティック オプティカル システムズ ゲーエムベーハー Method, apparatus, and membrane unit for manufacturing an optical element including a micro optical structure
EP3561870A4 (en) * 2016-12-23 2020-11-25 Lumens Co., Ltd. Micro led module and manufacturing method therefor
JP2023095460A (en) * 2021-12-24 2023-07-06 東京エレクトロン株式会社 Joint method and joint device

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Also Published As

Publication number Publication date
JP2008526537A (en) 2008-07-24
WO2006073829A2 (en) 2006-07-13
US7691723B2 (en) 2010-04-06
EP1833754A2 (en) 2007-09-19
US20060154443A1 (en) 2006-07-13

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