WO2006084177A3 - Nested integrated circuit package on package system - Google Patents

Nested integrated circuit package on package system Download PDF

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Publication number
WO2006084177A3
WO2006084177A3 PCT/US2006/003927 US2006003927W WO2006084177A3 WO 2006084177 A3 WO2006084177 A3 WO 2006084177A3 US 2006003927 W US2006003927 W US 2006003927W WO 2006084177 A3 WO2006084177 A3 WO 2006084177A3
Authority
WO
WIPO (PCT)
Prior art keywords
package
integrated circuit
nested
nested integrated
circuit package
Prior art date
Application number
PCT/US2006/003927
Other languages
French (fr)
Other versions
WO2006084177A2 (en
Inventor
Hyun Uk Kim
Original Assignee
Stats Chippac Ltd
Stats Chippac Inc
Hyun Uk Kim
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Stats Chippac Ltd, Stats Chippac Inc, Hyun Uk Kim filed Critical Stats Chippac Ltd
Priority to JP2007554259A priority Critical patent/JP2008533700A/en
Priority to KR1020077018095A priority patent/KR101099773B1/en
Publication of WO2006084177A2 publication Critical patent/WO2006084177A2/en
Publication of WO2006084177A3 publication Critical patent/WO2006084177A3/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/13Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
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    • H01L23/00Details of semiconductor or other solid state devices
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    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
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    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2225/06568Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
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    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
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    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
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    • H01L2924/3025Electromagnetic shielding

Abstract

A package on package system (100) is provided including providing a first substrate (106) having a first integrated circuit (126) thereon and a second substrate (110) having a second integrated circuit (402) thereon, the second substrate (110) having a recess (112) provided therein. The first and second substrates (106) (110) are mounted having the first integrated circuit (126) at least partially nested in the recess (112).
PCT/US2006/003927 2005-02-04 2006-02-04 Nested integrated circuit package on package system WO2006084177A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2007554259A JP2008533700A (en) 2005-02-04 2006-02-04 Nested integrated circuit package on package system
KR1020077018095A KR101099773B1 (en) 2005-02-04 2006-02-04 Nested integrated circuit package on package system

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US65027905P 2005-02-04 2005-02-04
US60/650,279 2005-02-04
US11/257,894 US7279786B2 (en) 2005-02-04 2005-10-24 Nested integrated circuit package on package system
US11/257,894 2005-10-24

Publications (2)

Publication Number Publication Date
WO2006084177A2 WO2006084177A2 (en) 2006-08-10
WO2006084177A3 true WO2006084177A3 (en) 2009-04-09

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/003927 WO2006084177A2 (en) 2005-02-04 2006-02-04 Nested integrated circuit package on package system

Country Status (4)

Country Link
US (2) US7279786B2 (en)
JP (1) JP2008533700A (en)
KR (1) KR101099773B1 (en)
WO (1) WO2006084177A2 (en)

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US7897503B2 (en) * 2005-05-12 2011-03-01 The Board Of Trustees Of The University Of Arkansas Infinitely stackable interconnect device and method
US7528474B2 (en) * 2005-05-31 2009-05-05 Stats Chippac Ltd. Stacked semiconductor package assembly having hollowed substrate
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US20060175696A1 (en) 2006-08-10
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