WO2006103167A1 - Configurable ports for a host ethernet adapter - Google Patents

Configurable ports for a host ethernet adapter Download PDF

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Publication number
WO2006103167A1
WO2006103167A1 PCT/EP2006/060732 EP2006060732W WO2006103167A1 WO 2006103167 A1 WO2006103167 A1 WO 2006103167A1 EP 2006060732 W EP2006060732 W EP 2006060732W WO 2006103167 A1 WO2006103167 A1 WO 2006103167A1
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WO
WIPO (PCT)
Prior art keywords
data
high speed
nic
adapter
receive
Prior art date
Application number
PCT/EP2006/060732
Other languages
French (fr)
Inventor
Claude Basso
Jean Calvignac
Chih-Jen Chang
Natarajan Vaidhyanathan
Philippe Damon
Fabrice Verplanken
Colin Beaton Verrilli
Original Assignee
International Business Machines Corporation
Compagnie Ibm France
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corporation, Compagnie Ibm France filed Critical International Business Machines Corporation
Priority to EP06708770A priority Critical patent/EP1875678A1/en
Publication of WO2006103167A1 publication Critical patent/WO2006103167A1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40032—Details regarding a bus interface enhancer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/407—Bus networks with decentralised control
    • H04L12/413—Bus networks with decentralised control with random access, e.g. carrier-sense multiple-access with collision detection (CSMA-CD)
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/12—Protocol engines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
    • H04L69/161—Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/18—Multiprotocol handlers, e.g. single devices capable of handling multiple protocols
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/323—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the physical layer [OSI layer 1]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/30—Definitions, standards or architectural aspects of layered protocol stacks
    • H04L69/32—Architecture of open systems interconnection [OSI] 7-layer type protocol stacks, e.g. the interfaces between the data link level and the physical level
    • H04L69/322—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions
    • H04L69/324—Intralayer communication protocols among peer entities or protocol data unit [PDU] definitions in the data link layer [OSI layer 2], e.g. HDLC
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/16—Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]

Definitions

  • the present invention relates generally to a server environment and more specifically to adapters utilized in such an environment.
  • RPS920050059US1/3485P entitled “Host Ethernet Adapter for Networking Offload in Server Environment”, filed on even date herewith and assigned to the assignee of the present invention.
  • RPS920050060US1/3486P entitled "Method and System for Accommodating Several Ethernet Ports and a Wrap Transmitted Flow Handled by a Simplified Frame-By-Frame Upper Structure", filed on even date herewith and assigned to the assignee of the present invention.
  • RPS920050076US1/3505P entitled “Method and Apparatus for Blind Checksum and Correction for Network Transmissions”, filed on even date herewith and assigned to the assignee of the present invention.
  • RPS920050082US1/3512P entitled “Method and System for Performing a Packet Header Lookup”, filed on even date herewith and assigned to the assignee of the present invention.
  • an adapter which can be utilized in a server environment which can accommodate multiple data sources but does not have any of the above-identified problems.
  • the adapter should be easily implemented utilizing existing technologies.
  • the adapter should also be cost effective and easily adapted to existing server environments.
  • the present invention addresses such a need.
  • the adapter comprises a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor.
  • the plurality of layers include a high speed serializer/deserializer (high speed serdes) to receive data from and provide data to different speed data sources on the same pins.
  • a system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources.
  • the high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources.
  • the system allows for the adapter to use the same pins for multiple data sources.
  • FIG. 1 is a block diagram of a server system in accordance with the present invention.
  • Figure 2 is a simple block diagram of the a Host Ethernet Adapter (HEA) in accordance with the present invention.
  • HSA Host Ethernet Adapter
  • Figure 3 is a block diagram of the HEA with a more detailed view of the MAC and Serdes Layer.
  • FIG. 4 is a more detailed diagram of the high speed serdes.
  • the present invention relates generally to a server environment and more specifically to adapters utilized in such an environment.
  • the following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements.
  • Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art.
  • the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.
  • a system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins.
  • FIG. 1 is a block diagram of a server system 100 in accordance with the present invention.
  • the server system 100 includes a processor 102 which is coupled between a memory 104 and an interface adapter chip 106.
  • the interface adapter chip 106 includes an interface 108 to the private (Gx) bus of the processor 102 and a Host Ethernet Adapter (HEA) 110.
  • the HEA 110 receives and transmits signals from and to the processor 102.
  • the HEA 110 is an integrated Ethernet adapter.
  • a set of accelerator features are provided such that a server TCP/IP stack uses those features when and as required.
  • the interface between the processor 102 and the interface adapter chip 106 has been streamlined by bypassing the PCI bus and providing interface techniques that enable demultiplexing and multiqueueing and packet header separation. In so doing an Ethernet adapter is provided that allows for improved functionality with high speed system while allowing for compatibility with legacy server environments.
  • FIG. 2 is a simple block diagram of the HEA 110 in accordance with the present invention.
  • the HEA 110 has a three layer architecture.
  • the first layer comprises a Media Access Controller (MAC) and Serialization/Deserialization (Serdes) layer 202 which provides a plurality of interfaces from and to other devices on the Ethernet network.
  • MAC Media Access Controller
  • Serdes Serialization/Deserialization
  • the same chip I/Os are used to provide a plurality of interfaces.
  • the same chip I/Os are utilized to provide either a 10 Gigabit interface or multiple 1 Gigabit interfaces.
  • the second layer comprises a Packet Acceleration and Virtualization Layer 204.
  • the layer 204 provides for receiving packets and demultiplexing the flow of packets for enabling virtualization.
  • the layer 204 enables virtualization or partitioning of the operating system of a server based upon the packets.
  • the layer 204 also provides packet header separation to enable zero copy operations and therefore provide improved latency. Also since layer 204 interacts directly with the private bus (Gx) through the Host Interface Layer 206, a low latency, high bandwidth connection is provided.
  • the third layer comprises the Host Interface Layer 206.
  • the Host Interface Layer 206 provides the interface to the Gx or private bus of the processor and communicates with layer 204.
  • the layer 206 provides for multiple receive sub-queues per Queue Pair (QP) to enable effective buffer management for a TCP stack.
  • QP receive sub-queues per Queue Pair
  • the host layer 206 provides the context management for a given flow of data packets.
  • FIG. 3 is a block diagram of the HEA 110 with a more detailed view of the MAC and Serdes Layer 202.
  • the MACs 302, 304a and 304b include physical coding units 308a, 308b and 308c for aligning and coding the received packets.
  • the MACs 302, 304a and 304b are coupled to a High Speed Serializer/Deserialization (high speed serdes) 306.
  • the high speed serdes 306 is capable of receiving data from and providing data to one 10 G source or four 1 G.
  • FIG. 4 is a more detailed diagram of the high speed serdes 306.
  • the high speed serdes 306 includes a receive section 602 and a transmit section 604. There are four lanes associated with the high speed serdes 306. Each lane corresponds to one up bottom arrow and one down bottom arrow on the receive section 602 and the transmit section 604 respectively. In this embodiment a 10 G source requires four lanes and a 1 G source requires one lane.
  • the high speed serdes 306 also includes a Phase Locked Loop (PLL) 606 which receives a reference clock signal from the NIC (not shown).
  • the reference clock is relatively low compared to the data sources because the PLL 606 can be set to different frequency multiplication ratios to allow the different data sources.
  • the high speed serdes 306 also can configured to allow for multiple modes of operation. In so doing, the different data sources can be accommodated since the PLL 606 has different multiplication ratios.
  • 1G data source Half-rate mode at 1.25 Gbps
  • the same high speed serdes Ref Clock can be used in both modes, because internal high speed serdes PLL 606 can be set to different frequency multiplication ratios.
  • a system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources.
  • the high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources.
  • the system allows for the adapter to use the same pins for multiple data sources.

Abstract

A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.

Description

CONFIGURABLE PORTS FOR A HOST ETHERNET ADAPTER
FIELD OF THE INVENTION
The present invention relates generally to a server environment and more specifically to adapters utilized in such an environment.
CROSS-REFERENCE TO RELATED APPLICATIONS
The present application is related to the following copending U.S. patent applications:
US. patent application, serial no. (Attorney Docket No.
RPS920050059US1/3485P), entitled "Host Ethernet Adapter for Networking Offload in Server Environment", filed on even date herewith and assigned to the assignee of the present invention.
U.S. patent application, serial no. (Attorney Docket No.
RPS920050060US1/3486P), entitled "Method and System for Accommodating Several Ethernet Ports and a Wrap Transmitted Flow Handled by a Simplified Frame-By-Frame Upper Structure", filed on even date herewith and assigned to the assignee of the present invention.
U.S. patent application, serial no. (Attorney Docket No.
RPS920050061 US1/3487P), entitled "Method and Apparatus for Providing a Network Connection Table", filed on even date herewith and assigned to the assignee of the present invention. U.S. patent application, serial no. (Attorney Docket No.
RPS920050062US1/3488P), entitled "Network Communications for Operating System Partitions", filed on even date herewith and assigned to the assignee of the present invention. U.S. patent application, serial no. (Attorney Docket No.
RPS920050074US1/3503P), entitled "System and Method for Parsing, Filtering, and Computing the Checksum in a Host Ethernet Adapter (HEA)", filed on even date herewith and assigned to the assignee of the present invention.
U.S. patent application, serial no. (Attorney Docket No. RPS920050075US1/3504P), entitled "System and Method for a Method for
Reducing Latency in a Host Ethernet Adapter (HEA)", filed on even date herewith and assigned to the assignee of the present invention.
U.S. patent application, serial no. (Attorney Docket No.
RPS920050076US1/3505P), entitled "Method and Apparatus for Blind Checksum and Correction for Network Transmissions", filed on even date herewith and assigned to the assignee of the present invention.
U.S. patent application, serial no. (Attorney Docket No.
RPS920050082US1/3512P), entitled "Method and System for Performing a Packet Header Lookup", filed on even date herewith and assigned to the assignee of the present invention.
U.S. patent application, serial no. (Attorney Docket No.
RPS920050089US1/3516P), entitled "System and Method for Computing a Blind Checksum in a Host Ethernet Adapter (HEA)", filed on even date herewith and assigned to the assignee of the present invention.
BACKGROUND OF THE INVENTION
The Internet and its applications have tremendously increased the number of clients' requests a server has to satisfy. Each client's request generates both network and storage I/Os. In addition, the advent of 10 gigabit (G) Ethernet and IP storage makes it possible to consolidate the data center communications on a single backbone infrastructure: Ethernet, TCP/IP. Adapters are utilized in Network Interface Controllers (NICs) to receive data from 10 G sources. In such an adapter it is also desirable to handle data from other sources. For example there are still a significant number of 1 G sources. However it is a problem to support 1 G ports through the same interface as the 10 G port. The problem is that the 10 G port is a serial interface while the 1 G port is typically a parallel interface. Typically to accommodate both types of data sources would require additional pins on the NIC. These additional pins would necessarily increase the cost and complexity of the device.
Accordingly, what is desired is an adapter which can be utilized in a server environment which can accommodate multiple data sources but does not have any of the above-identified problems. The adapter should be easily implemented utilizing existing technologies. The adapter should also be cost effective and easily adapted to existing server environments.
The present invention addresses such a need.
SUMMARY OF THE INVENTION
An Ethernet adapter is disclosed. The adapter comprises a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor. The plurality of layers include a high speed serializer/deserializer (high speed serdes) to receive data from and provide data to different speed data sources on the same pins.
A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources. BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a block diagram of a server system in accordance with the present invention. Figure 2 is a simple block diagram of the a Host Ethernet Adapter (HEA) in accordance with the present invention.
Figure 3 is a block diagram of the HEA with a more detailed view of the MAC and Serdes Layer.
Figure 4 is a more detailed diagram of the high speed serdes.
DETAILED DESCRIPTION
The present invention relates generally to a server environment and more specifically to adapters utilized in such an environment. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirements. Various modifications to the preferred embodiments and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein. A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. To more particularly describe the features of the present invention refer now to the accompanying drawings in conjunction with the accompanying Figures. Figure 1 is a block diagram of a server system 100 in accordance with the present invention. The server system 100 includes a processor 102 which is coupled between a memory 104 and an interface adapter chip 106. The interface adapter chip 106 includes an interface 108 to the private (Gx) bus of the processor 102 and a Host Ethernet Adapter (HEA) 110. The HEA 110 receives and transmits signals from and to the processor 102.
The HEA 110 is an integrated Ethernet adapter. A set of accelerator features are provided such that a server TCP/IP stack uses those features when and as required. The interface between the processor 102 and the interface adapter chip 106 has been streamlined by bypassing the PCI bus and providing interface techniques that enable demultiplexing and multiqueueing and packet header separation. In so doing an Ethernet adapter is provided that allows for improved functionality with high speed system while allowing for compatibility with legacy server environments.
Figure 2 is a simple block diagram of the HEA 110 in accordance with the present invention. As is seen, the HEA 110 has a three layer architecture. The first layer comprises a Media Access Controller (MAC) and Serialization/Deserialization (Serdes) layer 202 which provides a plurality of interfaces from and to other devices on the Ethernet network. In the layer 202 the same chip I/Os are used to provide a plurality of interfaces. For example, in a preferred embodiment, the same chip I/Os are utilized to provide either a 10 Gigabit interface or multiple 1 Gigabit interfaces.
The second layer comprises a Packet Acceleration and Virtualization Layer 204. The layer 204 provides for receiving packets and demultiplexing the flow of packets for enabling virtualization. The layer 204 enables virtualization or partitioning of the operating system of a server based upon the packets. The layer 204 also provides packet header separation to enable zero copy operations and therefore provide improved latency. Also since layer 204 interacts directly with the private bus (Gx) through the Host Interface Layer 206, a low latency, high bandwidth connection is provided.
The third layer comprises the Host Interface Layer 206. The Host Interface Layer 206 provides the interface to the Gx or private bus of the processor and communicates with layer 204. The layer 206 provides for multiple receive sub-queues per Queue Pair (QP) to enable effective buffer management for a TCP stack. The host layer 206 provides the context management for a given flow of data packets. To describe the features of the HEA 100 in more detail refer now to the following discussion in conjunction with the accompanying figures.
MAC and Serdes Layer 202
Figure 3 is a block diagram of the HEA 110 with a more detailed view of the MAC and Serdes Layer 202. As is seen in this embodiment there is one 10 Gigabit MAC 302 and two 1 Gigabit MACs 304a and 304b. The MACs 302, 304a and 304b include physical coding units 308a, 308b and 308c for aligning and coding the received packets. The MACs 302, 304a and 304b are coupled to a High Speed Serializer/Deserialization (high speed serdes) 306. The high speed serdes 306 is capable of receiving data from and providing data to one 10 G source or four 1 G. As before mentioned the high speed serdes 306 includes a mechanism for ensuring that data from and to the data sources are handled appropriately. To describe this feature more detail refer now to the following discussion in conjunction with the accompanying Figures. Figure 4 is a more detailed diagram of the high speed serdes 306. As is seen in this embodiment the high speed serdes 306 includes a receive section 602 and a transmit section 604. There are four lanes associated with the high speed serdes 306. Each lane corresponds to one up bottom arrow and one down bottom arrow on the receive section 602 and the transmit section 604 respectively. In this embodiment a 10 G source requires four lanes and a 1 G source requires one lane. The high speed serdes 306 also includes a Phase Locked Loop (PLL) 606 which receives a reference clock signal from the NIC (not shown). The reference clock is relatively low compared to the data sources because the PLL 606 can be set to different frequency multiplication ratios to allow the different data sources. The high speed serdes 306 also can configured to allow for multiple modes of operation. In so doing, the different data sources can be accommodated since the PLL 606 has different multiplication ratios.
Below is an example of the operation of the high speed serdes 306 using a 312.5MHz reference clock 10G data source: Full rate mode at 3.125 Gbps
1G data source: Half-rate mode at 1.25 Gbps The same high speed serdes Ref Clock can be used in both modes, because internal high speed serdes PLL 606 can be set to different frequency multiplication ratios.
312.5 MHz Ref Clock x 10 = 3.125 GHz 312.5 MHz Ref Clock x 8 = 2.5 GHz (high speed serdes half-rate mode then leads to 1.25 Gbps)
A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.
Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.

Claims

CLAIMSWhat is claimed is:
1. An Ethernet adapter comprising: a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor; wherein the plurality of layers include a high speed serializer/deserializer (high speed serdes) for receiving data from and providing data to different speed data sources on the same pins.
2. The Ethernet adapter of claim 1 wherein the different speed data sources comprise a 10 Gigabit (G) source and a plurality of 1 G sources.
3. The Ethernet adapter of claim 1 wherein the high speed serdes comprises a receive section for receiving data from a data source; a transmit section for transmitting data to a data source; and a phase locked loop (PLL) for controlling the data rate of the transmit and receive sections.
4. The Ethernet adapter of claim 3 wherein the receive section and transmit share a plurality of lanes.
The Ethernet adapter of claim 3 wherein the high speed serdes can be configured in different modes of operation.
6. The Ethernet adapter of claim 5 wherein the different modes of operation comprise full rate mode and half rate mode.
7. The Ethernet adapter of claim 3 wherein the PLL controls the data rate by setting different multiplication ratios.
8. A network interface controller (NIC) comprising: an interface to a private bus; and an Ethernet adapter coupled to the interface; the ethemet adapter comprising a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor; wherein the plurality of layers include a high speed serializer/deserializer (high speed serdes) for receiving data from and providing data to different speed data sources on the same pins.
9. The NIC of claim 8 wherein the different speed data sources comprise a 10 Gigabit (G) source and a plurality of 1 G sources.
10. The NIC of claim 8 wherein the high speed serdes comprises: a receive section for receiving data from a data source; a transmit section for transmitting data to a data source; and a phase locked loop (PLL) for controlling the data rate of the transmit and receive sections.
11. The NIC of claim 8 wherein the receive section and transmit share a plurality of lanes.
12. The NIC of claim 8 wherein the high speed serdes can be configured in different modes of operation.
13. The NIC of claim 8 wherein the different modes of operation comprise full rate mode and half rate mode.
14. The NIC of claim 8 wherein the PLL controls the data rate by setting different multiplication ratios.
15. A network interface controller (NIC) comprising: an interface coupled to a private bus; and an Ethernet adapter coupled to the interface, a plurality of layers for allowing the adapter to receive and transmit packets from and to a processor via the private bus, wherein the plurality of layers include a high speed serializer/deserializer (high speed serdes) for receiving data from and providing data to a 10 Gigabit (G) source and a plurality of 1 G sources on the same pins, wherein the high speed serdes can be configured in a full rate and a half rate mode of operation.
16. The NIC of claim 15 wherein the high speed serdes comprises a receive section for receiving data from a data source; a transmit section for transmitting data to a data source; and a phase locked loop (PLL) for controlling the data rate of the transmit and receive sections.
17. The NIC of claim 16 wherein the receive section and transmit share a plurality of lanes.
18. The NIC of claim 16 wherein the PLL controls the data rate by setting different multiplication ratios.
19. A server comprising: a processor; the processor including a private bus; and a network interface controller (NIC) coupled to the private bus, the NIC including an Ethernet adapter; the Ethernet adapter comprising a plurality of layers for allowing the adapter to receive and transmit packets from and to the processor; wherein the plurality of layers include a high speed serializer/deserializer (high speed serdes) to receive data from and provide data to different speed data sources on the same pins.
PCT/EP2006/060732 2005-04-01 2006-03-15 Configurable ports for a host ethernet adapter WO2006103167A1 (en)

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US11/097,652 2005-04-01
US11/097,652 US7881332B2 (en) 2005-04-01 2005-04-01 Configurable ports for a host ethernet adapter

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US7782888B2 (en) 2010-08-24
US7881332B2 (en) 2011-02-01

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