WO2006105514A3 - Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides - Google Patents

Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides Download PDF

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Publication number
WO2006105514A3
WO2006105514A3 PCT/US2006/012394 US2006012394W WO2006105514A3 WO 2006105514 A3 WO2006105514 A3 WO 2006105514A3 US 2006012394 W US2006012394 W US 2006012394W WO 2006105514 A3 WO2006105514 A3 WO 2006105514A3
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WO
WIPO (PCT)
Prior art keywords
package
assembly
lower sides
package assembly
substrate surfaces
Prior art date
Application number
PCT/US2006/012394
Other languages
French (fr)
Other versions
WO2006105514A2 (en
Inventor
Marcos Karnezos
Il Kwon Shim
Byung Joon Han
Kambhampati Ramakrishna
Seng Guan Chow
Original Assignee
Stats Chippac Ltd
Marcos Karnezos
Il Kwon Shim
Byung Joon Han
Kambhampati Ramakrishna
Seng Guan Chow
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/306,628 external-priority patent/US7364945B2/en
Application filed by Stats Chippac Ltd, Marcos Karnezos, Il Kwon Shim, Byung Joon Han, Kambhampati Ramakrishna, Seng Guan Chow filed Critical Stats Chippac Ltd
Priority to KR1020077025326A priority Critical patent/KR101172527B1/en
Priority to JP2008504521A priority patent/JP2008535273A/en
Publication of WO2006105514A2 publication Critical patent/WO2006105514A2/en
Publication of WO2006105514A3 publication Critical patent/WO2006105514A3/en

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    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]
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    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19106Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
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    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires
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    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding

Abstract

Stacked package assemblies include first and second stacked packages, each having at least one die affixed to, and electrically interconnected with, a die attach side of the package substrate. One package is inverted in relation to the other; that is, the die attach sides of the package substrates face one another, and the 'land' sides of the substrates face away from one another. Z-lnterconnectio of the packages is by wire bonds connecting the first and second package substrates. The assembly is encapsulated in such a way th both the second package substrate (one side of the assembly) and a portion of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made. In some embodiments the first package is a chip scale package, and the second package is a land grid array package.
PCT/US2006/012394 2005-03-31 2006-03-31 Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides WO2006105514A2 (en)

Priority Applications (2)

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KR1020077025326A KR101172527B1 (en) 2005-03-31 2006-03-31 Semiconductor stacked package assembly having exposed substrate surfaces on upper and lower sides
JP2008504521A JP2008535273A (en) 2005-03-31 2006-03-31 Semiconductor stacked package assembly having substrate surfaces exposed on top and bottom surfaces

Applications Claiming Priority (6)

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US66727705P 2005-03-31 2005-03-31
US60/667,277 2005-03-31
US69218205P 2005-06-20 2005-06-20
US60/692,182 2005-06-20
US11/306,628 US7364945B2 (en) 2005-03-31 2006-01-04 Method of mounting an integrated circuit package in an encapsulant cavity
US11/306,628 2006-01-04

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WO2006105514A3 true WO2006105514A3 (en) 2007-09-20

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KR (1) KR101172527B1 (en)
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