WO2007030258A3 - Post deposition plasma treatment to increase tensile stress of a hdp-cvd si 02 layer - Google Patents

Post deposition plasma treatment to increase tensile stress of a hdp-cvd si 02 layer Download PDF

Info

Publication number
WO2007030258A3
WO2007030258A3 PCT/US2006/031191 US2006031191W WO2007030258A3 WO 2007030258 A3 WO2007030258 A3 WO 2007030258A3 US 2006031191 W US2006031191 W US 2006031191W WO 2007030258 A3 WO2007030258 A3 WO 2007030258A3
Authority
WO
WIPO (PCT)
Prior art keywords
plasma treatment
substrate
tensile stress
plasma
layer
Prior art date
Application number
PCT/US2006/031191
Other languages
French (fr)
Other versions
WO2007030258A2 (en
Inventor
Xiaolin Chen
Srinivas D Nemani
Dongqing Li
Jeffrey C Munro
Marlon E Menezes
Original Assignee
Applied Materials Inc
Xiaolin Chen
Srinivas D Nemani
Dongqing Li
Jeffrey C Munro
Marlon E Menezes
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc, Xiaolin Chen, Srinivas D Nemani, Dongqing Li, Jeffrey C Munro, Marlon E Menezes filed Critical Applied Materials Inc
Publication of WO2007030258A2 publication Critical patent/WO2007030258A2/en
Publication of WO2007030258A3 publication Critical patent/WO2007030258A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • C23C16/402—Silicon dioxide
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/56—After-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H01L21/31612—Deposition of SiO2 on a silicon body

Abstract

A plasma treatment process for increasing the tensile stress of a silicon wafer is described. Following deposition of a dielectric layer on a substrate, the substrate is lifted to an elevated position above the substrate receiving surface and exposed to a plasma treatment process which treats both the top and bottom surface of the wafer and increases the tensile stress of the deposited layer. Another embodiment of the invention involves biasing of the substrate prior to plasma treatment to bombard the wafer with plasma ions and raise the temperature of the substrate. In another embodiment of the invention, a two-step plasma treatment process can be used where the substrate is first exposed to a plasma at a processing position directly after deposition, and then raised to an elevated position where both the top and bottom of the wafer are exposed to the plasma.
PCT/US2006/031191 2005-09-07 2006-08-10 Post deposition plasma treatment to increase tensile stress of a hdp-cvd si 02 layer WO2007030258A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/221,303 2005-09-07
US11/221,303 US7465680B2 (en) 2005-09-07 2005-09-07 Post deposition plasma treatment to increase tensile stress of HDP-CVD SIO2

Publications (2)

Publication Number Publication Date
WO2007030258A2 WO2007030258A2 (en) 2007-03-15
WO2007030258A3 true WO2007030258A3 (en) 2007-05-10

Family

ID=37801400

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/031191 WO2007030258A2 (en) 2005-09-07 2006-08-10 Post deposition plasma treatment to increase tensile stress of a hdp-cvd si 02 layer

Country Status (3)

Country Link
US (2) US7465680B2 (en)
TW (1) TWI355031B (en)
WO (1) WO2007030258A2 (en)

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7390755B1 (en) 2002-03-26 2008-06-24 Novellus Systems, Inc. Methods for post etch cleans
US7253125B1 (en) 2004-04-16 2007-08-07 Novellus Systems, Inc. Method to improve mechanical strength of low-k dielectric film using modulated UV exposure
US7288484B1 (en) 2004-07-13 2007-10-30 Novellus Systems, Inc. Photoresist strip method for low-k dielectrics
US9659769B1 (en) 2004-10-22 2017-05-23 Novellus Systems, Inc. Tensile dielectric films using UV curing
US7790633B1 (en) 2004-10-26 2010-09-07 Novellus Systems, Inc. Sequential deposition/anneal film densification method
US8193096B2 (en) 2004-12-13 2012-06-05 Novellus Systems, Inc. High dose implantation strip (HDIS) in H2 base chemistry
US7510982B1 (en) 2005-01-31 2009-03-31 Novellus Systems, Inc. Creation of porosity in low-k films by photo-disassociation of imbedded nanoparticles
US8454750B1 (en) 2005-04-26 2013-06-04 Novellus Systems, Inc. Multi-station sequential curing of dielectric films
US8889233B1 (en) 2005-04-26 2014-11-18 Novellus Systems, Inc. Method for reducing stress in porous dielectric films
US8980769B1 (en) 2005-04-26 2015-03-17 Novellus Systems, Inc. Multi-station sequential curing of dielectric films
US8282768B1 (en) 2005-04-26 2012-10-09 Novellus Systems, Inc. Purging of porogen from UV cure chamber
US8137465B1 (en) 2005-04-26 2012-03-20 Novellus Systems, Inc. Single-chamber sequential curing of semiconductor wafers
US8129281B1 (en) 2005-05-12 2012-03-06 Novellus Systems, Inc. Plasma based photoresist removal system for cleaning post ash residue
JP4984558B2 (en) * 2006-02-08 2012-07-25 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
US20070202710A1 (en) * 2006-02-27 2007-08-30 Hynix Semiconductor Inc. Method for fabricating semiconductor device using hard mask
US7482245B1 (en) * 2006-06-20 2009-01-27 Novellus Systems, Inc. Stress profile modulation in STI gap fill
US7740768B1 (en) * 2006-10-12 2010-06-22 Novellus Systems, Inc. Simultaneous front side ash and backside clean
US8465991B2 (en) 2006-10-30 2013-06-18 Novellus Systems, Inc. Carbon containing low-k dielectric constant recovery using UV treatment
US7851232B2 (en) 2006-10-30 2010-12-14 Novellus Systems, Inc. UV treatment for carbon-containing low-k dielectric repair in semiconductor processing
US10037905B2 (en) 2009-11-12 2018-07-31 Novellus Systems, Inc. UV and reducing treatment for K recovery and surface clean in semiconductor processing
US20080128675A1 (en) * 2006-11-30 2008-06-05 Michele Magistretti Phase change memory cell having a tapered microtrench
US7906174B1 (en) 2006-12-07 2011-03-15 Novellus Systems, Inc. PECVD methods for producing ultra low-k dielectric films using UV treatment
US8242028B1 (en) 2007-04-03 2012-08-14 Novellus Systems, Inc. UV treatment of etch stop and hard mask films for selectivity and hermeticity enhancement
US8435895B2 (en) 2007-04-04 2013-05-07 Novellus Systems, Inc. Methods for stripping photoresist and/or cleaning metal regions
US7622162B1 (en) * 2007-06-07 2009-11-24 Novellus Systems, Inc. UV treatment of STI films for increasing tensile stress
US8211510B1 (en) 2007-08-31 2012-07-03 Novellus Systems, Inc. Cascaded cure approach to fabricate highly tensile silicon nitride films
KR101002548B1 (en) * 2007-10-10 2010-12-17 주식회사 하이닉스반도체 Method of forming isolation layer in semiconductor device
US7618874B1 (en) * 2008-05-02 2009-11-17 Micron Technology, Inc. Methods of forming capacitors
US7696056B2 (en) 2008-05-02 2010-04-13 Micron Technology, Inc. Methods of forming capacitors
US8133797B2 (en) * 2008-05-16 2012-03-13 Novellus Systems, Inc. Protective layer to enable damage free gap fill
US9050623B1 (en) 2008-09-12 2015-06-09 Novellus Systems, Inc. Progressive UV cure
US8591661B2 (en) 2009-12-11 2013-11-26 Novellus Systems, Inc. Low damage photoresist strip method for low-K dielectrics
US20110143548A1 (en) 2009-12-11 2011-06-16 David Cheung Ultra low silicon loss high dose implant strip
KR101770008B1 (en) 2009-12-11 2017-08-21 노벨러스 시스템즈, 인코포레이티드 Enhanced passivation process to protect silicon prior to high dose implant strip
US8741394B2 (en) 2010-03-25 2014-06-03 Novellus Systems, Inc. In-situ deposition of film stacks
KR101223724B1 (en) * 2010-10-25 2013-01-17 삼성디스플레이 주식회사 Passivation film for electronic device and method of manufacturing the same
US8486814B2 (en) * 2011-07-21 2013-07-16 International Business Machines Corporation Wafer backside defectivity clean-up utilizing selective removal of substrate material
US9613825B2 (en) 2011-08-26 2017-04-04 Novellus Systems, Inc. Photoresist strip processes for improved device integrity
WO2013048872A1 (en) * 2011-09-26 2013-04-04 Applied Materials, Inc. Pretreatment and improved dielectric coverage
US9514954B2 (en) 2014-06-10 2016-12-06 Lam Research Corporation Peroxide-vapor treatment for enhancing photoresist-strip performance and modifying organic films
US9076868B1 (en) 2014-07-18 2015-07-07 Globalfoundries Inc. Shallow trench isolation structure with sigma cavity
US9219151B1 (en) * 2014-09-04 2015-12-22 United Microelectronics Corp. Method for manufacturing silicon nitride layer and method for manufacturing semiconductor structure applying the same
US10858727B2 (en) 2016-08-19 2020-12-08 Applied Materials, Inc. High density, low stress amorphous carbon film, and process and equipment for its deposition
US9847221B1 (en) 2016-09-29 2017-12-19 Lam Research Corporation Low temperature formation of high quality silicon oxide films in semiconductor device manufacturing
US10541137B2 (en) 2018-06-01 2020-01-21 Varian Semiconductor Equipment Associates, Inc. Method and apparatus for non line-of-sight doping
US11114306B2 (en) * 2018-09-17 2021-09-07 Applied Materials, Inc. Methods for depositing dielectric material
JP7222946B2 (en) * 2020-03-24 2023-02-15 株式会社Kokusai Electric Semiconductor device manufacturing method, substrate processing apparatus, and program
CN113969396B (en) * 2020-07-22 2023-12-01 盛合晶微半导体(江阴)有限公司 Preparation method of control wafer
US11572622B2 (en) * 2020-09-14 2023-02-07 Applied Materials, Inc. Systems and methods for cleaning low-k deposition chambers
WO2023042804A1 (en) * 2021-09-14 2023-03-23 東京エレクトロン株式会社 Plasma processing device and plasma processing method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56138916A (en) * 1980-03-31 1981-10-29 Fujitsu Ltd Formation of amorphous thin film
JPH06333922A (en) * 1993-05-19 1994-12-02 Nippondenso Co Ltd Device protective film and its manufacture
US6037237A (en) * 1997-07-25 2000-03-14 Samsung Electronics Co., Ltd. Trench isolation methods utilizing composite oxide films
EP1186685A2 (en) * 2000-09-08 2002-03-13 Applied Materials, Inc. Method for forming silicon carbide films
US20040063300A1 (en) * 2002-10-01 2004-04-01 Taiwan Semiconductor Manufacturing Company Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control
US20040248395A1 (en) * 2003-06-05 2004-12-09 Semiconductor Leading Edge Technologies, Inc. Method for manufacturing semiconductor device

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4962049A (en) 1989-04-13 1990-10-09 Applied Materials, Inc. Process for the plasma treatment of the backside of a semiconductor wafer
JP3013446B2 (en) * 1990-12-28 2000-02-28 ソニー株式会社 Dry etching method
US5707485A (en) * 1995-12-20 1998-01-13 Micron Technology, Inc. Method and apparatus for facilitating removal of material from the backside of wafers via a plasma etch
US5681425A (en) * 1995-12-29 1997-10-28 Industrial Technology Research Institute Teos plasma protection technology
US5948704A (en) * 1996-06-05 1999-09-07 Lam Research Corporation High flow vacuum chamber including equipment modules such as a plasma generating source, vacuum pumping arrangement and/or cantilevered substrate support
US5820723A (en) * 1996-06-05 1998-10-13 Lam Research Corporation Universal vacuum chamber including equipment modules such as a plasma generating source, vacuum pumping arrangement and/or cantilevered substrate support
US6287977B1 (en) * 1998-07-31 2001-09-11 Applied Materials, Inc. Method and apparatus for forming improved metal interconnects
US6514870B2 (en) 2001-01-26 2003-02-04 Applied Materials, Inc. In situ wafer heat for reduced backside contamination
US6528427B2 (en) * 2001-03-30 2003-03-04 Lam Research Corporation Methods for reducing contamination of semiconductor substrates
TW582086B (en) * 2001-04-02 2004-04-01 United Microelectronics Corp Surface densification method of low dielectric constant film
JP2002343787A (en) * 2001-05-17 2002-11-29 Research Institute Of Innovative Technology For The Earth Plasma treatment equipment and its cleaning method
JP3821065B2 (en) * 2002-07-04 2006-09-13 東京エレクトロン株式会社 Plasma processing apparatus, upper electrode cover, and upper electrode cover window
KR100481180B1 (en) * 2002-09-10 2005-04-07 삼성전자주식회사 Photoresist removal method
US6974768B1 (en) * 2003-01-15 2005-12-13 Novellus Systems, Inc. Methods of providing an adhesion layer for adhesion of barrier and/or seed layers to dielectric films
US20060105106A1 (en) * 2004-11-16 2006-05-18 Applied Materials, Inc. Tensile and compressive stressed materials for semiconductors
US7455735B2 (en) * 2005-09-28 2008-11-25 Nordson Corporation Width adjustable substrate support for plasma processing

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56138916A (en) * 1980-03-31 1981-10-29 Fujitsu Ltd Formation of amorphous thin film
JPH06333922A (en) * 1993-05-19 1994-12-02 Nippondenso Co Ltd Device protective film and its manufacture
US6037237A (en) * 1997-07-25 2000-03-14 Samsung Electronics Co., Ltd. Trench isolation methods utilizing composite oxide films
EP1186685A2 (en) * 2000-09-08 2002-03-13 Applied Materials, Inc. Method for forming silicon carbide films
US20040063300A1 (en) * 2002-10-01 2004-04-01 Taiwan Semiconductor Manufacturing Company Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control
US20040248395A1 (en) * 2003-06-05 2004-12-09 Semiconductor Leading Edge Technologies, Inc. Method for manufacturing semiconductor device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
RAMKUMAR K ET AL: "STRESS IN SIO2 FILMS DEPOSITED BY PLASMA AND OZONE TETRAETHYLORTHOSILICATE CHEMICAL VAPOR DEPOSITION PROCESSES", JOURNAL OF THE ELECTROCHEMICAL SOCIETY, ELECTROCHEMICAL SOCIETY. MANCHESTER, NEW HAMPSHIRE, US, vol. 139, no. 5, 1 May 1992 (1992-05-01), pages 1437 - 1442, XP000355385, ISSN: 0013-4651 *
THURN JEREMY ET AL: "Stress hysteresis and mechanical properties of plasma-enhanced chemical vapor deposited dielectric films", JOURNAL OF APPLIED PHYSICS, AMERICAN INSTITUTE OF PHYSICS. NEW YORK, US, vol. 95, no. 3, 1 February 2004 (2004-02-01), pages 967 - 976, XP012067366, ISSN: 0021-8979 *

Also Published As

Publication number Publication date
US7465680B2 (en) 2008-12-16
WO2007030258A2 (en) 2007-03-15
US7745351B2 (en) 2010-06-29
TWI355031B (en) 2011-12-21
US20090035918A1 (en) 2009-02-05
TW200715410A (en) 2007-04-16
US20070054504A1 (en) 2007-03-08

Similar Documents

Publication Publication Date Title
WO2007030258A3 (en) Post deposition plasma treatment to increase tensile stress of a hdp-cvd si 02 layer
WO2008064246A3 (en) Method of clustering sequential processing for a gate stack structure
WO2003088318A3 (en) Method of fabricating vertical structure leds
ATE495551T1 (en) PROCESS FOR PRODUCTION OF SOI TRANSISTOR HAVING SELF-ALIGINATED BASE PLATE AND GATE AND HAVING A BURNED OXIDE LAYER OF VARIABLE THICKNESS
US9252240B2 (en) Manufacturing method for semiconductor device with discrete field oxide structure
TW200509183A (en) Semiconductor device and process for fabricating the same
WO2012012138A3 (en) Method for finishing silicon on insulator substrates
WO2008120469A1 (en) Method for manufacturing silicon carbide semiconductor element
WO2009120407A3 (en) Integrated passive device and method with low cost substrate
TW200612493A (en) Forming high-k dielectric layers on smooth substrates
TW200707637A (en) Method of manufacturing a semiconductor device and semiconductor device obtained by means of said method
TW200636822A (en) Structure and method for manufacturing strained silicon directly-on insulator substrate with hybrid crystalling orientation and different stress levels
WO2003001583A3 (en) Process for producing silicon on insulator structure having intrinsic gettering by ion implantation
TW200729289A (en) Non-plasma method of removing photoresist from a substrate
EP2533305A3 (en) Method for blister-free passivation of a silicon surface
WO2008081723A1 (en) Method for forming insulating film and method for manufacturing semiconductor device
TW200640283A (en) Method of manufacturing an organic electronic device
TW200618298A (en) Fabrication method of thin film transistor
TW200725734A (en) Plasma etching method and making method of semiconductor
TW200717664A (en) Semiconductor fabrication process including silicide stringer removal processing
WO2007024714A3 (en) Process for modifying dielectric materials
WO2009078121A1 (en) Semiconductor substrate supporting jig and method for manufacturing the same
WO2002019363A3 (en) Pre-polycoating of glass substrates
TW200504821A (en) Thin film transistor and its manufacturing method
WO2009020023A1 (en) Power adjusting method, method for manufacturing silicon epitaxial wafer, and susceptor

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application
NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 06801137

Country of ref document: EP

Kind code of ref document: A2