WO2007034481A3 - A nand flash memory controller exporting a nand interface - Google Patents

A nand flash memory controller exporting a nand interface Download PDF

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Publication number
WO2007034481A3
WO2007034481A3 PCT/IL2006/001101 IL2006001101W WO2007034481A3 WO 2007034481 A3 WO2007034481 A3 WO 2007034481A3 IL 2006001101 W IL2006001101 W IL 2006001101W WO 2007034481 A3 WO2007034481 A3 WO 2007034481A3
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WO
WIPO (PCT)
Prior art keywords
interface
nand
flash memory
controller
die
Prior art date
Application number
PCT/IL2006/001101
Other languages
French (fr)
Other versions
WO2007034481A2 (en
Inventor
Menachem Lasser
Original Assignee
Msystems Ltd
Menachem Lasser
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=37889248&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO2007034481(A3) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Msystems Ltd, Menachem Lasser filed Critical Msystems Ltd
Priority to JP2008531880A priority Critical patent/JP2009510560A/en
Priority to EP06796108A priority patent/EP1929483A4/en
Priority to CN2006800356310A priority patent/CN101366182B/en
Publication of WO2007034481A2 publication Critical patent/WO2007034481A2/en
Publication of WO2007034481A3 publication Critical patent/WO2007034481A3/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1072Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Abstract

A NAND controller (130) for interfacing between a host device and a flash memory device (e.g. a NAND flash memory device) fabricated on a flash die is disclosed. In some embodiments, the presently disclosed NAND controller includes electronic circuitry fabricated on a controller die, the controller die being distinct from the flash die, a first interface (e.g. a host-type interface, for example a NAND interface) (144, 142) for interfacing between the electronic circuitry and the flash memory device, and a second interface (e.g. a flash-type interface) for interfacing between the controller and the host device, wherein the second interface is a NAND interface. According to some embodiments, the first interface is an inter-die interface. According to some embodiments, the first interface is a NAND interface. Systems including the presently disclosed NAND controller are also disclosed. Methods for assembling the aforementioned systems, and for reading and writing data using NAND controllers are also disclosed.
PCT/IL2006/001101 2005-09-26 2006-09-20 A nand flash memory controller exporting a nand interface WO2007034481A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2008531880A JP2009510560A (en) 2005-09-26 2006-09-20 NAND flash memory controller exporting NAND interface
EP06796108A EP1929483A4 (en) 2005-09-26 2006-09-20 A nand flash memory controller exporting a nand interface
CN2006800356310A CN101366182B (en) 2005-09-26 2006-09-20 A nand flash memory controller exporting a nand interface

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US72009805P 2005-09-26 2005-09-26
US60/720,098 2005-09-26
US11/326,336 2006-01-06
US11/326,336 US7631245B2 (en) 2005-09-26 2006-01-06 NAND flash memory controller exporting a NAND interface

Publications (2)

Publication Number Publication Date
WO2007034481A2 WO2007034481A2 (en) 2007-03-29
WO2007034481A3 true WO2007034481A3 (en) 2007-09-07

Family

ID=37889248

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IL2006/001101 WO2007034481A2 (en) 2005-09-26 2006-09-20 A nand flash memory controller exporting a nand interface

Country Status (6)

Country Link
US (2) US7631245B2 (en)
EP (2) EP2110746A1 (en)
JP (1) JP2009510560A (en)
KR (2) KR20080050433A (en)
CN (1) CN101366182B (en)
WO (1) WO2007034481A2 (en)

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