WO2007056745A3 - Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering - Google Patents

Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering Download PDF

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Publication number
WO2007056745A3
WO2007056745A3 PCT/US2006/060651 US2006060651W WO2007056745A3 WO 2007056745 A3 WO2007056745 A3 WO 2007056745A3 US 2006060651 W US2006060651 W US 2006060651W WO 2007056745 A3 WO2007056745 A3 WO 2007056745A3
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WO
WIPO (PCT)
Prior art keywords
arsenic
silicon wafer
doped silicon
wafer substrates
phosphorus doped
Prior art date
Application number
PCT/US2006/060651
Other languages
French (fr)
Other versions
WO2007056745A2 (en
Inventor
Robert J Falster
Vladimir Voronkov
Gabriella Borionetti
Original Assignee
Memc Electronic Materials
Robert J Falster
Vladimir Voronkov
Gabriella Borionetti
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Memc Electronic Materials, Robert J Falster, Vladimir Voronkov, Gabriella Borionetti filed Critical Memc Electronic Materials
Priority to EP06846251A priority Critical patent/EP1945838A2/en
Priority to JP2008540326A priority patent/JP2009515370A/en
Publication of WO2007056745A2 publication Critical patent/WO2007056745A2/en
Publication of WO2007056745A3 publication Critical patent/WO2007056745A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/02—Heat treatment

Abstract

A process for the preparation of low resistivity arsenic or phosphorous doped (N+/N++) silicon wafers which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, reliably form oxygen precipitates.
PCT/US2006/060651 2005-11-09 2006-11-08 Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering WO2007056745A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP06846251A EP1945838A2 (en) 2005-11-09 2006-11-08 Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
JP2008540326A JP2009515370A (en) 2005-11-09 2006-11-08 Silicon wafer substrate with intrinsic gettering doped with arsenic and phosphorus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/270,790 US7485928B2 (en) 2005-11-09 2005-11-09 Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering
US11/270,790 2005-11-09

Publications (2)

Publication Number Publication Date
WO2007056745A2 WO2007056745A2 (en) 2007-05-18
WO2007056745A3 true WO2007056745A3 (en) 2007-08-02

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/060651 WO2007056745A2 (en) 2005-11-09 2006-11-08 Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering

Country Status (7)

Country Link
US (2) US7485928B2 (en)
EP (1) EP1945838A2 (en)
JP (1) JP2009515370A (en)
KR (1) KR20080084941A (en)
CN (1) CN101351580A (en)
TW (1) TWI397619B (en)
WO (1) WO2007056745A2 (en)

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US8846460B2 (en) 2009-06-30 2014-09-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US9136115B2 (en) 2009-06-30 2015-09-15 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device

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US20090004426A1 (en) * 2007-06-29 2009-01-01 Memc Electronic Materials, Inc. Suppression of Oxygen Precipitation in Heavily Doped Single Crystal Silicon Substrates
JP4395812B2 (en) * 2008-02-27 2010-01-13 住友電気工業株式会社 Nitride semiconductor wafer-processing method
JP5561918B2 (en) * 2008-07-31 2014-07-30 グローバルウェーハズ・ジャパン株式会社 Silicon wafer manufacturing method
JP5420548B2 (en) * 2008-08-18 2014-02-19 Ｓｕｍｃｏ Ｔｅｃｈｘｉｖ株式会社 Silicon ingot, silicon wafer and epitaxial wafer manufacturing method, and silicon ingot
JP2010062452A (en) * 2008-09-05 2010-03-18 Sumco Corp Method of manufacturing semiconductor substrate
JP5830215B2 (en) * 2008-10-01 2015-12-09 信越半導体株式会社 Epitaxial wafer and method for manufacturing the same
JP5338559B2 (en) * 2009-08-19 2013-11-13 信越半導体株式会社 Manufacturing method of silicon epitaxial wafer
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US9634098B2 (en) * 2013-06-11 2017-04-25 SunEdison Semiconductor Ltd. (UEN201334164H) Oxygen precipitation in heavily doped silicon wafers sliced from ingots grown by the Czochralski method
US20150118861A1 (en) * 2013-10-28 2015-04-30 Texas Instruments Incorporated Czochralski substrates having reduced oxygen donors
JP6642410B2 (en) * 2016-12-20 2020-02-05 株式会社Sumco Method for producing silicon single crystal
JP7080017B2 (en) * 2017-04-25 2022-06-03 株式会社Sumco n-type silicon single crystal ingots, silicon wafers, and epitaxial silicon wafers
JP6881571B2 (en) * 2017-04-25 2021-06-02 株式会社Sumco Method for manufacturing n-type silicon single crystal

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Publication number Priority date Publication date Assignee Title
US8846460B2 (en) 2009-06-30 2014-09-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US9136115B2 (en) 2009-06-30 2015-09-15 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
US9576795B2 (en) 2009-06-30 2017-02-21 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

Also Published As

Publication number Publication date
US8026145B2 (en) 2011-09-27
US7485928B2 (en) 2009-02-03
TWI397619B (en) 2013-06-01
EP1945838A2 (en) 2008-07-23
KR20080084941A (en) 2008-09-22
US20090130824A1 (en) 2009-05-21
WO2007056745A2 (en) 2007-05-18
JP2009515370A (en) 2009-04-09
TW200736422A (en) 2007-10-01
US20070105279A1 (en) 2007-05-10
CN101351580A (en) 2009-01-21

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