WO2007078830A3 - Repair bits for low voltage cache - Google Patents

Repair bits for low voltage cache Download PDF

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Publication number
WO2007078830A3
WO2007078830A3 PCT/US2006/047717 US2006047717W WO2007078830A3 WO 2007078830 A3 WO2007078830 A3 WO 2007078830A3 US 2006047717 W US2006047717 W US 2006047717W WO 2007078830 A3 WO2007078830 A3 WO 2007078830A3
Authority
WO
WIPO (PCT)
Prior art keywords
cache
repair
bit
bad bit
column
Prior art date
Application number
PCT/US2006/047717
Other languages
French (fr)
Other versions
WO2007078830A2 (en
Inventor
Morgan J Dempsey
Jose A Maiz
Original Assignee
Intel Corp
Morgan J Dempsey
Jose A Maiz
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Morgan J Dempsey, Jose A Maiz filed Critical Intel Corp
Priority to DE112006003381T priority Critical patent/DE112006003381T5/en
Priority to CN200680049881.XA priority patent/CN101379566B/en
Publication of WO2007078830A2 publication Critical patent/WO2007078830A2/en
Publication of WO2007078830A3 publication Critical patent/WO2007078830A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/808—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout using a flexible replacement scheme
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores

Abstract

A method and apparatus for repairing cache memories/arrays is described herein. A cache includes a plurality of lines and logically viewable in columns. A repair cache coupled to the cache includes a repair bit mapped to each logically viewable column. A repair module determines a bad bit to be repaired within a column based on any individual or combination of factors, such as the number of errors per line of the cache, the number of errors correctable per line of the cache due to error correction code (ECC), the failure rate of bits, or other considerations. The bad bit is transparently repaired by the repair bit mapped to the column including the bad bit, upon an access to a cache line including the bad bit.
PCT/US2006/047717 2005-12-30 2006-12-14 Repair bits for low voltage cache WO2007078830A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE112006003381T DE112006003381T5 (en) 2005-12-30 2006-12-14 Repair BITS for low voltage cache
CN200680049881.XA CN101379566B (en) 2005-12-30 2006-12-14 Device, system and method for repair bits for low voltage cache

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/322,988 2005-12-30
US11/322,988 US7647536B2 (en) 2005-12-30 2005-12-30 Repair bits for a low voltage cache

Publications (2)

Publication Number Publication Date
WO2007078830A2 WO2007078830A2 (en) 2007-07-12
WO2007078830A3 true WO2007078830A3 (en) 2007-08-30

Family

ID=37969617

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2006/047717 WO2007078830A2 (en) 2005-12-30 2006-12-14 Repair bits for low voltage cache

Country Status (5)

Country Link
US (2) US7647536B2 (en)
CN (1) CN101379566B (en)
DE (1) DE112006003381T5 (en)
TW (1) TWI331340B (en)
WO (1) WO2007078830A2 (en)

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US7287836B2 (en) * 1997-07-15 2007-10-30 Sil;Verbrook Research Pty Ltd Ink jet printhead with circular cross section chamber
US8145960B2 (en) * 2006-07-20 2012-03-27 Arm Limited Storage of data in data stores having some faulty storage locations
US8640005B2 (en) * 2010-05-21 2014-01-28 Intel Corporation Method and apparatus for using cache memory in a system that supports a low power state
US8533572B2 (en) 2010-09-24 2013-09-10 Intel Corporation Error correcting code logic for processor caches that uses a common set of check bits
US8856616B1 (en) * 2011-07-29 2014-10-07 Proton Digital Systems, Inc. Two dimensional encoding for non-volatile memory blocks
TWI594254B (en) * 2012-07-17 2017-08-01 慧榮科技股份有限公司 Method for reading data from block of flash memory and associated memory device
KR102024033B1 (en) 2013-03-04 2019-09-24 삼성전자주식회사 Method and apparatus for controlling memory in mobile communication system
US9262263B2 (en) * 2013-11-25 2016-02-16 Qualcomm Incorporated Bit recovery system
US9959939B2 (en) * 2014-12-23 2018-05-01 Intel Corporation Granular cache repair
CN107329906B (en) * 2017-05-10 2018-07-03 北京邮电大学 A kind of multiple dimensioned failure bitmap buffer structure of high bandwidth
US11151006B2 (en) 2018-07-02 2021-10-19 Samsung Electronics Co., Ltd. HBM RAS cache architecture
US11360704B2 (en) * 2018-12-21 2022-06-14 Micron Technology, Inc. Multiplexed signal development in a memory device
US11257543B2 (en) 2019-06-25 2022-02-22 Stmicroelectronics International N.V. Memory management device, system and method
US11360667B2 (en) 2019-09-09 2022-06-14 Stmicroelectronics S.R.L. Tagged memory operated at lower vmin in error tolerant system

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US6006311A (en) * 1997-04-14 1999-12-21 Internatinal Business Machines Corporation Dynamic updating of repair mask used for cache defect avoidance
US6671822B1 (en) * 2000-08-31 2003-12-30 Hewlett-Packard Development Company, L.P. Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache
WO2006039406A1 (en) * 2004-09-30 2006-04-13 Texas Instruments Incorporated Set associative repair cache systems and methods

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US6055204A (en) 1997-04-29 2000-04-25 Texas Instruments Incorporated Circuits, systems, and methods for re-mapping memory column redundancy
US6772383B1 (en) * 1999-05-27 2004-08-03 Intel Corporation Combined tag and data ECC for enhanced soft error recovery from cache tag errors
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Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6006311A (en) * 1997-04-14 1999-12-21 Internatinal Business Machines Corporation Dynamic updating of repair mask used for cache defect avoidance
US6671822B1 (en) * 2000-08-31 2003-12-30 Hewlett-Packard Development Company, L.P. Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache
WO2006039406A1 (en) * 2004-09-30 2006-04-13 Texas Instruments Incorporated Set associative repair cache systems and methods

Non-Patent Citations (3)

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Title
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Also Published As

Publication number Publication date
TWI331340B (en) 2010-10-01
US8132061B2 (en) 2012-03-06
TW200741728A (en) 2007-11-01
CN101379566B (en) 2014-06-25
US20100070809A1 (en) 2010-03-18
WO2007078830A2 (en) 2007-07-12
US7647536B2 (en) 2010-01-12
US20070168836A1 (en) 2007-07-19
DE112006003381T5 (en) 2008-10-30
CN101379566A (en) 2009-03-04

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