WO2007095080A3 - Memory circuit system and method - Google Patents

Memory circuit system and method Download PDF

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Publication number
WO2007095080A3
WO2007095080A3 PCT/US2007/003460 US2007003460W WO2007095080A3 WO 2007095080 A3 WO2007095080 A3 WO 2007095080A3 US 2007003460 W US2007003460 W US 2007003460W WO 2007095080 A3 WO2007095080 A3 WO 2007095080A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
circuits
interface circuit
host system
circuit
Prior art date
Application number
PCT/US2007/003460
Other languages
French (fr)
Other versions
WO2007095080A2 (en
WO2007095080A8 (en
Inventor
Suresh Natarajan Rajan
Michael John Sebastian Smith
Keith R Schakel
David T Wang
Frederick Daniel Weber
Original Assignee
Suresh Natarajan Rajan
Michael John Sebastian Smith
Keith R Schakel
David T Wang
Frederick Daniel Weber
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/461,437 external-priority patent/US8077535B2/en
Application filed by Suresh Natarajan Rajan, Michael John Sebastian Smith, Keith R Schakel, David T Wang, Frederick Daniel Weber filed Critical Suresh Natarajan Rajan
Priority to KR1020137029741A priority Critical patent/KR101429869B1/en
Priority to DK07750307.6T priority patent/DK2005303T3/en
Priority to KR1020147007335A priority patent/KR101404926B1/en
Priority to EP07750307A priority patent/EP2005303B1/en
Priority to AT07750307T priority patent/ATE554447T1/en
Priority to JP2008554369A priority patent/JP5205280B2/en
Publication of WO2007095080A2 publication Critical patent/WO2007095080A2/en
Publication of WO2007095080A3 publication Critical patent/WO2007095080A3/en
Publication of WO2007095080A8 publication Critical patent/WO2007095080A8/en
Priority to KR1020087019582A priority patent/KR101343252B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

Abstract

A memory circuit system and method are provided. In one embodiment, an interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits. In another embodiment, an interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits. In yet another embodiment, at least one memory stack comprises a plurality of DRAM integrated circuits. Further, a buffer circuit, coupled to a host system, is utilized for interfacing the memory stack to the host system for transforming one or more physical parameters between the DRAM integrated circuits and the host system. In still yet another embodiment, at least one memory stack comprises a plurality of DRAM integrated circuits. Further, an interface circuit, coupled to a host system, is utilized for interfacing the memory stack to the host system so to operate the memory stack as a single DRAM integrated circuit.
PCT/US2007/003460 2006-02-09 2007-02-08 Memory circuit system and method WO2007095080A2 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
KR1020137029741A KR101429869B1 (en) 2006-02-09 2007-02-08 Memory circuit system and method
DK07750307.6T DK2005303T3 (en) 2006-02-09 2007-02-08 Memory circuit system as well - method
KR1020147007335A KR101404926B1 (en) 2006-02-09 2007-02-08 Memory circuit system and method
EP07750307A EP2005303B1 (en) 2006-02-09 2007-02-08 Memory circuit system and method
AT07750307T ATE554447T1 (en) 2006-02-09 2007-02-08 MEMORY CIRCUIT SYSTEM AND METHOD
JP2008554369A JP5205280B2 (en) 2006-02-09 2007-02-08 Memory circuit system and method
KR1020087019582A KR101343252B1 (en) 2006-02-09 2008-08-08 memory circuit system and method

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
USNOTFURNISHED 2002-12-27
US77241406P 2006-02-09 2006-02-09
US60/772,414 2006-02-09
US11/461,437 2006-07-31
US11/461,437 US8077535B2 (en) 2006-07-31 2006-07-31 Memory refresh apparatus and method
US86562406P 2006-11-13 2006-11-13
US60/865,624 2006-11-13

Publications (3)

Publication Number Publication Date
WO2007095080A2 WO2007095080A2 (en) 2007-08-23
WO2007095080A3 true WO2007095080A3 (en) 2008-04-10
WO2007095080A8 WO2007095080A8 (en) 2008-05-22

Family

ID=38372014

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/003460 WO2007095080A2 (en) 2006-02-09 2007-02-08 Memory circuit system and method

Country Status (1)

Country Link
WO (1) WO2007095080A2 (en)

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US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US20080082763A1 (en) 2006-10-02 2008-04-03 Metaram, Inc. Apparatus and method for power management of memory circuits by a system or component thereof
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US7609567B2 (en) 2005-06-24 2009-10-27 Metaram, Inc. System and method for simulating an aspect of a memory circuit
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
KR20100098622A (en) * 2007-11-19 2010-09-08 램버스 인코포레이티드 Scheduling based on turnaround event
US8521979B2 (en) 2008-05-29 2013-08-27 Micron Technology, Inc. Memory systems and methods for controlling the timing of receiving read data
JP5292935B2 (en) * 2008-06-16 2013-09-18 日本電気株式会社 Memory module control method, memory module, and data transfer device
US7855931B2 (en) * 2008-07-21 2010-12-21 Micron Technology, Inc. Memory system and method using stacked memory device dice, and system using the memory system
US7978721B2 (en) * 2008-07-02 2011-07-12 Micron Technology Inc. Multi-serial interface stacked-die memory architecture
US8289760B2 (en) 2008-07-02 2012-10-16 Micron Technology, Inc. Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes
US8756486B2 (en) 2008-07-02 2014-06-17 Micron Technology, Inc. Method and apparatus for repairing high capacity/high bandwidth memory devices
CN102177550B (en) 2008-08-08 2014-03-12 惠普开发有限公司 Independently controlled virtual memory devices in memory modules
KR101477849B1 (en) * 2008-08-08 2014-12-30 휴렛-팩커드 디벨롭먼트 컴퍼니, 엘.피. Independently controllable and reconfigurable virtual memory devices in memory modules that are pin-compatible with standard memory modules
US8812886B2 (en) 2008-08-13 2014-08-19 Hewlett-Packard Development Company, L.P. Dynamic utilization of power-down modes in multi-core memory modules
US8032804B2 (en) * 2009-01-12 2011-10-04 Micron Technology, Inc. Systems and methods for monitoring a memory system
US8572320B1 (en) 2009-01-23 2013-10-29 Cypress Semiconductor Corporation Memory devices and systems including cache devices for memory modules
US8725983B2 (en) 2009-01-23 2014-05-13 Cypress Semiconductor Corporation Memory devices and systems including multi-speed access of memory modules
US8683164B2 (en) * 2009-02-04 2014-03-25 Micron Technology, Inc. Stacked-die memory systems and methods for training stacked-die memory systems
US8364901B2 (en) * 2009-02-13 2013-01-29 Micron Technology, Inc. Memory prefetch systems and methods
US9123552B2 (en) 2010-03-30 2015-09-01 Micron Technology, Inc. Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks, interleaved conductive paths in stacked devices, and methods for forming and operating the same
JP4861497B2 (en) 2010-05-31 2012-01-25 株式会社東芝 Data storage device and memory adjustment method
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JP5541373B2 (en) 2011-01-13 2014-07-09 富士通株式会社 Memory controller and information processing apparatus
GB2488516A (en) * 2011-02-15 2012-09-05 Advanced Risc Mach Ltd Using priority dependent delays to ensure that the average delay between accesses to a memory remains below a threshold
US9679615B2 (en) * 2013-03-15 2017-06-13 Micron Technology, Inc. Flexible memory system with a controller and a stack of memory
US9171597B2 (en) 2013-08-30 2015-10-27 Micron Technology, Inc. Apparatuses and methods for providing strobe signals to memories
US10303235B2 (en) * 2015-03-04 2019-05-28 Qualcomm Incorporated Systems and methods for implementing power collapse in a memory
US10679722B2 (en) 2016-08-26 2020-06-09 Sandisk Technologies Llc Storage system with several integrated components and method for use therewith
US11386004B2 (en) * 2019-02-22 2022-07-12 Micron Technology, Inc. Memory device interface and method

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Title
See also references of EP2005303A4 *

Also Published As

Publication number Publication date
WO2007095080A2 (en) 2007-08-23
WO2007095080A8 (en) 2008-05-22

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