WO2007112162A3 - Selective instruction breakpoint generation - Google Patents

Selective instruction breakpoint generation Download PDF

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Publication number
WO2007112162A3
WO2007112162A3 PCT/US2007/062532 US2007062532W WO2007112162A3 WO 2007112162 A3 WO2007112162 A3 WO 2007112162A3 US 2007062532 W US2007062532 W US 2007062532W WO 2007112162 A3 WO2007112162 A3 WO 2007112162A3
Authority
WO
WIPO (PCT)
Prior art keywords
instruction
address value
breakpoint
source event
instruction source
Prior art date
Application number
PCT/US2007/062532
Other languages
French (fr)
Other versions
WO2007112162A2 (en
Inventor
William C Moyer
Original Assignee
Freescale Semiconductor Inc
William C Moyer
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc, William C Moyer filed Critical Freescale Semiconductor Inc
Publication of WO2007112162A2 publication Critical patent/WO2007112162A2/en
Publication of WO2007112162A3 publication Critical patent/WO2007112162A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software

Abstract

A method includes generating (304) an instruction address value in response to an instruction source event (302). The method further includes selectively generating (314) a breakpoint request based on the instruction source event and responsive to a comparison of the instruction address value to a breakpoint address value. In one embodiment, selectively generating a breakpoint request includes comparing the instruction source event to an instruction source event type, comparing the instruction address value to a breakpoint address value, and generating the breakpoint request responsive to a match between the first instruction source event type and the instruction source event and a match between the instruction address value and the breakpoint address value.
PCT/US2007/062532 2006-03-29 2007-02-22 Selective instruction breakpoint generation WO2007112162A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/392,383 2006-03-29
US11/392,383 US7865704B2 (en) 2006-03-29 2006-03-29 Selective instruction breakpoint generation based on a count of instruction source events

Publications (2)

Publication Number Publication Date
WO2007112162A2 WO2007112162A2 (en) 2007-10-04
WO2007112162A3 true WO2007112162A3 (en) 2008-09-12

Family

ID=38541776

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/062532 WO2007112162A2 (en) 2006-03-29 2007-02-22 Selective instruction breakpoint generation

Country Status (2)

Country Link
US (1) US7865704B2 (en)
WO (1) WO2007112162A2 (en)

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US7958436B2 (en) 2005-12-23 2011-06-07 Intel Corporation Performing a cyclic redundancy checksum operation responsive to a user-level instruction
US8458669B2 (en) * 2007-11-02 2013-06-04 International Business Machines Corporation Automated test system
US8291388B2 (en) * 2008-01-09 2012-10-16 International Business Machines Corporation System, method and program for executing a debugger
US8689196B2 (en) * 2010-12-10 2014-04-01 Microsoft Corporation Display of data from parallel programming contexts
GB2497736A (en) * 2011-12-16 2013-06-26 St Microelectronics Ltd Hardware monitor with context selector for selecting from multiple contexts
KR20150008447A (en) * 2012-05-07 2015-01-22 마이크로칩 테크놀로지 인코포레이티드 Device having configurable breakpoint based on interrupt status
US9053607B2 (en) * 2013-01-30 2015-06-09 Wms Gaming, Inc. Emulator for production software outcome validation
JP6333005B2 (en) * 2014-03-17 2018-05-30 キヤノン株式会社 Image forming apparatus, control method therefor, and program
GB2553311B (en) * 2016-08-31 2020-05-20 Advanced Risc Mach Ltd An apparatus and method for controlling assertion of a trigger signal to processing circuitry
CN107688530B (en) * 2017-04-06 2020-04-10 平安科技（深圳）有限公司 Software testing method and device
US11573802B2 (en) * 2019-10-23 2023-02-07 Texas Instruments Incorporated User mode event handling

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US6751751B1 (en) * 2000-11-06 2004-06-15 Xilinx, Inc. Universal multi-bus breakpoint unit for a configurable system-on-chip

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US6751751B1 (en) * 2000-11-06 2004-06-15 Xilinx, Inc. Universal multi-bus breakpoint unit for a configurable system-on-chip
US20030061599A1 (en) * 2001-09-26 2003-03-27 International Business Machines Corporation Dynamic setting of breakpoint count attributes

Also Published As

Publication number Publication date
WO2007112162A2 (en) 2007-10-04
US7865704B2 (en) 2011-01-04
US20070234017A1 (en) 2007-10-04

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