WO2007125519A3 - Latency optimized resynchronization solution for ddr/ddr2 sdram read path - Google Patents
Latency optimized resynchronization solution for ddr/ddr2 sdram read path Download PDFInfo
- Publication number
- WO2007125519A3 WO2007125519A3 PCT/IB2007/051617 IB2007051617W WO2007125519A3 WO 2007125519 A3 WO2007125519 A3 WO 2007125519A3 IB 2007051617 W IB2007051617 W IB 2007051617W WO 2007125519 A3 WO2007125519 A3 WO 2007125519A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- resynchronization
- ddr
- solution
- read path
- ddr2 sdram
- Prior art date
Links
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
- G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
Abstract
An apparatus for synchronizing memory data signals is provided. The apparatus comprises a first interface circuit (110) that is configured to generate a differential clock signal in a strobe domain and to convey a data signal to a data bus (110), a second interface circuit (120) in a clock domain that is configured to receive the data signal (170) from the data bus and a synchronization circuit that is configured to adjust the data signal (170) between the strobe domain and the clock domain such that integrity of information encoded by the data signal is preserved. Methods of using the apparatus are also disclosed.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US79747206P | 2006-05-03 | 2006-05-03 | |
US60/797,472 | 2006-05-03 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2007125519A2 WO2007125519A2 (en) | 2007-11-08 |
WO2007125519A3 true WO2007125519A3 (en) | 2008-01-10 |
Family
ID=38529487
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB2007/051617 WO2007125519A2 (en) | 2006-05-03 | 2007-05-02 | Latency optimized resynchronization solution for ddr/ddr2 sdram read path |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2007125519A2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8966151B2 (en) * | 2012-03-30 | 2015-02-24 | Spansion Llc | Apparatus and method for a reduced pin count (RPC) memory bus interface including a read data strobe signal |
US9875209B2 (en) * | 2013-05-06 | 2018-01-23 | Qualcomm Incorporated | Synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation/demodulation |
US9515816B2 (en) | 2014-06-30 | 2016-12-06 | International Business Machines Corporation | Latency-optimized physical coding sublayer |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5999458A (en) * | 1997-12-10 | 1999-12-07 | Fujitsu Limited | Latch circuit, data output circuit and semiconductor device having the circuits |
WO2001024184A1 (en) * | 1999-09-30 | 2001-04-05 | Silicon Graphics, Inc. | Configurable synchronizer for double data rate synchronous dynamic random access memory |
US6920526B1 (en) * | 2000-07-20 | 2005-07-19 | Silicon Graphics, Inc. | Dual-bank FIFO for synchronization of read data in DDR SDRAM |
-
2007
- 2007-05-02 WO PCT/IB2007/051617 patent/WO2007125519A2/en active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5999458A (en) * | 1997-12-10 | 1999-12-07 | Fujitsu Limited | Latch circuit, data output circuit and semiconductor device having the circuits |
WO2001024184A1 (en) * | 1999-09-30 | 2001-04-05 | Silicon Graphics, Inc. | Configurable synchronizer for double data rate synchronous dynamic random access memory |
US6920526B1 (en) * | 2000-07-20 | 2005-07-19 | Silicon Graphics, Inc. | Dual-bank FIFO for synchronization of read data in DDR SDRAM |
Also Published As
Publication number | Publication date |
---|---|
WO2007125519A2 (en) | 2007-11-08 |
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