WO2007130976A3 - Non-volatile memory with background data latch caching during program operations and methods therefor - Google Patents

Non-volatile memory with background data latch caching during program operations and methods therefor Download PDF

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Publication number
WO2007130976A3
WO2007130976A3 PCT/US2007/067930 US2007067930W WO2007130976A3 WO 2007130976 A3 WO2007130976 A3 WO 2007130976A3 US 2007067930 W US2007067930 W US 2007067930W WO 2007130976 A3 WO2007130976 A3 WO 2007130976A3
Authority
WO
WIPO (PCT)
Prior art keywords
volatile memory
memory
data latch
background data
during program
Prior art date
Application number
PCT/US2007/067930
Other languages
French (fr)
Other versions
WO2007130976A2 (en
Inventor
Yan Li
Original Assignee
Sandisk Corp
Yan Li
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/382,006 external-priority patent/US7505320B2/en
Application filed by Sandisk Corp, Yan Li filed Critical Sandisk Corp
Publication of WO2007130976A2 publication Critical patent/WO2007130976A2/en
Publication of WO2007130976A3 publication Critical patent/WO2007130976A3/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20—Employing a main memory using a specific memory technology
    • G06F2212/202—Non-volatile memory
    • G06F2212/2022—Flash memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5643—Multilevel memory comprising cache storage devices

Abstract

Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a write operation. In the exemplary embodiment, when the multiple phases of a write operation vary as to the number of states to track, a phase-dependent coding enables efficient utilization of the available data latches, thereby allowing a maximum of surplus latches for background cache operations.
PCT/US2007/067930 2006-05-05 2007-05-01 Non-volatile memory with background data latch caching during program operations and methods therefor WO2007130976A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/382,006 2006-05-05
US11/381,995 2006-05-05
US11/382,006 US7505320B2 (en) 2005-04-01 2006-05-05 Non-volatile memory with background data latch caching during program operations
US11/381,995 US7502260B2 (en) 2005-04-01 2006-05-05 Method for non-volatile memory with background data latch caching during program operations

Publications (2)

Publication Number Publication Date
WO2007130976A2 WO2007130976A2 (en) 2007-11-15
WO2007130976A3 true WO2007130976A3 (en) 2008-04-10

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/067930 WO2007130976A2 (en) 2006-05-05 2007-05-01 Non-volatile memory with background data latch caching during program operations and methods therefor

Country Status (1)

Country Link
WO (1) WO2007130976A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11269555B2 (en) 2020-06-22 2022-03-08 Sandisk Technologies Llc System idle time reduction methods and apparatus

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1209568A1 (en) * 1999-02-22 2002-05-29 Hitachi, Ltd. Memory card, method for allotting logical address, and method for writing data
EP1473737A1 (en) * 2002-02-08 2004-11-03 Matsushita Electric Industrial Co., Ltd. Non-volatile storage device and control method thereof
US6856568B1 (en) * 2000-04-25 2005-02-15 Multi Level Memory Technology Refresh operations that change address mappings in a non-volatile memory
US20060221704A1 (en) * 2005-04-01 2006-10-05 Yan Li Use of data latches in cache operations of non-volatile memories

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1209568A1 (en) * 1999-02-22 2002-05-29 Hitachi, Ltd. Memory card, method for allotting logical address, and method for writing data
US6856568B1 (en) * 2000-04-25 2005-02-15 Multi Level Memory Technology Refresh operations that change address mappings in a non-volatile memory
EP1473737A1 (en) * 2002-02-08 2004-11-03 Matsushita Electric Industrial Co., Ltd. Non-volatile storage device and control method thereof
US20060221704A1 (en) * 2005-04-01 2006-10-05 Yan Li Use of data latches in cache operations of non-volatile memories
US7206230B2 (en) * 2005-04-01 2007-04-17 Sandisk Corporation Use of data latches in cache operations of non-volatile memories

Also Published As

Publication number Publication date
WO2007130976A2 (en) 2007-11-15

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