WO2007131059A3 - Non-volatile memory with background data latch caching during erase operations and methods therefor - Google Patents

Non-volatile memory with background data latch caching during erase operations and methods therefor Download PDF

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Publication number
WO2007131059A3
WO2007131059A3 PCT/US2007/068065 US2007068065W WO2007131059A3 WO 2007131059 A3 WO2007131059 A3 WO 2007131059A3 US 2007068065 W US2007068065 W US 2007068065W WO 2007131059 A3 WO2007131059 A3 WO 2007131059A3
Authority
WO
WIPO (PCT)
Prior art keywords
volatile memory
read
memory
erase operation
data
Prior art date
Application number
PCT/US2007/068065
Other languages
French (fr)
Other versions
WO2007131059A2 (en
Inventor
Jason Lin
Yan Li
Original Assignee
Sandisk Corp
Jason Lin
Yan Li
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/381,998 external-priority patent/US7609552B2/en
Application filed by Sandisk Corp, Jason Lin, Yan Li filed Critical Sandisk Corp
Publication of WO2007131059A2 publication Critical patent/WO2007131059A2/en
Publication of WO2007131059A3 publication Critical patent/WO2007131059A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache

Abstract

Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with an erase operation. In the exemplary embodiment, a read operation is inserted just prior to the erase operation or one or more read operations are inserted during a soft programming phase of the erase operation. In this way, the read data could be output while the erase operation is taking place, thereby making use of otherwise waiting time.
PCT/US2007/068065 2006-05-05 2007-05-02 Non-volatile memory with background data latch caching during erase operations and methods therefor WO2007131059A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US11/381,998 2006-05-05
US11/382,001 2006-05-05
US11/381,998 US7609552B2 (en) 2005-04-01 2006-05-05 Non-volatile memory with background data latch caching during erase operations
US11/382,001 US7619922B2 (en) 2005-04-01 2006-05-05 Method for non-volatile memory with background data latch caching during erase operations

Publications (2)

Publication Number Publication Date
WO2007131059A2 WO2007131059A2 (en) 2007-11-15
WO2007131059A3 true WO2007131059A3 (en) 2008-03-13

Family

ID=38668524

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/068065 WO2007131059A2 (en) 2006-05-05 2007-05-02 Non-volatile memory with background data latch caching during erase operations and methods therefor

Country Status (2)

Country Link
TW (1) TWI367489B (en)
WO (1) WO2007131059A2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1209568A1 (en) * 1999-02-22 2002-05-29 Hitachi, Ltd. Memory card, method for allotting logical address, and method for writing data
EP1473737A1 (en) * 2002-02-08 2004-11-03 Matsushita Electric Industrial Co., Ltd. Non-volatile storage device and control method thereof
US6856568B1 (en) * 2000-04-25 2005-02-15 Multi Level Memory Technology Refresh operations that change address mappings in a non-volatile memory
US20060221704A1 (en) * 2005-04-01 2006-10-05 Yan Li Use of data latches in cache operations of non-volatile memories

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1209568A1 (en) * 1999-02-22 2002-05-29 Hitachi, Ltd. Memory card, method for allotting logical address, and method for writing data
US6856568B1 (en) * 2000-04-25 2005-02-15 Multi Level Memory Technology Refresh operations that change address mappings in a non-volatile memory
EP1473737A1 (en) * 2002-02-08 2004-11-03 Matsushita Electric Industrial Co., Ltd. Non-volatile storage device and control method thereof
US20060221704A1 (en) * 2005-04-01 2006-10-05 Yan Li Use of data latches in cache operations of non-volatile memories
US7206230B2 (en) * 2005-04-01 2007-04-17 Sandisk Corporation Use of data latches in cache operations of non-volatile memories

Also Published As

Publication number Publication date
TW200809863A (en) 2008-02-16
WO2007131059A2 (en) 2007-11-15
TWI367489B (en) 2012-07-01

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