WO2007134301A3 - Iterative memory cell charging based on reference cell value - Google Patents

Iterative memory cell charging based on reference cell value Download PDF

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Publication number
WO2007134301A3
WO2007134301A3 PCT/US2007/068903 US2007068903W WO2007134301A3 WO 2007134301 A3 WO2007134301 A3 WO 2007134301A3 US 2007068903 W US2007068903 W US 2007068903W WO 2007134301 A3 WO2007134301 A3 WO 2007134301A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory cell
voltage level
target voltage
charging based
data value
Prior art date
Application number
PCT/US2007/068903
Other languages
French (fr)
Other versions
WO2007134301A2 (en
Inventor
Michael J Cornwell
Christopher P Dudte
Original Assignee
Apple Inc
Michael J Cornwell
Christopher P Dudte
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Apple Inc, Michael J Cornwell, Christopher P Dudte filed Critical Apple Inc
Publication of WO2007134301A2 publication Critical patent/WO2007134301A2/en
Publication of WO2007134301A3 publication Critical patent/WO2007134301A3/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification

Abstract

Systems and methods, including computer software for writing (700) to a memory device include applying charge (730) to each of multiple memory cells for storage of a selected data value in each memory cell. The memory cells include a first reference memory cell (130a), and each data value is selected from a group of possible data values. Each possible data value has a corresponding target voltage level, and the first reference memory cell has a corresponding predetermined first reference target voltage level. The voltage level in the first reference memory cell is detected (735). A determination is made whether the voltage level in the first reference memory cell is less than the first reference target voltage level (740). Additional charge is applied to the memory cells (730) upon the determination that the voltage level in the first reference memory cell is less than the first reference target voltage.
PCT/US2007/068903 2006-05-15 2007-05-14 Iterative memory cell charging based on reference cell value WO2007134301A2 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US80035706P 2006-05-15 2006-05-15
US60/800,357 2006-05-15
US11/694,742 US7551486B2 (en) 2006-05-15 2007-03-30 Iterative memory cell charging based on reference cell value
US11/694,742 2007-03-30

Publications (2)

Publication Number Publication Date
WO2007134301A2 WO2007134301A2 (en) 2007-11-22
WO2007134301A3 true WO2007134301A3 (en) 2008-03-13

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/068903 WO2007134301A2 (en) 2006-05-15 2007-05-14 Iterative memory cell charging based on reference cell value

Country Status (2)

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US (2) US7551486B2 (en)
WO (1) WO2007134301A2 (en)

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Publication number Publication date
US7551486B2 (en) 2009-06-23
US7859908B2 (en) 2010-12-28
WO2007134301A2 (en) 2007-11-22
US20090237994A1 (en) 2009-09-24
US20070263455A1 (en) 2007-11-15

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