WO2008005087A3 - A nano imprint technique with increased flexibility with respect to alignment and feature shaping - Google Patents
A nano imprint technique with increased flexibility with respect to alignment and feature shaping Download PDFInfo
- Publication number
- WO2008005087A3 WO2008005087A3 PCT/US2007/008371 US2007008371W WO2008005087A3 WO 2008005087 A3 WO2008005087 A3 WO 2008005087A3 US 2007008371 W US2007008371 W US 2007008371W WO 2008005087 A3 WO2008005087 A3 WO 2008005087A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- imprint
- respect
- alignment
- increased flexibility
- imprint technique
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76817—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics using printing or stamping techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
- H01L2221/1015—Forming openings in dielectrics for dual damascene structures
- H01L2221/1021—Pre-forming the dual damascene structure in a resist layer
Abstract
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020097002089A KR101336274B1 (en) | 2006-06-30 | 2007-04-05 | A nano imprint technique with increased flexibility with respect to alignment and feature shaping |
CN200780024239.0A CN101479842B (en) | 2006-06-30 | 2007-04-05 | A nano imprint technique with increased flexibility with respect to alignment and feature shaping |
JP2009518102A JP5244793B2 (en) | 2006-06-30 | 2007-04-05 | Nanoimprint technology with improved flexibility for alignment and feature shaping |
GB0822570A GB2452445A (en) | 2006-06-30 | 2008-12-11 | A nano imprint technique with increased flexibility with respect to alignment and feature shaping |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102006030267A DE102006030267B4 (en) | 2006-06-30 | 2006-06-30 | Nano embossing technique with increased flexibility in terms of adjustment and shaping of structural elements |
DE102006030267.2 | 2006-06-30 | ||
US11/671,688 | 2007-02-06 | ||
US11/671,688 US7928004B2 (en) | 2006-06-30 | 2007-02-06 | Nano imprint technique with increased flexibility with respect to alignment and feature shaping |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2008005087A2 WO2008005087A2 (en) | 2008-01-10 |
WO2008005087A3 true WO2008005087A3 (en) | 2008-03-27 |
Family
ID=38529645
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2007/008371 WO2008005087A2 (en) | 2006-06-30 | 2007-04-05 | A nano imprint technique with increased flexibility with respect to alignment and feature shaping |
Country Status (1)
Country | Link |
---|---|
WO (1) | WO2008005087A2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4825891B2 (en) * | 2009-03-31 | 2011-11-30 | 株式会社東芝 | Semiconductor device manufacturing method and template |
JP5481963B2 (en) * | 2009-06-25 | 2014-04-23 | 富士通株式会社 | Wiring forming method, semiconductor device manufacturing method, and circuit board manufacturing method |
FR3000598B1 (en) * | 2012-12-27 | 2016-05-06 | Commissariat Energie Atomique | IMPROVED METHOD FOR PRODUCING A CONTACT RESUME STRUCTURE |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5173442A (en) * | 1990-07-23 | 1992-12-22 | Microelectronics And Computer Technology Corporation | Methods of forming channels and vias in insulating layers |
US6501180B1 (en) * | 2000-07-19 | 2002-12-31 | National Semiconductor Corporation | Structure and method for controlling copper diffusion and for utilizing low K materials for copper interconnects in integrated circuit structures |
EP1387216A2 (en) * | 2002-08-01 | 2004-02-04 | Hitachi, Ltd. | Stamper, lithographic method of using the stamper and method of forming a structure by a lithographic pattern |
US20040224261A1 (en) * | 2003-05-08 | 2004-11-11 | Resnick Douglas J. | Unitary dual damascene process using imprint lithography |
US20050170269A1 (en) * | 2003-06-20 | 2005-08-04 | Matsushita Electric Industrial Co., Ltd. | Pattern formation method and method for forming semiconductor device |
-
2007
- 2007-04-05 WO PCT/US2007/008371 patent/WO2008005087A2/en active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5173442A (en) * | 1990-07-23 | 1992-12-22 | Microelectronics And Computer Technology Corporation | Methods of forming channels and vias in insulating layers |
US6501180B1 (en) * | 2000-07-19 | 2002-12-31 | National Semiconductor Corporation | Structure and method for controlling copper diffusion and for utilizing low K materials for copper interconnects in integrated circuit structures |
EP1387216A2 (en) * | 2002-08-01 | 2004-02-04 | Hitachi, Ltd. | Stamper, lithographic method of using the stamper and method of forming a structure by a lithographic pattern |
US20040224261A1 (en) * | 2003-05-08 | 2004-11-11 | Resnick Douglas J. | Unitary dual damascene process using imprint lithography |
US20050170269A1 (en) * | 2003-06-20 | 2005-08-04 | Matsushita Electric Industrial Co., Ltd. | Pattern formation method and method for forming semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
WO2008005087A2 (en) | 2008-01-10 |
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