WO2008005301A3 - Mixed analog and digital pixel for high dynamic range readout - Google Patents

Mixed analog and digital pixel for high dynamic range readout Download PDF

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Publication number
WO2008005301A3
WO2008005301A3 PCT/US2007/015069 US2007015069W WO2008005301A3 WO 2008005301 A3 WO2008005301 A3 WO 2008005301A3 US 2007015069 W US2007015069 W US 2007015069W WO 2008005301 A3 WO2008005301 A3 WO 2008005301A3
Authority
WO
WIPO (PCT)
Prior art keywords
pixel
test
dynamic range
analog
integration
Prior art date
Application number
PCT/US2007/015069
Other languages
French (fr)
Other versions
WO2008005301A2 (en
Inventor
Bryan D Ackland
Original Assignee
Noble Peak Vision Corp
Bryan D Ackland
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Noble Peak Vision Corp, Bryan D Ackland filed Critical Noble Peak Vision Corp
Priority to JP2009518277A priority Critical patent/JP2009543454A/en
Priority to EP07810013A priority patent/EP2033433A2/en
Publication of WO2008005301A2 publication Critical patent/WO2008005301A2/en
Publication of WO2008005301A3 publication Critical patent/WO2008005301A3/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/767—Horizontal readout lines, multiplexers or registers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/50—Control of the SSIS exposure
    • H04N25/57—Control of the dynamic range
    • H04N25/59—Control of the dynamic range by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

An improved CMOS pixel with a combination of analog and digital readouts to provide a large pixel dynamic range without compromising low-light performance using a comparator to test the value of an accumulated charge at a series of exponentially increasing exposure times. The test is used to stop the integration of photocurrent once the accumulated analog voltage has reached a predetermined threshold. A one-bit output value of the test is read out of the pixel (digitally) at each of the exponentially increasing exposure periods. At the end of the integration period, the analog value stored on the integration capacitor is read out using conventional CMOS active pixel readout circuits.
PCT/US2007/015069 2006-06-29 2007-06-28 Mixed analog and digital pixel for high dynamic range readout WO2008005301A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2009518277A JP2009543454A (en) 2006-06-29 2007-06-28 Mixed analog and digital pixels for high dynamic range readout
EP07810013A EP2033433A2 (en) 2006-06-29 2007-06-28 Mixed analog and digital pixel for high dynamic range readout

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/427,483 2006-06-29
US11/427,483 US7326903B2 (en) 2006-06-29 2006-06-29 Mixed analog and digital pixel for high dynamic range readout

Publications (2)

Publication Number Publication Date
WO2008005301A2 WO2008005301A2 (en) 2008-01-10
WO2008005301A3 true WO2008005301A3 (en) 2008-03-27

Family

ID=38875620

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/015069 WO2008005301A2 (en) 2006-06-29 2007-06-28 Mixed analog and digital pixel for high dynamic range readout

Country Status (6)

Country Link
US (4) US7326903B2 (en)
EP (1) EP2033433A2 (en)
JP (1) JP2009543454A (en)
KR (1) KR20090023549A (en)
TW (1) TW200822707A (en)
WO (1) WO2008005301A2 (en)

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Also Published As

Publication number Publication date
US8022350B2 (en) 2011-09-20
US20100264296A1 (en) 2010-10-21
JP2009543454A (en) 2009-12-03
US20120001059A1 (en) 2012-01-05
US8586907B2 (en) 2013-11-19
KR20090023549A (en) 2009-03-05
TW200822707A (en) 2008-05-16
WO2008005301A2 (en) 2008-01-10
US20140042304A1 (en) 2014-02-13
US20080001065A1 (en) 2008-01-03
US7326903B2 (en) 2008-02-05
EP2033433A2 (en) 2009-03-11

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