WO2008018738A1 - Fabricating method for chip molding type semiconductor package - Google Patents

Fabricating method for chip molding type semiconductor package Download PDF

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Publication number
WO2008018738A1
WO2008018738A1 PCT/KR2007/003793 KR2007003793W WO2008018738A1 WO 2008018738 A1 WO2008018738 A1 WO 2008018738A1 KR 2007003793 W KR2007003793 W KR 2007003793W WO 2008018738 A1 WO2008018738 A1 WO 2008018738A1
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WO
WIPO (PCT)
Prior art keywords
wafer
molding
bumps
sawing
chip
Prior art date
Application number
PCT/KR2007/003793
Other languages
French (fr)
Inventor
Young Sun Kim
Original Assignee
Young Sun Kim
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020060074002A external-priority patent/KR20060093690A/en
Application filed by Young Sun Kim filed Critical Young Sun Kim
Publication of WO2008018738A1 publication Critical patent/WO2008018738A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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Definitions

  • the present invention relates generally to a method of manufacturing a chip molding type semiconductor package, and more particularly, to a method of manufacturing a chip-sized semiconductor package that is more reliable by forming bumps on the I/O terminals of semiconductor chips in a wafer form, attaching the wafer to a tape, sawing the wafer to the size of the semiconductor chip, and conducting molding.
  • Background Art
  • conventional methods of packaging semiconductor chips include connecting the VO terminals of a semiconductor chip with the I/O terminals of a substrate using fine gold wire, conducting molding, and then forming solder balls on the external I/O terminals of the substrate, thus manufacturing a package.
  • FIG. 1 is a sectional view of a semiconductor plastic package manufactured using a conventional method, a detailed description of which follows.
  • a semiconductor chip 1 is attached to a substrate 5 using adhesive epoxy 6, after which the I/O terminals 2 (which are the bond pads) of the attached semiconductor chip 1 are connected to the internal I/O terminals 4 of the substrate using fine metal wire 3 (e.g., gold wire or aluminum wire).
  • fine metal wire 3 e.g., gold wire or aluminum wire
  • solder balls 9 are formed on the external I/O terminals 8 of the substrate.
  • FIG. 2 is a sectional view of a conventional flip chip bonding package, a description of which follows.
  • flip chip bonding is conducted on a printed circuit board (PCB) 12, after which an underfilling process is conducted using epoxy resin to form an underfill 11, in order to protect the circuit portion of the chip, the bumps 10, and the I/O terminals 2 of the chip.
  • PCB printed circuit board
  • the underfill which is applied in a small amount between the chip and the board, plays a role as an adhesive for holding the chip, and functions to protect the chip from external impacts.
  • the underfill suffers because the process thereof should be minutely and precisely controlled, and furthermore, the underfill is not sufficiently able to electrically and mechanically protect the chip, because part of the side surface of the bare chip is exposed. Disclosure of Invention Technical Problem
  • the present invention has been made keeping in mind the above problems occurring in the related art, and provides a method of manufacturing a chip molding type semiconductor package, without the need for the underfilling process used in a conventional flip chip bonding packaging method, which typically results in a decrease in reliability and an increase in process cost.
  • a method of manufacturing a chip molding type semiconductor package may include a first step of forming bumps on bond pads of a wafer having semiconductor chips, a second step of subjecting the wafer having the bumps to primary sawing to the size of the semiconductor chip, a third step of molding the wafer and conducting baking, thus forming a molding protection layer, and a fourth step of grinding and polishing the protection layer, thus exposing one end of each of the bumps.
  • the second step may be conducted by attaching the surface opposite the surface of the wafer having the bumps to tape and then conducting sawing.
  • the tape is a polymer-based member or a thin metal sheet.
  • the molding in the third step is conducted using a mold die.
  • the molding compound includes an epoxy molding compound (EMC), a thermosetting resin or a thermoplastic resin.
  • EMC epoxy molding compound
  • thermosetting resin thermosetting resin
  • thermoplastic resin thermoplastic resin
  • the molding in the third step is conducted by applying a Silicone Resin on the wafer.
  • plating or soldering the exposed end of the bump with an electrically conductive metal may also be conducted.
  • subjecting the molded chips to secondary sawing may also be conducted, thus forming individual semiconductor packages. As such, in order to allow the side protection layer of the semiconductor chip to remain, the primary sawing and the secondary sawing may be conducted to attain sawing widths different from each other.
  • the method of manufacturing the chip molding type semiconductor package according to the present invention may have the following advantages, compared to conventional methods of manufacturing plastic packages, in which fine gold wires, chips and substrates are molded together.
  • the volume of a package may be remarkably decreased.
  • the method of the present invention may have the following advantages, compared to flip chip methods of wiring bare chips through the formation of bumps.
  • the semiconductor chip can be protected from the external environment, thus increasing reliability.
  • the method of manufacturing the semiconductor package according to the present invention is expected to be efficiently applied to semiconductor chip package products requiring improved electrical properties and reliability of the products, which are manufactured to be light, slim, short and small.
  • FIG. 1 is a sectional view of a semiconductor plastic package, manufactured using a conventional method
  • FIG. 2 is a sectional view of a conventional flip chip bonding package
  • FIGS. 3 to 8 are sectional views of packages sequentially illustrating the process of manufacturing a chip molding type semiconductor package, according to the present invention.
  • FIGS. 9 and 10 are sectional views of final packages, obtained using the m anu- facturing process of the present invention. Mode for the Invention
  • FIGS. 3 to 8 are sectional views of packages sequentially illustrating the process of manufacturing a chip molding type semiconductor package according to the present invention.
  • bumps 10 are formed on the bond pads 2 of a wafer 1 having semiconductor chips (FIG. 3). Such bumps are formed using a material having good electrical conductivity, examples of such material including gold, silver, copper, and aluminum.
  • the piece of tape may include a tape based on a polymer, which is highly resistant to heat, or alternatively, a thin metal sheet may be used.
  • the polymer-based tape may be provided in the form of a film.
  • the surface of the wafer having the bumps is subjected to molding using a mold die and a molding compound, and then baking is conducted, thus forming a molding protection layer 13 (FIG. 5).
  • a molding compound an epoxy molding compound (EMC) is mainly used.
  • EMC epoxy molding compound
  • thermosetting or thermoplastic resin that is transparent, translucent, or opaque may be used.
  • a coating material such as Silicone Resin, coating may be performed on the wafer.
  • the protection layer is subjected to grinding and polishing, thus exposing one end of each of the bumps and controlling the thickness of the protection layer (FIG. 6).
  • a micro I/O terminal 14 is formed on the exposed end of the bump 10 using an electrically conductive material (FIG. 7).
  • the process of forming the above micro I/O terminal may include plating or soldering of electrically conductive metal or solder ball attachment.
  • the exposed bump may be used alone as the micro VO terminal.
  • primary sawing (FIG. 3) and secondary sawing (FIG. 8) may be performed so as to attain sawing widths different from each other. This allows the side protection layer of the semiconductor chip to remain, thereby increasing the operational reliability of the semiconductor package.
  • FIGS. 9 and 10 are sectional views of final packages, obtained using the manufacturing process according to the present invention.
  • FIG. 9 illustrates the micro I/O terminal, formed through plating
  • FIG. 10 illustrates the micro I/O terminal, formed in a solder ball shape.
  • a safe semiconductor package which has an area equal to that of the semiconductor chip and has a minimum volume, may be manufactured by simultaneously molding respective semiconductor chips in a state in which the wafer is sawn, conducting grinding and polishing, and then forming the micro VO terminal on the end of the bump.
  • the present invention provides a method of manufacturing a chip-sized semiconductor package that is more reliable by forming bumps on the I/O terminals of semiconductor chips in a wafer form, attaching the wafer to a tape, sawing the wafer to the size of the semiconductor chip, and conducting molding.
  • the semiconductor package according to the present invention has an area equal to that of the semiconductor chip, therefore drastically decreasing the volume of the package, and furthermore, the electrical properties of the semiconductor chip may be improved, and the chip may be protected from the external environment.
  • the method of the present invention may be widely applied to packages of semiconductor chips for use in wireless communication terminal devices, mobile electronic devices, etc., which require high reliability, a very small size, and ultralight weight.

Abstract

Disclosed is a method of manufacturing a chip molding type semiconductor package that obviates the need for an underfilling process, which typically results in a decrease in reliability and an increase in process cost. The method of manufacturing a chip molding type semi-conductor package includes a first step of forming bumps on the bond pads of a wafer having semiconductor chips, a second step of subjecting the wafer having the bumps to primary sawing to the size of the semiconductor chip, a third step of molding the wafer, and conducting baking, thus forming a molding protection layer, and a fourth step of grinding and polishing the protection layer, thus exposing one end of each of the bumps.

Description

Description
FABRICATING METHOD FOR CHIP MOLDING TYPE SEMICONDUCTOR PACKAGE
Technical Field
[1] The present invention relates generally to a method of manufacturing a chip molding type semiconductor package, and more particularly, to a method of manufacturing a chip-sized semiconductor package that is more reliable by forming bumps on the I/O terminals of semiconductor chips in a wafer form, attaching the wafer to a tape, sawing the wafer to the size of the semiconductor chip, and conducting molding. Background Art
[2] Generally, conventional methods of packaging semiconductor chips include connecting the VO terminals of a semiconductor chip with the I/O terminals of a substrate using fine gold wire, conducting molding, and then forming solder balls on the external I/O terminals of the substrate, thus manufacturing a package.
[3] FIG. 1 is a sectional view of a semiconductor plastic package manufactured using a conventional method, a detailed description of which follows.
[4] First, a semiconductor chip 1 is attached to a substrate 5 using adhesive epoxy 6, after which the I/O terminals 2 (which are the bond pads) of the attached semiconductor chip 1 are connected to the internal I/O terminals 4 of the substrate using fine metal wire 3 (e.g., gold wire or aluminum wire).
[5] Thereafter, molding is conducted using an epoxy molding compound (EMC) 7, in order to protect the semiconductor chip 1 and the fine metal wire 3.
[6] Finally, solder balls 9 are formed on the external I/O terminals 8 of the substrate.
[7] Recently, various types of the above semiconductor packaging method have been developed to satisfy requirements of miniaturization of package size and mounting reliability. In particular, according to the advancement of wireless communication techniques, in portable mobile products, it is essential to miniaturize the semiconductor package and increase the reliability thereof.
[8] That is, the requirement for miniaturization accelerates the development of packages approaching the scale of chips, and the requirement for mounting reliability emphasizes the importance of packaging techniques able to increase the efficiency of a mounting process and mechanical and electrical reliability after mounting.
[9] As the packaging techniques for satisfying such miniaturization, a flip chip bonding packaging method is widely used these days.
[10] FIG. 2 is a sectional view of a conventional flip chip bonding package, a description of which follows. [11] As illustrated in FIG. 2, when the package is used in the form of a bare chip through the formation of bumps, flip chip bonding is conducted on a printed circuit board (PCB) 12, after which an underfilling process is conducted using epoxy resin to form an underfill 11, in order to protect the circuit portion of the chip, the bumps 10, and the I/O terminals 2 of the chip.
[12] Unlike conventional semiconductor molding material (e.g. EMC) for enclosing the entire semiconductor chip to package it, the underfill, which is applied in a small amount between the chip and the board, plays a role as an adhesive for holding the chip, and functions to protect the chip from external impacts.
[13] However, the underfill suffers because the process thereof should be minutely and precisely controlled, and furthermore, the underfill is not sufficiently able to electrically and mechanically protect the chip, because part of the side surface of the bare chip is exposed. Disclosure of Invention Technical Problem
[14] Accordingly, the present invention has been made keeping in mind the above problems occurring in the related art, and provides a method of manufacturing a chip molding type semiconductor package, without the need for the underfilling process used in a conventional flip chip bonding packaging method, which typically results in a decrease in reliability and an increase in process cost. Technical Solution
[15] According to the present invention, a method of manufacturing a chip molding type semiconductor package may include a first step of forming bumps on bond pads of a wafer having semiconductor chips, a second step of subjecting the wafer having the bumps to primary sawing to the size of the semiconductor chip, a third step of molding the wafer and conducting baking, thus forming a molding protection layer, and a fourth step of grinding and polishing the protection layer, thus exposing one end of each of the bumps.
[16] Preferably, the second step may be conducted by attaching the surface opposite the surface of the wafer having the bumps to tape and then conducting sawing.
[17] Preferably, the tape is a polymer-based member or a thin metal sheet.
[18] Preferably, the molding in the third step is conducted using a mold die.
[19] Preferably, the molding compound includes an epoxy molding compound (EMC), a thermosetting resin or a thermoplastic resin.
[20] Preferably, the molding in the third step is conducted by applying a Silicone Resin on the wafer.
[21] Preferably, plating or soldering the exposed end of the bump with an electrically conductive metal may also be conducted. [22] Preferably, subjecting the molded chips to secondary sawing may also be conducted, thus forming individual semiconductor packages. As such, in order to allow the side protection layer of the semiconductor chip to remain, the primary sawing and the secondary sawing may be conducted to attain sawing widths different from each other.
Advantageous Effects
[23] As mentioned above, the method of manufacturing the chip molding type semiconductor package according to the present invention may have the following advantages, compared to conventional methods of manufacturing plastic packages, in which fine gold wires, chips and substrates are molded together.
[24] First, the volume of a package may be remarkably decreased.
[25] Second, electrical properties may be improved.
[26] Third, the material cost and process cost for the package may be decreased.
[27] Further, the method of the present invention may have the following advantages, compared to flip chip methods of wiring bare chips through the formation of bumps.
[28] First, the semiconductor chip can be protected from the external environment, thus increasing reliability.
[29] Second, there is no need for an underfilling process, which needs to be precisely conducted, and thus the overall process may be simplified, consequently decreasing a defective rate and realizing a very low manufacturing cost.
[30] Therefore, the method of manufacturing the semiconductor package according to the present invention is expected to be efficiently applied to semiconductor chip package products requiring improved electrical properties and reliability of the products, which are manufactured to be light, slim, short and small. Brief Description of the Drawings
[31] FIG. 1 is a sectional view of a semiconductor plastic package, manufactured using a conventional method;
[32] FIG. 2 is a sectional view of a conventional flip chip bonding package;
[33] FIGS. 3 to 8 are sectional views of packages sequentially illustrating the process of manufacturing a chip molding type semiconductor package, according to the present invention; and
[34] FIGS. 9 and 10 are sectional views of final packages, obtained using the m anu- facturing process of the present invention. Mode for the Invention
[35] Hereinafter, a detailed description will be given of an embodiment of the present invention, with reference to the appended drawings. [36] FIGS. 3 to 8 are sectional views of packages sequentially illustrating the process of manufacturing a chip molding type semiconductor package according to the present invention.
[37] First, bumps 10 are formed on the bond pads 2 of a wafer 1 having semiconductor chips (FIG. 3). Such bumps are formed using a material having good electrical conductivity, examples of such material including gold, silver, copper, and aluminum.
[38] Subsequently, the surface opposite the surface of the wafer having the bumps is attached to a piece of tape 15, after which the wafer is subjected to primary sawing to the size of the semiconductor chip 1, thus forming individual chips 1 (FIG. 4). The piece of tape may include a tape based on a polymer, which is highly resistant to heat, or alternatively, a thin metal sheet may be used. The polymer-based tape may be provided in the form of a film.
[39] Subsequently, in order to protect the semiconductor chips and the bumps, the surface of the wafer having the bumps is subjected to molding using a mold die and a molding compound, and then baking is conducted, thus forming a molding protection layer 13 (FIG. 5). As the molding compound, an epoxy molding compound (EMC) is mainly used. Further, depending on the end use of the semiconductor package, thermosetting or thermoplastic resin that is transparent, translucent, or opaque may be used. Instead of the molding compound, using a coating material such as Silicone Resin, coating may be performed on the wafer.
[40] Subsequently, the protection layer is subjected to grinding and polishing, thus exposing one end of each of the bumps and controlling the thickness of the protection layer (FIG. 6).
[41] Then, a micro I/O terminal 14 is formed on the exposed end of the bump 10 using an electrically conductive material (FIG. 7). As such, the process of forming the above micro I/O terminal may include plating or soldering of electrically conductive metal or solder ball attachment. Further, in place of the application of the electrically conductive material on the exposed end of the bump, the exposed bump may be used alone as the micro VO terminal.
[42] Finally, the chips, which are molded in a wafer shape, are subjected to secondary sawing to the size of the semiconductor chip 1, thus completing individual semiconductor packages (FIG. 8).
[43] To optimally maintain the protection layer, primary sawing (FIG. 3) and secondary sawing (FIG. 8) may be performed so as to attain sawing widths different from each other. This allows the side protection layer of the semiconductor chip to remain, thereby increasing the operational reliability of the semiconductor package.
[44] FIGS. 9 and 10 are sectional views of final packages, obtained using the manufacturing process according to the present invention. FIG. 9 illustrates the micro I/O terminal, formed through plating, and FIG. 10 illustrates the micro I/O terminal, formed in a solder ball shape.
[45] According to the present invention, unlike general semiconductor packages, obtained by attaching individual chips and conducting molding, and bare chips using only bumps, a safe semiconductor package, which has an area equal to that of the semiconductor chip and has a minimum volume, may be manufactured by simultaneously molding respective semiconductor chips in a state in which the wafer is sawn, conducting grinding and polishing, and then forming the micro VO terminal on the end of the bump. Industrial Applicability
[46] As described hereinbefore, the present invention provides a method of manufacturing a chip-sized semiconductor package that is more reliable by forming bumps on the I/O terminals of semiconductor chips in a wafer form, attaching the wafer to a tape, sawing the wafer to the size of the semiconductor chip, and conducting molding.
[47] The semiconductor package according to the present invention has an area equal to that of the semiconductor chip, therefore drastically decreasing the volume of the package, and furthermore, the electrical properties of the semiconductor chip may be improved, and the chip may be protected from the external environment.
[48] Hence, the method of the present invention may be widely applied to packages of semiconductor chips for use in wireless communication terminal devices, mobile electronic devices, etc., which require high reliability, a very small size, and ultralight weight.

Claims

Claims
[I] A method of manufacturing a chip molding type semiconductor package, comprising: forming bumps on bond pads of a wafer having semiconductor chips; subjecting the wafer having the bumps to primary sawing to a size of the s emi- conductor chip; molding the wafer using a molding material and conducting baking, thus forming a molding protection layer; and grinding and polishing the protection layer, thus exposing one end of each of the bumps. [2] The method according to claim 1, wherein the subjecting the wafer having the bumps to primary sawing is conducted by attaching a surface opposite a surface of the wafer having the bumps to a piece of tape and then conducting sawing. [3] The method according to claim 2, wherein the tape comprises a polymer-based member.
[4] The method according to claim 2, wherein the tape comprises a thin metal sheet.
[5] The method according to claim 1, wherein the molding the wafer is conducted using a mold die. [6] The method according to claim 1, wherein the molding material comprises an epoxy molding compound. [7] The method according to claim 1, wherein the molding material comprises either a thermosetting resin or a thermoplastic resin. [8] The method according to claim 1, wherein the molding the wafer is conducted by applying a Silicone Resin on the wafer. [9] The method according to claim 1, further comprising plating the exposed end of the bump with an electrically conductive metal, thus forming a micro I/O terminal. [10] The method according to claim 1, further comprising soldering the exposed end of the bump with an electrically conductive metal, thus forming a micro VO terminal.
[I I] The method according to claim 1, further comprising subjecting the molded chips to secondary sawing, thus forming individual semiconductor packages.
[12] The method according to claim 11, wherein the primary sawing and the secondary sawing are conducted to attain sawing widths different from each other, in order to allow the side protection layer of the semiconductor chip to remain.
PCT/KR2007/003793 2006-08-07 2007-08-07 Fabricating method for chip molding type semiconductor package WO2008018738A1 (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR10-2006-0074002 2006-08-07
KR1020060074002A KR20060093690A (en) 2006-08-07 2006-08-07 Chip molding type semiconductor package and fabricating this
KR10-2007-0078835 2007-08-07
KR1020070078835A KR20080013770A (en) 2006-08-07 2007-08-07 Fabricating method for chip molding type semiconductor package

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420244B2 (en) * 2000-02-21 2002-07-16 Advanced Semiconductor Engineering, Inc. Method of making wafer level chip scale package
KR20030036372A (en) * 2003-03-17 2003-05-09 김영선 Wafer Coated Type Semiconductor Package and Fabricating this.
KR20060024451A (en) * 2006-02-10 2006-03-16 김영선 Wafer molding type semiconductor package and fabricating this

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6420244B2 (en) * 2000-02-21 2002-07-16 Advanced Semiconductor Engineering, Inc. Method of making wafer level chip scale package
KR20030036372A (en) * 2003-03-17 2003-05-09 김영선 Wafer Coated Type Semiconductor Package and Fabricating this.
KR20060024451A (en) * 2006-02-10 2006-03-16 김영선 Wafer molding type semiconductor package and fabricating this

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