WO2008020810A1 - Edge bond chip connection (ebcc) - Google Patents

Edge bond chip connection (ebcc) Download PDF

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Publication number
WO2008020810A1
WO2008020810A1 PCT/SG2006/000239 SG2006000239W WO2008020810A1 WO 2008020810 A1 WO2008020810 A1 WO 2008020810A1 SG 2006000239 W SG2006000239 W SG 2006000239W WO 2008020810 A1 WO2008020810 A1 WO 2008020810A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
die
substrate
bond
edge
Prior art date
Application number
PCT/SG2006/000239
Other languages
French (fr)
Inventor
Wai Seng Chew
Wee Meng Lim
Original Assignee
Wai Seng Chew
Wee Meng Lim
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wai Seng Chew, Wee Meng Lim filed Critical Wai Seng Chew
Priority to PCT/SG2006/000239 priority Critical patent/WO2008020810A1/en
Priority to TW096116550A priority patent/TW200811967A/en
Publication of WO2008020810A1 publication Critical patent/WO2008020810A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/76—Apparatus for connecting with build-up interconnects
    • H01L2224/7615—Means for depositing
    • H01L2224/76151—Means for direct writing
    • H01L2224/76155—Jetting means, e.g. ink jet
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06551—Conductive connections on the side of the device

Definitions

  • the present invention relates to an integrated circuit package.
  • Integrated circuits are typically assembled into packages that are electrically connected at one or more sides of the die shown in Figure 1 to be known as Edge Bond Chip Connection (EBCC).
  • EBCC Edge Bond Chip Connection
  • the die to die surface attachment or die to substrate surface attachment are mechanically held using composite material which has a coefficient of thermal expansion that is different than the coefficient of the thermal expansion for the integrated circuit.
  • This bonding material is to provide the physical strength of holding both parts together to overcome any mechanical or thermal force induced and moisture stability of the Integrated Circuit Package.
  • the thickness of this bonding material is kept to the minimum to reduce the gap between two surfaces.
  • All electrical bonding pads of the die reside at the edges of the die which are aligned to the adjacent die pads or substrate pads for the electrical connections.
  • These die can be stacked in two or more layers as per Figure 3 and because of the reduction in the gap between die to die or die to substrate and having all the connecting pads at the edges, the Integrated Package could stacked more dies in comparison to the same physical size of an IC using Wire Bonding or Flip Chip technology.
  • the EBCC technology could be a stand alone package or used in combination with existing Flip Chip Technology or Wire Bonding Technique.
  • One embodiment of the present invention is an integrated circuit package which may include an integrated circuit that is mounted over another integrated circuit which could be in numerous layers and finally, mounted to a substrate.
  • the integrate circuit is mechanical bonded to another integrated circuit or substrate using composite material.
  • Figure 1 is a view of an integrated circuit package of the prior art
  • Figure 2 is a view of the integrated circuit package that has the electrical connections on its sides and could be done in any format so long as they are paired to the adjacent;
  • Figure 3 is a view of an integrated circuit package with numerous layers of die stacked that embodied the present invention of the Edge Bond Chip Connection (EBCC).
  • EBCC Edge Bond Chip Connection
  • Step 1 Composite material are first applied to the surface of the substrate.
  • Step 2 A die is vision aligned and placed over the composite material.
  • Step 3 Composite material are then applied over the die surface. Step 2 & 3 are repeated in accordance to the number of layers required. After which, it is sent for oven curing.
  • Step 4 The stacked dies are then electrical connected at the sides employing Edge Bond Chip Connection technique.
  • the connecting bumps materials could be Gold, Silver, Palladium, Solder, conductive epoxy and other conductive materials.
  • the application of these materials not confining to these ranges could be from dispensing, plating, solder jetting, gold bumping, reflow, evaporation, electro less and others.
  • Size and shape of these connecting bumps can be in any form or dimensions. Consequently, when these dies are stacked very closely, it can add more layers in comparison to convention die attached. In doing so, it increases the performances of the package as more layers added equate to increase capacity performance of the package.

Abstract

A seal process step wherein a composite material is applied on an integrated circuit package which may include an integrated circuit that is mounted over another integrated circuit for two or more repeating layers and finally mounted to a substrate. The uniform seal created by the composite material form the mechanical bonding between two surfaces and may inhibit cracking of the integrated circuit (die) during thermo-mechanical loading. The distinctive features of these dies are that, each die has the connecting pads residing at the edge of the die. The introduction of Edge Bond Chip Connection is to make electrical connection at the sides of the dies connecting the pads at the edges.

Description

EDGE BOND CHIP CONNECTION (EBCC)
INTEGRATED CIRCUIT PACKAGE THAT USES ONE OR MORE SIDES OF
THE STACKED DIES FOR THE INTER-CONNECT
BACKGROUND OF THE INVENTION
1.0 FIELD OF THE INVENTION
The present invention relates to an integrated circuit package.
2.0 BACKGROUND INFORMATION
Integrated circuits are typically assembled into packages that are electrically connected at one or more sides of the die shown in Figure 1 to be known as Edge Bond Chip Connection (EBCC).
The die to die surface attachment or die to substrate surface attachment are mechanically held using composite material which has a coefficient of thermal expansion that is different than the coefficient of the thermal expansion for the integrated circuit. This bonding material is to provide the physical strength of holding both parts together to overcome any mechanical or thermal force induced and moisture stability of the Integrated Circuit Package. The thickness of this bonding material is kept to the minimum to reduce the gap between two surfaces.
It is desirable that the air voids are to be avoided as it weakens the structural integrity of the integrated circuit to integrate circuit/substrate interface.
All electrical bonding pads of the die reside at the edges of the die which are aligned to the adjacent die pads or substrate pads for the electrical connections.
It may not necessary that they are connected together in a straight line but so long as they are in pair, reference Figure 2.
These die can be stacked in two or more layers as per Figure 3 and because of the reduction in the gap between die to die or die to substrate and having all the connecting pads at the edges, the Integrated Package could stacked more dies in comparison to the same physical size of an IC using Wire Bonding or Flip Chip technology.
The EBCC technology could be a stand alone package or used in combination with existing Flip Chip Technology or Wire Bonding Technique. SUMMARY OF THE INVENTION
One embodiment of the present invention is an integrated circuit package which may include an integrated circuit that is mounted over another integrated circuit which could be in numerous layers and finally, mounted to a substrate.
The integrate circuit is mechanical bonded to another integrated circuit or substrate using composite material.
All the electrical connections are done at the sides of the integrated circuit.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a view of an integrated circuit package of the prior art; Figure 2 is a view of the integrated circuit package that has the electrical connections on its sides and could be done in any format so long as they are paired to the adjacent;
Figure 3 is a view of an integrated circuit package with numerous layers of die stacked that embodied the present invention of the Edge Bond Chip Connection (EBCC). DETAILED DESCRIPTION OF THE INVENTION
Referring to the drawings more particularly on Figure 3 and Figure 4, shows an embodiment of "EBCC" on an integrated circuit package. Reference to Figure 5 for Process Flow
Step 1 Composite material are first applied to the surface of the substrate.
Step 2 A die is vision aligned and placed over the composite material.
Step 3 Composite material are then applied over the die surface. Step 2 & 3 are repeated in accordance to the number of layers required. After which, it is sent for oven curing.
Step 4 The stacked dies are then electrical connected at the sides employing Edge Bond Chip Connection technique.
The connecting bumps materials could be Gold, Silver, Palladium, Solder, conductive epoxy and other conductive materials. The application of these materials not confining to these ranges could be from dispensing, plating, solder jetting, gold bumping, reflow, evaporation, electro less and others.
Size and shape of these connecting bumps can be in any form or dimensions. Consequently, when these dies are stacked very closely, it can add more layers in comparison to convention die attached. In doing so, it increases the performances of the package as more layers added equate to increase capacity performance of the package.
In addition, with the prospect of thinning the wafer in general, it would further increase the performance capacity while maintaining the same physical size in comparison.

Claims

What is claimed is :
1 An integrated circuit package, comprising of :
- A substrate;
- One or more integrated circuit mounted over the next and consequently having the bottom integrated circuit mounted on the substrate;
- A composite material used to bond the IC to IC or IC to substrate.
2 The package as recited in claim 1, where is said composite material used to bond one surface to the other.
3 These bonding materials will not come in the way of the bonded edges.
4 The integrated circuit can be stacked in numerous layers depending on its desired nature.
5 Having the connecting pads at the edge of the die, the die can be electrically connected at the sides and usage of sides depending on its desired nature. The connecting material could be from a know range of conductive material and the application of such material is dependence its desired nature. Connecting Edge Bond can be of any shapes or sizes. Dies can come in any form of thickness or material so long as contain bonding pads at the edges. Edge Bond Chip Connection is applicable to all integrated circuit packaging which demands for higher performance capabilities in comparison to the same conventional process. EBCC could be used in conjunction with either Wire Bond Technology or Flip Chip process. Or, a combination of either or both.
PCT/SG2006/000239 2006-08-18 2006-08-18 Edge bond chip connection (ebcc) WO2008020810A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/SG2006/000239 WO2008020810A1 (en) 2006-08-18 2006-08-18 Edge bond chip connection (ebcc)
TW096116550A TW200811967A (en) 2006-08-18 2007-05-09 Integrated circuits die package and its bond connection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/SG2006/000239 WO2008020810A1 (en) 2006-08-18 2006-08-18 Edge bond chip connection (ebcc)

Publications (1)

Publication Number Publication Date
WO2008020810A1 true WO2008020810A1 (en) 2008-02-21

Family

ID=39082281

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/SG2006/000239 WO2008020810A1 (en) 2006-08-18 2006-08-18 Edge bond chip connection (ebcc)

Country Status (2)

Country Link
TW (1) TW200811967A (en)
WO (1) WO2008020810A1 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6818998B2 (en) * 2001-06-29 2004-11-16 Samsung Electronics Co., Ltd. Stacked chip package having upper chip provided with trenches and method of manufacturing the same
US6884654B2 (en) * 1998-03-09 2005-04-26 Micron Technology, Inc. Method of forming a stack of packaged memory dice
US7030489B2 (en) * 2003-07-31 2006-04-18 Samsung Electronics Co., Ltd. Multi-chip module having bonding wires and method of fabricating the same
KR20060039143A (en) * 2004-11-02 2006-05-08 삼성전자주식회사 Semiconductor package

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6884654B2 (en) * 1998-03-09 2005-04-26 Micron Technology, Inc. Method of forming a stack of packaged memory dice
US6818998B2 (en) * 2001-06-29 2004-11-16 Samsung Electronics Co., Ltd. Stacked chip package having upper chip provided with trenches and method of manufacturing the same
US7030489B2 (en) * 2003-07-31 2006-04-18 Samsung Electronics Co., Ltd. Multi-chip module having bonding wires and method of fabricating the same
KR20060039143A (en) * 2004-11-02 2006-05-08 삼성전자주식회사 Semiconductor package

Also Published As

Publication number Publication date
TW200811967A (en) 2008-03-01

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