WO2008021705A2

WO2008021705A2 - Linearised transmitter and method of operation for use in wireless communications

Info

Publication number: WO2008021705A2
Application number: PCT/US2007/074700
Authority: WO
Inventors: Ib Fordsmand Pedersen; Hans Blomberg; Niels Svenningsen
Original assignee: Motorola, Inc.
Priority date: 2006-08-11
Filing date: 2007-07-30
Publication date: 2008-02-21
Also published as: GB0615955D0; WO2008021705A3; GB2442775A; GB2442775B

Abstract

An RF (radio frequency) transmitter (100) includes: a forward path (102); an RF power amplifier (126); a feedback path (104), coupled from the power amplifier to the forward path to form a linearising loop; an RF power meter (135) for measuring an output power level of an RF signal produced by the power amplifier and for providing a signal indicating the output power level and a processor (101) for applying periodically to the forward path in a training mode of the transmitter a training signal including an I component including a first ramped waveform portion (405) and a Q component including a second ramped waveform portion (411), and for sampling the signal indicating output power level to find minima corresponding to optimal positions on the first and second ramped waveform portions and for issuing correction signals indicating corresponding DC offset adjustment levels to be applied in an operational mode.

Description

LINEARISED TRANSMITTER AND METHOD OF OPERATION FOR USE IN

WIRELESS COMMUNICATIONS

Field of the Invention

The present invention relates generally to a linearised transmitter and a method of operation for use in wireless communications. The invention relates particularly to training of a linearised transmitter to provide a stable, linear output.

Background of the Invention

Wireless communication systems, for example cellular telephony or private mobile radio communication systems, typically provide for radio telecommunication links to be arranged between a plurality of base transceiver stations (BTSs) and a plurality of user terminals, including mobile stations (MSs) . The term ^Λmobile station' generally includes both hand-portable and vehicular mounted radio communication units. Radio frequency (RF) transmitters are employed in both BTSs and MSs in order to provide wireless communication between the communication units.

In the field of this invention, it is known that continuing pressure on the limited radio spectrum available for radio communication systems is focusing attention on the development of spectrally efficient linear modulation schemes. By using such schemes, more communication units are able to share the allocated spectrum within a defined geographical coverage area (e.g. a communication cell) . An example of a digital mobile radio communication system that uses a linear modulation method, such as IT/4 differential quaternary phase shift keying (DQPSK) , is a TETRA system operating in accordance with the TETRA (TErrestrial Trunked Radio) standard defined by the European Telecommunications Standards Institute (ETSI) .

Typically, RF transmitters employ one or more RF power amplifiers to amplify a modulated RF signal to be transmitted. If such a power amplifier shows non- linearity it can generate undesirable intermodulation products which are observed as out-of-band emissions. In digital mobile radio systems such as TETRA systems, restrictions on out-of-band emissions are strict, e.g. of the order of -6OdBc to -7OdBc relative to the power of a wanted signal in an adjacent channel. Hence, RF transmitters employed in communication terminals in such systems are required to show a high degree of linearity.

However, quantum processes within a typical amplifying device of an RF power amplifier are non-linear by nature, allowing a linear transfer of DC to RF power to be obtained only with a low energy efficiency.

In order to achieve both good linearity and good efficiency, linearisation techniques are used to improve the linearity performance of the more efficient classes of RF power amplifier, for example class AB, B or C amplifiers. One such linearisation technique, often used in designing linear transmitters, is to use a control loop employing a negative feedback control. An example of such a control loop is a Cartesian loop. In such a loop, baseband digital ^ΛI' (in phase) and ^ΛQ' (quadrature phase) feedback control signals are produced by quadrature resolution and downconversion of an RF signal which is a sample of the output signal produced by the RF power amplifier of the final amplifying stage. These baseband digital control signals are combined with corresponding ^ΛI' and ^ΛQ' input signals applied from a baseband processor to a forward path of the transmitter. These combinations are performed at baseband prior to upconversion of the ^ΛI' and ^ΛQ' input signals. The linearising of the output signal produced by the RF power amplifier in such a transmitter requires accurate setting and maintenance of operational parameters in the control loop .

In particular, relative phase and DC offset errors can arise in the control loop owing to RF circuit components being imperfect and having physical properties which drift with temperature and time. Such errors can lead undesirably to a degradation in performance of the transmitter as well as loop instability. In particular, a known degradation in performance is caused by an effect known as 'carrier feed through' in which there is an unwanted presence in an output RF signal of the unmodulated RF carrier signal employed to be modulated by the ^ΛI' and ^ΛQ' modulation signals. Carrier feed through is caused by DC offset errors in the transmitter.

Many transmitters, particularly those having a strict linearity specification, e.g. for use in a TETRA system, employ a procedure to select suitable DC offset adjustments which can be applied to compensate for the DC offset errors. A known procedure to provide fine tuning of the I and Q DC offsets is to adjust the I and Q DC offsets whilst no modulation is applied, to find a minimum in the RF power. This known procedure typically uses an external RF power meter and is applied only once during testing and preparation of the terminal in a factory before the terminal is put into normal operation. Undesirably, during normal use of the terminal, the DC offset adjustments applied in the factory can become inaccurate, leading to a gradual degradation in performance .

Summary of the invention

In accordance with a first aspect of the present invention, there is provided a linearised transmitter for use in wireless communications, the linearised transmitter being as defined in claim 1 of the accompanying claims.

In accordance with the present invention in a second aspect there is provided a method of operation as defined in claim 14 of the accompanying claims.

Further features of the present invention are as defined in the accompanying dependent claims and are as disclosed in the embodiments of the invention to be described.

Embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which:

Brief Description of the accompanying drawings FIG. 1 is a block schematic diagram of an illustrative RF transmitter which may be adapted in accordance with embodiments of the present invention.

FIG. 2 is a block schematic diagram of a portion of the transmitter of FIG. 1 showing more detail of an I channel processor and a Q channel processor of the transmitter.

FIG. 3 is a block schematic diagram of a portion of the transmitter of FIG. 1 showing more detail of a Cartesian feedback processor of the transmitter.

FIG. 4 is a graph of applied signal value versus time for an illustrative training signal employed in a training mode of the transmitter of FIG. 1 in a method of operation embodying the invention.

FIG. 5 is a flow chart of a method of operation embodying the invention in the transmitter of FIG. 1.

FIG. 6 is a waveform diagram illustrating signals employed in the method of FIG. 5.

Description of embodiments of the present invention

FIG. 1 is a block schematic diagram of an illustrative Cartesian loop linearised transmitter 100 which may be adapted in accordance with embodiments of the present invention. The transmitter 100 includes a digital signal processor 101 which generates a baseband digital signal containing information to provide a modulation signal to modulate an RF signal to be transmitted by the transmitter 100. The digital signal processor 101 may carry out other known control and signal processing functions of the transmitter 100. The input baseband digital signal generated by the digital signal processor 101 is provided as an output to a forward path 102 of the transmitter 100 extending from the digital signal processor 101 to an antenna 128 via an RFPA (RF power amplifier) 126 and other components to be described. The forward path 102 includes an I (in-phase) channel 105 and a Q (quadrature phase) channel 107. The baseband digital signal produced by the digital signal processor 101 includes a first component which is an I signal which is delivered via the I channel 105 and a second component which is a Q signal which is delivered via the Q channel 107. The I signal and the Q signal are converted to analog baseband form by a D/A (digital to analog) converter 103. The D/A converter 103 delivers the I signal in baseband analog form to an I channel processor 112 in the I channel 105. The D/A converter 103 also delivers a Q signal in baseband analog form to a Q channel processor 114 in the Q channel 107. The I channel processor 112 and the Q channel processor 114 are described in more detail later with reference to FIG. 2. The I channel processor 112 is connected to an upconverting mixer 120 which is also connected to a local oscillator (carrier frequency synthesizer) 121. The Q channel processor 114 is connected to an upconverting mixer 122 which is also connected to the local oscillator 121 via a ninety degrees phase shifter 123. Output connections from the upconverting mixers 120 and 122 provide inputs to a summer 124 having an output connected in turn to the RFPA 126, a circulator 131 and the antenna 128.

In operation, a baseband I signal produced digitally by the digital signal processor 101 and converted to analog form by the D/A converter 103 is delivered to the I channel processor 112 for processing as described later. A processed output signal produced by the I channel processor 112 is then mixed with a carrier frequency signal from the local oscillator 121 to upconvert the I signal from baseband to RF (radio frequency) to provide a modulated RF signal. A baseband Q signal produced digitally by the digital signal processor 101 and converted to analog form by the D/A converter 103 is delivered to the Q channel processor 114 for processing as described later. A processed output signal produced by the Q channel processor 114 is then mixed with a carrier frequency signal from the local oscillator 121, shifted in phase by ninety degrees by the phase shifter 123, to upconvert the Q signal from baseband to RF to provide a modulated RF signal.

Modulated RF signals produced as outputs by the upconverting mixer 120 of the I channel 105 and the upconverting mixer 122 of the Q channel 107 are combined by the summer 124, and a combined RF signal produced by the summer 124 is amplified by the RFPA 126 to produce an amplified RF output signal. The RFPA 126 receives a supply voltage V₃ produced by a voltage source 113 and regulated by a regulator 111 in a known manner. The regulator 111 may be connected to a known control loop (not shown) which modulates the supply voltage V₃ so that it follows a power envelope of the modulation signal delivered to the forward path 102. The RFPA 126 produces an amplified RF output signal which is delivered via the circulator 131 to the antenna 128. The signal is sent as a radiated over-the-air signal by the antenna 128 to a distant terminal (not shown) at which it is received.

The antenna 128 may (at times when the transmitter 100 is not in operation) also receive an incoming RF signal sent over-the-air from a distant terminal (not shown) and may deliver the received signal for processing to an RF receiver 133 via the circulator 131.

It will be apparent to those skilled in the art that other forms of device may be employed in place of the circulator 131, especially to isolate the RFPA 126 from unwanted energy reflections from the antenna 128. Alternatively, the transmitter 100 may include no circulator, isolator or like device between the RFPA 126 and the antenna 128. Instead, the transmitter 100 may include a known control loop (not shown) which controls gain or attenuation of the modulation signal comprising the I and Q input signals provided to the forward path 102 to compensate for the effect on the RFPA 126 of energy reflections from the antenna 128.

A directional coupler 130 is connected between the RFPA 126 and the circulator 131 to sample the amplified RF output signal produced by the RFPA 126. An output of the directional coupler 130 is connected to a feedback path 104 which extends to the forward path 102 at the I channel processor 112 and the Q channel processor 114. The feedback path 104 includes a Cartesian feedback processor 106 which is described in more detail later with reference to FIG. 3. The Cartesian feedback processor 106 downconverts the sampled signal provided by the directional coupler 130 and produces (i) an I feedback control signal which is delivered via an I feedback path 115 to the I channel processor 112; and (ii) a Q feedback control signal which is delivered via a Q feedback path 117 to the Q channel processor 114. A closed Cartesian loop is formed by the forward path 102 from the processors 112 and 114 to the RFPA 126 and the directional coupler 130, and the feedback path 104 including the Cartesian feedback processor 106 and the feedback paths 115 and 117.

A control loop 119 including a phase training processor 108 is connected to the Cartesian feedback processor 106. The control loop 119 operates in a known manner to detect and correct any relative phase error between I and Q feedback control signals in the Cartesian loop.

An output of the directional coupler 130 is also connected to an RF power meter 135 to sample and measure an output power level of the amplified RF output signal produced by the RFPA 126. This measurement can be used to find a minimum level of carrier feed through detected in the signal amplified by the RFPA 126. A signal indicating in digital form the measurements carried out by the RF power meter 135 is delivered via a connection 143 from the RF power meter 135 to the digital signal processor

101. Output connections 146 and 148 are provided from the digital signal processor 101 to a D/A converter 147. The digital signal processor 101 monitors the RF output power indicated by the signal from the RF power meter 135 and uses the monitoring, in a manner described later with reference to FIGS. 4 to 6, to produce output signals indicating adjustments required to eliminate carrier feed through. The output signals are digital signals which indicate a size of DC offset correction signals required to be combined respectively with the I and Q signals produced by the D/A converter 103. The digital output signals produced by the digital signal processor 101 are thus applied via the connections 146, 148 to the D/A converter 147. These signals could alternatively be applied serially via a single connection. The D/A converter 147 converts each digital signal into a required DC offset correction signal. A first or ^ΛI' DC offset correction signal produced by the D/A converter 147 is applied to the I channel processor 112. A second or ^ΛQ' DC offset correction voltage is applied to the Q channel processor 114.

FIG. 2 shows a portion 200 of the transmitter 100 including more detail of the I channel processor 112 and the Q channel processor 114 (which are indicated by dashed lines in FIG. 2) . Parts in FIG. 2 having the same reference numerals as parts shown in FIG. 1 are the same as such parts. The I channel 105 includes, connected to the D/A converter 103 and connected together in turn, a summer 201, a summer 205, an amplifier/ filter 209 and the upconverting mixer 120. The Q channel 107 includes, connected to the D/A converter 103 and connected together in turn, a summer 203, a summer 207, an amplifier/ filter 211 and the upconverting mixer 122. In an operational mode, the summer 201 combines the I signal produced by the D/A converter 103 with the I DC offset correction signal produced by the D/A converter 147 to produce a corrected I signal. Also in the operational mode, the summer 203 combines the Q signal produced by the D/A converter 103 with the Q DC offset correction signal produced by the D/A converter 147 to produce a corrected Q signal. The corrected I and Q signals produced by the summers 201 and 203 are provided as respective input signals to the further summers 205 and 207. The I and Q feedback control signals delivered from the Cartesian feedback processor 106 (FIG. 1) via the I feedback path 115 and the Q feedback path 117 are combined respectively with the corrected I and Q signals from the summers 201 and 203 by the summer 205 and the summer 207. The summers 205 and 207 thereby provide further corrected I and Q signals which are delivered respectively to the amplifier/ filter 209 and the amplifier/filter 211. Each of the amplifier/filter 209 and the amplifier/filter 211 comprises a low pass filter which serves as a known slew rate limiter (A/D reconstruction filter) in a known manner .

It will be apparent to those skilled in the art that the DC offset correction signal produced by the D/A converter 147 could be combined with the I and Q signals (in the forward path 102 to produce corrected I and Q signals) alternatively at the summers 205 and 207 respectively or at further summers (not shown) in the I channel 105 and the Q channel 107 before the mixers 120 and 122.

Alternatively, the D/A converter 147 may be omitted and the correction signals produced by the digital signal processor 101 indicating a required DC offset correction may be combined in digital form with the I and Q signals in digital form inside the digital signal processor 101.

In alternative forms of the transmitter 100 which will be readily apparent to those skilled in the art, the summers 201 and 203 or the summers 205 and 207 may be replaced by differential amplifiers. Furthermore, an amplifier and low pass filter (not shown) may be included in each of the feedback loops 115 and 117. Such amplifiers and filters may be included instead of or in addition to the amplifier/ filters 209 and 211.

In another alternative form of the transmitter 100, the power meter 135 may be arranged to measure an RF power before the RFPA 126. Thus the RF power meter 135 may be arranged to measure the RF power of the RF signal produced as an output by the summer 124.

FIG. 3 shows a portion 300 of the transmitter 100 including more detail of the feedback path 104 including the Cartesian feedback processor 106 (indicated in FIG. 3 by a dashed line) . Parts in FIG. 3 having the same reference numerals as parts shown in FIG. 1 are the same as such parts. The Cartesian feedback processor 106 includes an attenuator 301 connected to receive an input signal from the directional coupler 130. An output connection from the attenuator 301 is branched to form the I feedback path 115 and the Q feedback path 117. The I feedback path 115 includes a downconverting mixer 303 connected to the attenuator 301 and also connected to a local oscillator 307. The downconverting mixer 303 is connected to provide an output signal to the summer 205 (FIG. 2) via a switch 311. The Q feedback path 117 includes a downconverting mixer 305 which is connected to the attenuator 301 and also is connected to the local oscillator 307 via a ninety degrees phase shifter 309. The downconverting mixer 305 is connected to provide an output signal to the summer 207 (FIG. 2) via a switch 313.

In an operational mode of the Cartesian loop of the transmitter 100, the switches 137 and 139 are closed so that the Cartesian loop is completed. The directional coupler 130 supplies the feedback path 104 with a feedback signal representing the amplified RF output signal produced by the RFPA 126. The feedback signal is attenuated by the attenuator 301. The attenuated feedback signal is downconverted into I and Q feedback baseband component signals by the mixers 303 and 305. These signals are baseband I and Q feedback control signals which are combined respectively in the summer 205 and the summer 207 with the corrected I signal and the corrected Q signal delivered respectively by the summers 201 and 203 to the summers 205 and 207 (FIG. 2) . The feedback paths 115 and 117 thereby provide a known mechanism for maintaining linear operation of the transmitter 100 by forcing the transmitter 100 to produce an RF output which follows the corrected I signal and the corrected Q signal supplied along the channels 105 and 107 respectively to the summers 205 and 207.

A training mode is applied in the transmitter 100 when the operational mode is suspended. In the training mode, the switches 313 and 311 are opened so that the feedback paths 115 and 117 are disconnected from the I channel 105 and the Q channel 107. The phase training processor 108 comes into operation in a known way during the training mode. The phase training processor 108 receives baseband input signals from the feedback paths 115 and 117 respectively at the outputs of the mixers 303 and 305. The phase training processor 108 thereby measures in a known way any error in the relative phase between the input signals. The phase training processor 108 produces an output control signal which is delivered via the control loop 119 to the local oscillator 307 to adjust a relative phase of the reference signal produced by the local oscillator 307 to compensate for the measured phase error.

The local oscillator 121 (FIG. 1) and the local oscillator 307 (FIG. 3) may be separate local oscillators as shown although they could be combined in the form of a single local oscillator. In the latter case a phase adjustment is applied to the output from the local oscillator to the mixer 303 and the mixer 305 via the ninety degrees phase shifter 309.

FIG. 4 is a graph 400 of an illustrative training signal applied from the digital signal processor 101 to the forward path 102 in the transmitter 100 in a training mode of the transmitter 100. The vertical axis in FIG. 4 is signal value (amplitude measured relative to amplitude units of the I and Q signals employed in the operational mode) and the horizontal axis is time. The training signal shown in FIG. 4 is applied repeatedly during training time slots selected from available time slots of a timing sequence employed in operation by the transmitter 100. Each of the available training slots may be a TETRA training slot which is available once per second in every eighteenth frame of the TETRA TDMA (time divided multiple access) timing sequence. In that case, the training signal may occupy the second half slot of each selected TETRA training slot and may have a length (duration) of approximately 7 milliseconds. The applied training signal includes a first component which is an I training signal 401 indicated by a full line in FIG. 4.

The I training signal 401 is applied to the I channel 105 during each period that the transmitter 100 is in its training mode. The applied training signal also includes a second component which is a Q training signal 403 indicated by a dashed line in FIG. 4. The Q training signal 403 is applied to the Q channel 107 during each period that the transmitter 100 is in its training mode.

The I training signal 401 includes a ramped waveform portion 405 in which the signal 401 has an upward ramp which reaches a peak 407. After the peak 407, the I training signal 401 falls to a signal value which was reached part-way along the ramp of the ramped waveform portion 405. The I training signal then has a constant portion 413. Whilst the I training signal 401 is in the ramped waveform portion 405, the Q training signal 403 has a constant portion 404. Following the constant portion 404, the Q training signal 403 includes a ramped waveform portion 411 having an upward ramp. The Q training signal 403 begins the ramped waveform portion

411 at a signal value below that of the constant portion 404 and at a point in time co-incident with the ramped portion 405 reaching the peak 407. The ramped waveform portion 405 has a gradient and a length which are the same as for the ramped waveform portion 411. The ramped waveform portion 411 reaches a peak 415 and then the Q training signal 403 falls to a lower value to begin a further constant portion 417. The constant portion 417 of the Q training signal 403 is shown in FIG. 5 to coincide approximately with (part of) the constant portion 413 of the I training signal 401, although such a co-incidence need not necessarily be present.

Following the constant portion 413, the I training signal 401 has a ^Λsquiggle' (spike) portion 419 is which the signal value rises steeply to reach a truncated peak (not shown) then falls steeply to reach a truncated trough

(not shown) and then rises again to reach the same signal value as for the constant portion 413. Such a squiggle portion 419 is a waveform portion that is known per se for phase training.

The ramped waveform portions 405 and 411 are employed in the training mode of the transmitter 100 to provide DC offset fine tuning to eliminate (or at least reduce) carrier feed through. A signal representing discrete samples of the output RF power of the RFPA 126 as measured by the power meter 135 whilst the ramped waveform portions 405 and 411 are being applied is delivered to and recorded by the digital signal processor 101. The digital signal processor 101 thereby produces for discrete samples of the ramped waveform portions 405 and 411 a graph or table of corresponding values of the measured RF output power. The digital signal processor 101 obtains from the graph or table an optimal value of each of the ramped waveform portions 405 and 411 at which the output RF power reaches a local minimum. The digital signal processor 101 records the optimal values of the ramped waveform portions 405 and 411 for use in the operational mode.

The squiggle portion 419 of the I training signal is employed in the training mode of the transmitter 100 to provide phase training to allow any phase imbalance in the Cartesian linearising loop to be detected and compensated for by the phase training processor 108 in a known manner.

FIG. 5 is a flow chart showing an illustrative method 500 of operation embodying the invention in the transmitter 100 to apply adjustments to eliminate errors in DC offsets and relative phase. In a step 501, an operational mode of the transmitter 100 is suspended and a training mode is begun by opening of the switches 311 and 313

(FIG. 3) . This may be at the start of a designated time slot in an operational timing sequence used by the transmitter 100, e.g. a training half slot of a TETRA TDMA timing sequence. The digital signal processor 101 prepares to apply a training signal, comprising a first component which is an I signal for application to the I channel 105, e.g. in the form of the I training signal 401, and a second component which is a Q signal for application to the Q channel 107, e.g. in the form of the Q training signal 403. In a step 503, the I signal and the Q signal are set to start at signal values which correspond respectively to optimal DC offset values determined by a previous run of the method 500. In a step 505, the training signal is applied. The I and Q signals which are components of the training signal are applied respectively to the I channel 105 and the Q channel 107. In a step 507, an optimal DC offset for the I signal is found. During application of a ramped portion of the I signal, e.g. the ramped waveform portion 405 shown in FIG. 4, the output RF power measured by the RF power meter 135 is sampled by the digital signal processor 101 to find a point on the ramped portion when the output RF power is a local minimum (i.e. local to the ramped portion) . Samples may be taken at a rate suitable to allow a local minimum to be found during the ramped portion of the I signal. An example of a suitable sampling rate is 84,000 samples per second (588 samples per half slot) . The point when the output RF power is a local minimum is recorded by the digital signal processor 101 as corresponding to an optimal DC offset for the I signal. Similarly, in a step 509, an optimal DC offset for the Q signal is found. During application of a ramped portion of the Q signal, e.g. the ramped waveform portion 411 shown in FIG. 4, the output RF power measured by the RF power meter 135 is sampled by the digital signal processor 101 to find a point on the ramped portion when the output RF power is a local minimum. The sampling rate may be the same as for the ramped portion of the I signal. The appropriate point on the ramped portion of the Q signal is recorded by the digital signal processor 101 as corresponding to an optimal DC offset for the Q signal. In a step 511, the optimal DC offset for the I signal and for the Q signal are set by the digital signal processor 101 by issue of appropriate correction signals, e.g. to the D/A converter 147. In a step 513, the training mode ends and the operational mode re-starts by closing of the switches 311 and 313. In a step 515 which begins when step 513 is applied, the optimal DC offset values for the I signal and the Q signal are applied in the operational mode, e.g. from the D/A converter 147 via the summers 201 and 203 (FIG. 2) . These DC offset values are maintained until the next run of the method 500.

In a step 517 of the method 500 following the step 505, a relative phase error in the Cartesian loop of the transmitter 100 between an I feedback control signal and a Q feedback control signal in the loop is found in a known manner by the phase training processor 108. In a step 519, the phase of the reference signal produced by the local oscillator 307 is adjusted to eliminate the phase error found in step 515. Finally, in a step 521 which begins when step 513 is applied, the phase of the reference signal produced by the local oscillator 307 adjusted in step 519 is used in the operational mode of the transmitter 100. This adjusted phase value is maintained until the next run of the method 500.

In the method 500, the following further steps may be applied for convenience. The digital signal processor 101 may record in an internal buffer (not shown) of the digital signal processor 101, samples of the I signal and the Q signal of the training signal as they are delivered to the forward path 102 during the training mode. The samples may be taken at the same rate at which the RF power is monitored and recorded, e.g. 84,000 samples per second as mentioned earlier. Monitoring and recording of the RF power may be started at the same time as recording of the samples of the I signal and the Q signal of the training signal. When all samples of the I signal and the Q signal have been recorded in the buffer, the recorded RF power samples may be aligned with the recorded I and Q signals by finding a local maximum of the RF power that corresponds to the I signal first reaching a maximum at the squiggle 419.

FIG. 6 is a waveform diagram 600 illustrating graphically steps 507 and 509 of the method 500. In a lower part of the waveform diagram 600 a DC offset adjustment portion of a training signal applied to the forward path 102 is shown. The training signal includes in this portion an I signal 601 including a ramped portion 603 and a Q signal 602 including a ramped portion 604. In an upper part of the waveform diagram 600 a plot 605 of the corresponding RF output power is shown. The plot 605 is aligned (synchronised) to the I signal 601 and the Q signal 602, e.g. using the aligning procedure described above. A first local minimum 606 is shown by the plot 605. This is level along the horizontal axis, which represents time, with a point 607 on the ramped portion 603 of the I signal 601. A second local minimum 608 is shown by the plot 605. This is level along the horizontal axis with a point 609 on the ramped portion 604 of the Q training signal 602. The value along the vertical axis, which for the I signal 603 represents baseband signal amplitude, of the point 607 is the optimum setting of the required I DC offset. The value along the vertical axis of the point 609 is the optimum setting of the required Q DC offset. The gradient of the ramped portions 603 and 604 is shown in FIG. 6 to be constant. The ramped portions 603 and 604 may however have a gradient that varies locally, especially in localised regions where the optimum points 607 and 609 are expected, in order to facilitate finding of the optimum points 607 and 609.

Gradient analysis techniques known in the art of signal processing may be employed in the digital signal processor 101 to analyse the plot 605 to identify positions on the plot 605 where the minimum 606 and the minimum 608 occur.

Beneficially, by repeated running of the method 500 in selected training time slots, carrier feed through caused by drifting of the operational parameters of the transmitter 100 can be kept to a negligible or acceptable level. This maintains a suitable quality of the transmitted RF signal and helps to maintain suitable stability in the Cartesian linearising loop. The method 500 is aimed at providing fine tuning of the DC offset values required to be applied (as well as known adjustment of the relative phase) . Where a large adjustment is required to the DC offset values, e.g. soon after initial powering up of the transmitter 100, the required adjustment may not be achieved by a single run of the method 500. However, by repeated iterative application of the method 500, the transmitter 100 soon becomes fine tuned at the required optimal DC offset levels. The fine tuning may suitably achieve an attenuation of the carrier feed through of more than 3OdB, desirably more than 4OdB. Such a repeated fine tuning is not achieved in the prior art.

The method 500 illustrates use of DC offset adjustment training and phase training in the same time slot (e.g. in the same second half slot of a TETRA training slot) using the same training signal (e.g. comprising the signals 401 and 403 in FIG. 4) . A training signal employed for DC offset adjustments may in some or all training slots be applied separately from a training signal applied for phase training. For example, when using a multiframe timing sequence, a training signal for DC offset adjustments may be applied in a training slot of each odd numbered frame and a training signal for phase adjustment may be applied in a training slot of each even numbered frame. Alternatively, for example, in a training slot of each nth frame of a multiframe timing sequence a training signal for both DC offset adjustments and phase adjustment may be applied and in a training slot of each other frame a training signal for phase adjustment only may be applied. For example, n may be an integer between 4 and 12.

In any event, in order to minimise the requirement for additional signal processing in the digital signal processor 101, the RF power meter 135 may be selectively activated so that it monitors RF power only during application of the training signal or part of the training signal applied for DC offset adjustment training. The RF power meter 135 may conveniently be provided by a processor, e.g. in the form of a semiconductor microchip, incorporated within the transmitter 100 and operably coupled to, or even forming part of, the digital signal processor 101. Such an arrangement may be operated more quickly and efficiently than the arrangements of the prior art and is suited to the repeated fine tuning of DC offsets as described herein .

Although the method 500 illustrates the same training signal used to provide DC offset adjustment training and phase training with the portion of the training signal for DC offset adjustment training applied prior to the portion of the training signal for phase training, the portion of the training signal applied for phase training, e.g. comprising the squiggle 419 in FIG. 4, may alternatively be applied prior to the portion applied for DC offset adjustment training, e.g. the ramped waveform portions 405 and 411 in FIG. 4.

The transmitter 100 provides improved efficient linear operation in an RF communication terminal, especially a terminal that operates at full power for most of the time. The transmitter is suitable for use in a base transceiver station of a cellular or trunked communication system, particularly a TETRA system or another system requiring linear transmitter operation, e.g. an APCO 25 system operable in accordance with the APCO Project 25 standard defined by APCO (the Association of Public-Safety Communications Officials-International, Inc.) .

Claims

1. An RF (radio frequency) transmitter including: a forward path for delivering a signal for transmission; an RF power amplifier; a feedback path, coupled from the power amplifier to the forward path to form a linearising loop; an RF power meter for measuring in a training mode the output power level of an RF signal in the forward path and for providing a signal indicating the output power level; and a processor for (i) applying to the forward path in a periodically applied training mode of the transmitter a training signal including, for application to an I (in phase) channel of the forward path, an I component including a first ramped waveform portion and, for application to a Q (quadrature phase) channel of the forward path, a Q component including a second ramped waveform portion, and (ii) for sampling the signal indicating output power level to find minima corresponding to optimal positions on the first and second ramped waveform portions, and (iii) for issuing correction signals, corresponding to the optimal positions, indicating DC offset adjustments to be applied in an operational mode.

2. An RF transmitter according to claim 1 wherein the processor is operable to apply one of the first and second ramped waveform portions following the other of the first and second ramped waveform portions .

3. An RF transmitter according to claim 2 wherein the processor is operable to start applying one of the ramped waveform portions when the other of the ramped waveform portions reaches a peak.

4. An RF transmitter according to claim 3 wherein the processor is operable to apply the training signal periodically in a selected training slot of a multislot operational timing sequence employed by the transmitter.

5. An RF transmitter according to claim 4 wherein the selected training slot is a time slot of a TDMA (time divided multiple access) timing sequence of a communication system in which the transmitter is operable .

6. An RF transmitter according to claim 5 wherein the transmitter is operable in accordance with the TETRA standard and the processor is operable to apply the training signal in the second half slot of selected training time slots.

7. An RF transmitter according to claim 4 wherein the processor is operable to apply during a selected training slot in which the training signal including the first and second ramped waveform portions is applied a further training signal portion to allow a further parameter of the linearising loop to be adjusted.

8. An RF transmitter according to claim 7 wherein the further parameter comprises a relative phase difference between signals in the linearising loop.

9. An RF transmitter according to claim 8 wherein the first and second ramped waveform portions of the training signal are applied before or after the further training signal portion.

10. An RF transmitter according to claim 9 wherein in the selected training slot an I component of the training signal has a continuous waveform which includes the first ramped waveform portion and an I component of the further training portion.