WO2008027216A3 - Processes and integrated systems for engineering a substrate surface for metal deposition - Google Patents

Processes and integrated systems for engineering a substrate surface for metal deposition Download PDF

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Publication number
WO2008027216A3
WO2008027216A3 PCT/US2007/018270 US2007018270W WO2008027216A3 WO 2008027216 A3 WO2008027216 A3 WO 2008027216A3 US 2007018270 W US2007018270 W US 2007018270W WO 2008027216 A3 WO2008027216 A3 WO 2008027216A3
Authority
WO
WIPO (PCT)
Prior art keywords
metal
substrate surface
copper
integrated system
processes
Prior art date
Application number
PCT/US2007/018270
Other languages
French (fr)
Other versions
WO2008027216A2 (en
WO2008027216A9 (en
Inventor
Yezdi Dordi
Fritz C Redeker
John Boyd
William Thie
Tiruchirapalli Arunagiri
Arthur M Howald
Hyungsuk Alexander Yoon
Johan Vertommen
Original Assignee
Lam Res Corp
Yezdi Dordi
Fritz C Redeker
John Boyd
William Thie
Tiruchirapalli Arunagiri
Arthur M Howald
Hyungsuk Alexander Yoon
Johan Vertommen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/513,446 external-priority patent/US8747960B2/en
Priority claimed from US11/513,634 external-priority patent/US8771804B2/en
Priority claimed from US11/514,038 external-priority patent/US8241701B2/en
Application filed by Lam Res Corp, Yezdi Dordi, Fritz C Redeker, John Boyd, William Thie, Tiruchirapalli Arunagiri, Arthur M Howald, Hyungsuk Alexander Yoon, Johan Vertommen filed Critical Lam Res Corp
Priority to KR1020097004276A priority Critical patent/KR101506352B1/en
Priority to CN200780032409.XA priority patent/CN101558186B/en
Priority to JP2009526621A priority patent/JP5489717B2/en
Publication of WO2008027216A2 publication Critical patent/WO2008027216A2/en
Publication of WO2008027216A3 publication Critical patent/WO2008027216A3/en
Publication of WO2008027216A9 publication Critical patent/WO2008027216A9/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material

Abstract

The embodiments provide processes and integrated systems that produce a metal-to-metal or a silicon-to-metal interface to enhance electro-migration performance, to provide lower metal resistivity, and to improve metal-to-metal or silicon-to-metal interfacial adhesion for copper interconnects. An exemplary method of preparing a substrate surface to selectively deposit a thin layer of a cobalt-alloy material on a copper surface of in an integrated system to improve electromigration performance of a copper interconnect is provided. The method includes removing contaminants and metal oxides from the substrate surface in the integrated system, and reconditioning the substrate surface using a reducing environment after removing contaminants and metal oxides in the integrated system. The method also includes selectively depositing the thin layer of cobalt-alloy material on the copper surface of the copper interconnect in the integrated system after reconditioning the substrate surface. System to practice the exemplary method described above are also provided.
PCT/US2007/018270 2006-08-30 2007-08-17 Processes and integrated systems for engineering a substrate surface for metal deposition WO2008027216A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020097004276A KR101506352B1 (en) 2006-08-30 2007-08-17 Processes and integrated systems for engineering a substrate surface for metal deposition
CN200780032409.XA CN101558186B (en) 2006-08-30 2007-08-17 Processes and integrated systems for engineering a substrate surface for metal deposition
JP2009526621A JP5489717B2 (en) 2006-08-30 2007-08-17 Method and integrated system for conditioning a substrate surface for metal deposition

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US11/513,446 US8747960B2 (en) 2005-08-31 2006-08-30 Processes and systems for engineering a silicon-type surface for selective metal deposition to form a metal silicide
US11/514,038 2006-08-30
US11/513,446 2006-08-30
US11/513,634 US8771804B2 (en) 2005-08-31 2006-08-30 Processes and systems for engineering a copper surface for selective metal deposition
US11/513,634 2006-08-30
US11/514,038 US8241701B2 (en) 2005-08-31 2006-08-30 Processes and systems for engineering a barrier surface for copper deposition

Publications (3)

Publication Number Publication Date
WO2008027216A2 WO2008027216A2 (en) 2008-03-06
WO2008027216A3 true WO2008027216A3 (en) 2008-04-17
WO2008027216A9 WO2008027216A9 (en) 2008-05-22

Family

ID=39136458

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2007/018270 WO2008027216A2 (en) 2006-08-30 2007-08-17 Processes and integrated systems for engineering a substrate surface for metal deposition

Country Status (2)

Country Link
KR (1) KR101506352B1 (en)
WO (1) WO2008027216A2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090269507A1 (en) 2008-04-29 2009-10-29 Sang-Ho Yu Selective cobalt deposition on copper surfaces
KR101685372B1 (en) * 2010-05-07 2016-12-12 성균관대학교 산학협력단 Method for forming copper alloy by cyclic deposition
US8603913B1 (en) * 2012-12-20 2013-12-10 Lam Research Corporation Porous dielectrics K value restoration by thermal treatment and or solvent treatment
WO2018063815A1 (en) 2016-10-02 2018-04-05 Applied Materials, Inc. Doped selective metal caps to improve copper electromigration with ruthenium liner
US11913107B2 (en) * 2019-11-08 2024-02-27 Applied Materials, Inc. Methods and apparatus for processing a substrate
US11380536B2 (en) * 2020-05-05 2022-07-05 Applied Materials, Inc. Multi-step pre-clean for selective metal gap fill
US20220375751A1 (en) * 2021-05-24 2022-11-24 Applied Materials, Inc. Integrated epitaxy and preclean system
KR102619817B1 (en) * 2022-05-19 2024-01-02 세메스 주식회사 Method of forming semiconductor device and substrate processing system for forming semiconductor device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6017820A (en) * 1998-07-17 2000-01-25 Cutek Research, Inc. Integrated vacuum and plating cluster system
US6239006B1 (en) * 1999-07-09 2001-05-29 Advanced Micro Devices, Inc. Native oxide removal with fluorinated chemistry before cobalt silicide formation
US20010055934A1 (en) * 2000-06-22 2001-12-27 Applied Materials, Inc. Method and apparatus for treating a substrate
US6365516B1 (en) * 2000-01-14 2002-04-02 Advanced Micro Devices, Inc. Advanced cobalt silicidation with in-situ hydrogen plasma clean
US20030022509A1 (en) * 1998-11-17 2003-01-30 Applied Materials, Inc. Plasma treatment for copper oxide reduction
US6843852B2 (en) * 2002-01-16 2005-01-18 Intel Corporation Apparatus and method for electroless spray deposition
US6875693B1 (en) * 2003-03-26 2005-04-05 Lsi Logic Corporation Via and metal line interface capable of reducing the incidence of electro-migration induced voids
US6890853B2 (en) * 2000-04-25 2005-05-10 Tokyo Electron Limited Method of depositing metal film and metal deposition cluster tool including supercritical drying/cleaning module

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7232766B2 (en) 2003-03-14 2007-06-19 Lam Research Corporation System and method for surface reduction, passivation, corrosion prevention and activation of copper surface
US7211508B2 (en) * 2003-06-18 2007-05-01 Applied Materials, Inc. Atomic layer deposition of tantalum based barrier materials
TW200530427A (en) * 2003-10-17 2005-09-16 Applied Materials Inc Selective self-initiating electroless capping of copper with cobalt-containing alloys

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6017820A (en) * 1998-07-17 2000-01-25 Cutek Research, Inc. Integrated vacuum and plating cluster system
US20030022509A1 (en) * 1998-11-17 2003-01-30 Applied Materials, Inc. Plasma treatment for copper oxide reduction
US6239006B1 (en) * 1999-07-09 2001-05-29 Advanced Micro Devices, Inc. Native oxide removal with fluorinated chemistry before cobalt silicide formation
US6365516B1 (en) * 2000-01-14 2002-04-02 Advanced Micro Devices, Inc. Advanced cobalt silicidation with in-situ hydrogen plasma clean
US6890853B2 (en) * 2000-04-25 2005-05-10 Tokyo Electron Limited Method of depositing metal film and metal deposition cluster tool including supercritical drying/cleaning module
US20010055934A1 (en) * 2000-06-22 2001-12-27 Applied Materials, Inc. Method and apparatus for treating a substrate
US6843852B2 (en) * 2002-01-16 2005-01-18 Intel Corporation Apparatus and method for electroless spray deposition
US6875693B1 (en) * 2003-03-26 2005-04-05 Lsi Logic Corporation Via and metal line interface capable of reducing the incidence of electro-migration induced voids

Also Published As

Publication number Publication date
WO2008027216A2 (en) 2008-03-06
WO2008027216A9 (en) 2008-05-22
KR101506352B1 (en) 2015-03-26
KR20090052331A (en) 2009-05-25

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