WO2008042179A1 - Transitioning a computing platform to a low power system state - Google Patents
Transitioning a computing platform to a low power system state Download PDFInfo
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- WO2008042179A1 WO2008042179A1 PCT/US2007/020749 US2007020749W WO2008042179A1 WO 2008042179 A1 WO2008042179 A1 WO 2008042179A1 US 2007020749 W US2007020749 W US 2007020749W WO 2008042179 A1 WO2008042179 A1 WO 2008042179A1
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- computing platform
- state
- power
- controller
- power system
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
Definitions
- a computing platform e.g., a personal computer
- power management is coordinated and controlled by an operating system and its associated software (e.g., power management software).
- Various industry standards describe how power management may by implemented by the computing platform and the operating system.
- One such industry standard is the Advanced Configuration Power Interface Specification, Revision 3.0a, published December 30, 2005, and/or later revisions ("the ACPI Specification").
- the ACPI specification defines computing platform or system power states as "S-states" and these states are denoted in the ACPI specification as SO, Sl, S2, S3, S4 and S5. In a common usage these S-states are available for power management of a computing platform.
- the S-states include three categories that are denoted in the ACPI specification as “working”, “sleeping” and “soft off states.
- the working state includes the SO state
- the sleeping state includes Sl, S2, S3 and S4 states
- the soft off state includes the S5 state. Transition of a computing platform between working, sleeping ⁇ and_ ⁇ oft off states is typically controlled by an operating system's power management software.
- Fig. 1 is a block diagram of an example computing platform
- Fig.2 is an example block diagram of a portion of a controller to include logic to transition the computing platform between higher and lower power states;
- Fig.3 is an example flow diagram of the computing platform transitioning to and from various power states.
- Fig.4 is a flow chart of an example method to transition the computing platform between a run and a low power system state.
- transition of a computing platform between working, sleeping and soft off states is typically controlled by an operating system's power management software.
- the ACPI specification for example, describes component power states for various components resident on or responsive to a computing platform. These component power states include "C-states” for processing elements (e.g., a central processing unit (CPU)) and “D-states” for other components resident on or responsive to a computing platform. These other components are hereinafter referred to as “devices” and may include, but are not limited to, controllers, memory, peripherals, etc.
- the operating system's power management software places those idle processing elements in lower C-states.
- the higher the C- state the less power consumed by the processing element.
- a processing element in a C3 power state consumes less power than when the processing element is in a CO, Cl , or C2 power state.
- the operating system's power management software leaves most devices in a power state that consumes a significant amount of power. This is because, for example, inherent latency penalties caused when devices are transitioned by the operating system's power management software between high and lower power consuming D-states can be greater than the period of time the processing element is actually is in a lower power state, or device functionality required by OS (or end user) is lost when entering a lower power consuming D-state.
- a method includes initiating a power management policy based on a processing element for a computing platform entering a given power state.
- the power management policy is to include a determination as to whether an input/output (I/O) controller and a memory controller for the computing platform are substantially quiescent, e.g., a period of relatively no activity, network traffic, memory requests, etc.
- the computing platform may then be transitioned to a low power system state from a run power system state based on a determination that both the I/O controller and the memory controller are substantially quiescent and an indication that the computing platform is capable of entering the low power system state.
- the low power system state includes entering one or more devices responsive to the computing platform in a power level adequate to retain a configuration state that enables the one or more devices to transition back to the run power system state in a manner that is substantially transparent to an operating system for the computing platform.
- Fig. 1 is a block diagram of an example computing platform 100.
- Computing platform 100 includes, but is not limited to, a computing platform for a two-way radio communication system, a one-way pager, a two-way pager, a personal communication system, a personal computer (e.g., laptop, desktop, notebook, ultra-mobile, etc.), a work station, a server, a personal digital assistant (PDAs), a digital broadband telephony device, a portable music, video or game player.
- PDAs personal digital assistant
- computing platform 100 includes configuration controller 110, memory controller 120, memory 130, processing elements 140, input/output (I/O) controller 150, devices 160 and power circuitry 170. This disclosure is not limited to a computing platform that includes only these elements.
- configuration controller 110 includes logic that is depicted in Fig. 1 as configuration logic 112 and power state logic 115.
- Configuration logic 112 for example, facilitates the configuration of one or more devices responsive to computing platform 100 for operation on computing platform 100.
- Power state logic 115 for example, facilitates the transition of computing platform 100 between a run power system state and a low power system state.
- the run and low power system states are within the SO power state as described by the ACPI specification.
- transitions between run and low power system states may be substantially transparent to the operating system's power management software.
- the transitions may also be transparent to an end-use, e.g. display screen is unchanged, network connections remain activated, etc. This transparency, for example, provides a look and feel to the OS and/or the end user that computing platform 100 is fully on when it is actually in a low power system state.
- configuration controller 110 is maintained as a separate component resident on computing platform 100. But this disclosure is not limited to only this example of a separate configuration controller 110. Configuration controller 110, for example, may be integrated with other controllers or processing elements resident on computing platform 100 (e.g., in a firmware hub, manageability engine, chipset, system on a chip, etc.). [0010] In one implementation, memory controller 120 facilitates or controls memory transactions (e.g., read or write requests) to memory 130.
- Memory 130 for example, includes system memory that is used or accessible to devices and/or components resident on or responsive to computing platform 100, e.g., processing elements 140, devices 160, etc. This system memory, for example, includes one or more dynamic random access memory (DRAM) modules (not shown).
- DRAM dynamic random access memory
- memory controller 120 may be integrated with other components on computing platform 100.
- memory controller 120 may be integrated with processing elements 140.
- Memory controller 120 may also reside with other controllers (e.g., I/O controller 150 and/or configuration controller 110) in a cluster of other components (e.g., in a chipset) resident on computing platform 100.
- processing elements 140 represent any of a wide variety of logic device(s) or executable content to perform processing functions for computing platform 100, e.g., a central processing unit (CPU).
- Processing elements 140 may include one or more of a microprocessor, a network processor, a service processor, a microcontroller, one or more sequestered cores of a multi-core microprocessor or combination thereof.
- I/O controller 150 facilitates the control and management of devices 160 that are resident on or responsive to computing platform 100.
- Devices 160 include but are not limited to one or more devices such as a keyboard, mouse, internal/external storage drive, display, wired/wireless network hardware (NICs), etc. These devices may couple to I/O controller 150 through various types of buses or interconnects.
- NICs wired/wireless network hardware
- buses or interconnects may operate according to various industry standard interconnect communication protocols to include Universal Serial Bus (USB), Peripheral Component Interconnect (PCI), PCI Express (PCI-e), Smart Management Bus (SMBus), HyperTransport, Low Pin Count (LPC), Serial Advanced Technology Attachment (SATA) and Parallel Advanced Technology Attachment (PATA), High Definition Multimedia Interface (HDMI), etc.
- USB Universal Serial Bus
- PCI Peripheral Component Interconnect
- PCI-e PCI Express
- SMBs Smart Management Bus
- HyperTransport Low Pin Count
- LPC Low Pin Count
- SATA Serial Advanced Technology Attachment
- PATA Parallel Advanced Technology Attachment
- HDMI High Definition Multimedia Interface
- power circuitry 170 includes run power 172 and low power 174.
- run power 172 and low power 174 may each include voltage regulators, power switches, power feeds and clock generators as needed to maintain the higher and lower power states.
- Run power 172 for example, provides power to enable all components to operate at or near full operational capacity.
- Low power 174 for example, provides power adequate for devices on or responsive to computing platform 100 to retain their configuration states and yet enables those devices to transition back to the run power system state in a manner that is substantially transparent to the operating system's power management software. This disclosure is not limited to only run and lower power system states. Other levels of power may be provided to computing platform 100 by power circuitry 170 as computing platform 100 is transitioned between high and lower power system states
- Fig. 2 is an example block diagram of a portion of configuration controller 110 to include power state logic 115 to transition all or portions of computing platform 100 between high and lower power system states.
- configuration controller 110 also includes various interfaces and logic gates coupled to power state logic 115 to facilitate this transition of computing platform 100. These interfaces and logic gates are portrayed as C-state interface 220, low power policy interface 230, AND gate 240 and NOR gate 250.
- power state logic 115 and configuration logic 112 each or collectively represent any of a wide variety of logic device(s) or executable content to cause computing platform 100 to transition between a run and a low power system state.
- These logic device(s) may include a microprocessor, network processor, service processor, microcontroller, field programmable gate array (FPGA), application specific integrated circuit (ASIC), sequestered thread or core of a multi-core/multi-threaded microprocessor, special operating mode of a processor or a combination thereof.
- FPGA field programmable gate array
- ASIC application specific integrated circuit
- power state logic 115 includes c-state feature 205, memory 210 and low power enable feature 215.
- c-state feature 205, memory 210 and low power enable feature 215 are activated or used by power state logic 115 to initiate a power management policy.
- the power management policy for example, to cause computing platform 100 to transition between run and low power system states based on a C-state maintained by one or more processing elements of processing elements 140, substantially quiescent activity indications from I/O and memory controllers 150 and 120 and/or based on a wake signal via communication link 260.
- computing platform 100 implements C-state power management states for processing elements 140 as described in the ACPI specification.
- a processing element of processing elements 140 and/or operating system power management software for computing platform 100 may send an indication to configuration controller 110 as to what C- state that processing element is currently maintaining.
- C-state interface 220 may include a memory register of a given number of bits. These bits in C-state interface 220 may be selectively asserted to indicate the C-state maintained by one or more processing elements of processing elements 140. For example, if a given processing element transitions to a Cl power state, then the bits of the memory register are selectively asserted to indicate the given processing element is in the Cl power state. Power state logic 115, for example, may receive or access this indication via communication link 222.
- C-state interface 220 includes a one or more shift registers (not shown) coupled to communication link 222.
- Portions of a given shift register are associated with a given C-state for a given processing element of processing elements 140.
- the outputs of the associated portions of the shift register will indicate to power state logic 115 via communication link 222 what given C-state is currently being maintained by the given processing element.
- configuration controller 110 also includes low power policy interface 230.
- Low power policy interface 230 includes information to indicate a given C-state that computing platform 100 is enabled for transitioning from a run power system state to a low power system state.
- Low power policy interface 230 may also include information associated with requirements for one or more policies that are to be met before computing platform 100 is transitioned to a low power system state.
- low power policy interface 230 includes an 8-bit memory register that is maintained by configuration controller 110 and/or configuration logic 115. Lm this example, one or more bits of the memory register may be selectively asserted to indicate the given C-state that computing platform 100 is enabled for transitioning from a run power system state to a low power system state (if enabled at all) and may also indicate requirements for that transition.
- at least a portion of a power management policy includes requirements associated with guidance provided from an OS and/or its power management software via low power policy interface 230.
- the OS may selectively assert one or more bits of a memory register included in low power policy interface 230 to provide that guidance.
- the guidance may indicate to power state logic 115 such information as an expected duration for a given C-state and the threshold time values associated with maximum allowed latencies for transparently transitioning a computing platform between run and low power system states when a given processing element is in the given C- state.
- power state logic 115 causes computing platform 100 to transition between run and low power system states in a substantially transparent manner to the operating system.
- c-state interface 220 serves as more of a hardware- based interface that includes memory registers or shift registers for power state logic 115 to gather information to determine whether to transition computing platform 100 to a low power system state.
- low power policy interface 230 serves as more of a software-based interface that may or may not rely on hardware- based components such as memory registers.
- Low power policy interface 230 serves as a more flexible interface that allows for greater interaction between power logic 115 and elements resident on or remote to computing platform 100. These elements may include an OS for computing platform 100.
- configuration controller 110 includes AND gate 240.
- AND gate 240 receives inputs from memory controller 120 and I/O controller 150.
- these inputs are indications of substantial inactivity or quiescence at memory controller 120 and I/O controller 150.
- Substantially quiescent activity at I/O controller 150 is based on very little of no activity or traffic over one or more buses and/or interconnects coupled between I/O controller 150 and devices 160.
- Substantially quiescent activity at memory controller 120 includes the draining of practically all outstanding memory transaction requests to memory 130. This disclosure is not limited to only these indications of substantially quiescent activity and is not limited to only an AND logic gate to receive these inputs.
- configuration controller 110 also includes NOR gate 250.
- NOR gate 250 receives an input signal via communication link 217 and produces an output that is sent to run power 172 of power circuitry 170. In one implementation, if no signal is received from low power enable feature 215, then a signal is sent to run power 172.
- This signal indicates to run power 172 that it is to provide computing platform 100 with adequate power to maintain a run power system state (e.g., SO run power system state).
- a run power system state e.g., SO run power system state
- the output signal from NOR gate 250 is cut off or gated.
- a signal is then sent to low power 174 to provide computing platform 100 with low power.
- a signal is also sent, for example, to memory controller 120 to indicate to memory controller 120 to place at least portions of memory 130 (e.g., DRAM modules) in a low power self-refresh state.
- This disclosure is not limited to only a NOR logic gate to receive an input signal via communication link 217.
- communication link 260 may be used to provide a wake signal.
- the wake signal provides an indication for power state logic 115 to cause computing platform 100 to transition out of the low power system state and back to the run power system state.
- Fig. 3 is an example flow diagram 300 of computing platform 100 transitioning to and from various power states.
- flow diagram 300 depicts computing platform transitioning between working (SO), sleeping (S3 and S4) and soft off (S5) power states. At least a portion of these working, sleeping and soft off states may be the same S-states described in the ACPI specification and are characterized, for example, as involving computing platform 100's operating system's power management software.
- Also depicted in flow diagram 300 are three different power system states within the SO working power state (Run, Idle and Standby). Computing platform 100, for example may transition between these power states without the involvement of or substantially transparent to the operating system's power management software and also possibly transparent to an end user.
- state 310 for example, computing platform 100 is in a run power system system state. In this state, for example, processing elements 140 are in a fully operational or a CO power state as described by the ACPI specification. From state 310, for example, computing platform 100 may transition to various other power states as depicted in flow diagram 300.
- Those involving the operating system's power management software to transition in and out of the various power states are the S3 sleep (S3_sleep) state at state 340, the S4 hibernate (S4_Hib) state at state 350 and the S5 off (S5_off) state at state 360.
- Those states not involving the operating system's power management software or substantially transparent to the software are the SO idle (S0_idle) state at state 320 and the SO standby (SO_standby) state at state 330.
- computing platform 100 may transition to state 310 from state 320 or 330 based on a wake event. These wake events and states 310, 320 and 330 are described in more detail below for Fig. 4.
- Fig. 4 is a flow chart of an example method to transition computing platform 100 between a run and a low power system state.
- the run and low power system states are part of the working SO power state.
- the SO power state also includes an intermediary idle power state (S0_Idle).
- processing elements 140 may transition in and out of various power states. Such as, for example, the C-state power consumption levels described in the ACPI specification.
- S0_Idle may represent all or a portion of processing elements 140 in a given low power state (e.g., a C-state of Cl or higher).
- power state logic 115 obtains low power policy information from low power policy interface 230.
- the low power policy information obtained from low power policy interface 230 may be at least temporarily stored in a memory responsive to power state logic 215 (e.g., memory 210).
- power state logic 115 activates low power enable feature 215.
- Low power enable feature 215, determines whether computing platform 100 is capable of entering the low power system state. This determination, for example, is based on the low power policy information obtained from low power policy interface 230. That information may indicate whether computing platform 100 is capable of providing power to maintain a run and a low power system state, e.g., has the appropriate power circuitry.
- ⁇ low power policy interface 230 indicates that computing platform 100 is not capable of providing power to maintain a run and a low power system state. In this example, since computing platform 100 is unable to transition to the low power system state, the process is aborted.
- power state logic 215 activates c-state feature 205.
- c-state feature 205 determines whether one or more processing elements of processing elements 140 have indicated entering a given C-state by querying C-state interface 220.
- C-state feature 205 determines at what given C-state it is to initiate a power management policy for computing platform 100. This determination, for example, is based on the low power policy information obtained from low power policy interface 230. That information, for example, may indicate to c-state feature 205 that the given C-state is the C6 power state.
- the given C-state or power state is the power state at which a given processing element is consuming its lowest amount of power.
- the C6 power state is the lowest power state processing elements 140 may enter, hi other examples, the given C-state or power state may be any other power state that is consuming less power than when the one or more processing elements of processing elements 140 are in a fully operational CO power state, hi these other examples, the given C-state is not necessarily the lowest power consuming C-state.
- c-state feature 205 has determined that the given processing element has entered the given c-state. C-state feature 205 based on that determination, for example, initiates the power management policy for computing platform 100.
- low power enable feature 215 accesses the low power policy information obtained from low power policy interface 230 and stored in the memory responsive to power state logic 215.
- the low power policy information includes one or more requirements that should be met before transitioning computing platform 100 to a low power state.
- a requirement includes a given threshold time value for low power enable feature 215 to wait before transitioning computing platform 100 to a low power system state based on the given processing element entering the given C-state.
- This information may also include guidance provided from an OS for computing platform 100 (e.g., via low power policy interface 230). This OS-provided guidance may include information about the expected duration for the given C-state that the given processing element has entered.
- the OS-provided guidance may also include transition timing values associated with meeting latency requirements to transparently transition computing platform between run and low power system states.
- the low power policy information may also include conditional requirements that base a transition on given conditions, e.g., number of transitions in a given period of time.
- c-state feature 215 monitors the initiated timer or tracks the age of the timestamp to determine the amount of time the given processing element has been in the given c-state.
- the requirement which includes a given threshold time value for low power enable feature 215 to wait before transitioning computing platform 100 to a low power system state based on the given processing element entering the given C-state has been met.
- another portion of the power management policy may include a requirement associated with the OS-provided guidance.
- another portion of the power management policy may include guidance to not transition computing platform 100 into a low power system state if certain conditions are met. These conditions may include a given threshold number for a number of instances in a given time period that computing platform 100 has been transitioned in an out of a low power system state. This guidance, for example, may be based on the costs (e.g., latencies and/or performance) of rapidly transitioning computing platform 100 in and out of the low power system state exceeding the benefits (power saving) after the threshold number is reached for a given time period.
- power enable feature 215 maintains a count of the number of times computing platform 100 is transitioned in a given period. If the count does not exceed the threshold number, the requirement associated with the conditional guidance has been met.
- the process may return to block 420 or to block 435.
- the process returns to block 420, for example, if the OS-provided guidance or the conditional guidance requirements are not met.
- the process returns to block 435, for example, if only the timer requirement is not met.
- low power enable feature 215 has determined that one or more requirements included in the power management policy information have been met.
- Low power enable feature 215, for example, determines whether memory controller 120 and I/O controller 150 for computing platform are substantially quiescent (in a period of inactivity). As mentioned above, the output from AND gate 240 will signal quiescence via communication link 242 if both memory controller 120 and I/O controller 150 have indicated they are substantially quiescent.
- low power enable feature 215 has determined that the one or more requirements have been met and memory controller 120 and VO controller 150 are substantially quiescent. Based on this, low power enable feature 215, in one implementation, asserts a signal over communication link 217. This signal assertion, for example, sends a signal to memory controller 120 to transition at least portions of memory 130 to a self-refresh mode and also sends a signal to low power 174 to provide low power to computing platform 100. Also, for example, the asserted input to NOR gate 250 results in an output that is de-asserted and indicates to run power 172 to not provide, disable or shut off run power to computing platform 100.
- low power enable feature 215 determines whether a wake event has occurred to cause computing platform 100 to transition out of the low power system state.
- a wake event may include a wake signal received via communication link 260, an indication that memory controller 120 and I/O controller 150 are no longer substantially quiescent or the given processing element is no longer in the given C-state.
- a wake event may also be based on a requirement included in a power management policy that places a limit on an amount of time that computing platform 100 can be in a low power system state. This limit, for example, is based on OS-provided guidance associated with transition timing values for meeting latency requirements to transparently transition computing platform 100 between run and low power system states.
- low power enable feature 215 determines that a wake event has occurred.
- Computing platform 100 for example, is then transitioned back to the run power system state.
- low power 274 is disabled and run power 272 is enabled.
- memory controller 120 transitions those portions of memory 130 placed in a self-refresh mode back to an active mode.
- the method for example, then returns to block 420 to determine if or when one or more processing elements of processing elements 140 again enter a given C-state. Alternatively, although not shown in Fig. 4, the method may return to block 405.
- Fig. 4 depicts a given sequence of actions taken to transition a computing platform from a run to a low power system state
- this disclosure is not limited to this particular sequence or order of actions.
- This disclosure may also include a sequence of actions that includes more or less actions as depicted and described for Fig. 4.
- memory 130 and memory 210 may include a wide variety of memory media including but not limited to volatile memory, non-volatile memory, flash, programmable variables or states, random access memory (RAM), read-only memory (ROM), flash, or other static or dynamic storage media.
- machine-readable instructions can be provided to memory 130 and/or memory 210 from a form of machine-accessible medium.
- a machine-accessible medium may represent any mechanism that provides (i.e., stores and/or transmits) information or content in a form readable by a machine (e.g., an ASIC, special function controller or processor, FPGA, device, computing platform or other hardware device).
- a machine-accessible medium may include a computer readable medium that includes: ROM; RAM; magnetic disk storage media; optical storage media; flash memory devices.
- the machine-accessible medium may also include a communication medium that includes: electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals) and the like.
- references made in the specification to the term “responsive to” are not limited to responsiveness to only a particular feature and/or structure.
- a feature may also be “responsive to” an other feature and/or structure and also be located within that feature and/or structure.
- the term “responsive to” may also be synonymous with other terms such as “communicatively coupled to” or “operatively coupled to,” although the term is not limited in this regard.
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DE112007001987T DE112007001987B4 (en) | 2006-09-29 | 2007-09-25 | Transferring a computing platform into a low power system state |
CN200780035771.2A CN101517510B (en) | 2006-09-29 | 2007-09-25 | Transitioning a computing platform to a low power system state |
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US11/541,222 US7849334B2 (en) | 2006-09-29 | 2006-09-29 | Transitioning a computing platform to a low power system state |
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Also Published As
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TWI386791B (en) | 2013-02-21 |
CN101517510B (en) | 2013-03-13 |
US7849334B2 (en) | 2010-12-07 |
DE112007001987B4 (en) | 2013-05-16 |
CN101517510A (en) | 2009-08-26 |
TW200825706A (en) | 2008-06-16 |
US20110078475A1 (en) | 2011-03-31 |
US20080082841A1 (en) | 2008-04-03 |
DE112007001987T5 (en) | 2010-01-07 |
US8527785B2 (en) | 2013-09-03 |
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