WO2008093947A1 - Dual edge access nand flash memory - Google Patents

Dual edge access nand flash memory Download PDF

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Publication number
WO2008093947A1
WO2008093947A1 PCT/KR2008/000309 KR2008000309W WO2008093947A1 WO 2008093947 A1 WO2008093947 A1 WO 2008093947A1 KR 2008000309 W KR2008000309 W KR 2008000309W WO 2008093947 A1 WO2008093947 A1 WO 2008093947A1
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WO
WIPO (PCT)
Prior art keywords
output
input
data
nand flash
buffers
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Application number
PCT/KR2008/000309
Other languages
French (fr)
Inventor
Un Sik Seo
Original Assignee
Mgine Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Mgine Co., Ltd. filed Critical Mgine Co., Ltd.
Publication of WO2008093947A1 publication Critical patent/WO2008093947A1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits

Definitions

  • the present invention relates to a dual edge accessible NAND flash memory and more particularly, to a dual edge accessible NAND flash memory, in that each buffer related to a data input/output with a NAND flash cell array is divided into odd and even buffers and the data of the odd and even buffers is alternately inputted or outputted from both edges of the rising and falling of signals received from a host, whereby remarkably increasing the efficiency of the data transmittance thereof.
  • a flash memory is a kind of a writable memory having a nonvolatility capable of preserving a write-once information without supply of a power like a ROM (Read Only Memory).
  • the flash memory can be divided into a NOR flash memory having a cell arranged in parellel between a bit line and a grounding line and a AND flash memory arranged in series between them.
  • the NOR flash memory is a kind of a device capable of reading and writing an arbitrary address by a bite unit through a random access without order of the cell.
  • it is necessary to electrically connect each cell to the contact electrodes of the bit line there is a problem in that the area of the cell becomes large in comparison with the serial type flash memory.
  • block means a kind of a unit capable of deleting through a deleting-once operation
  • page means a size of data capable of reading and writing during read/write operation.
  • FIG. 1 is a circuit diagram illustrating a conventional NAND flash memory
  • FIG. 2 and FIG 3 illustrate a read timing and a write timing of the conventional NAND flash memory.
  • the conventional NAND flash memory includes a NAND flash cell array 1, a control logic 2, an input/output buffer 3, a global buffer 4, and an output buffer 5.
  • the NAND flash cell array 1 is connected to the input/output buffer 3.
  • the NAND flash cell array 1 includes a plurality memory cell strings having flash memory cells and serves to record the data.
  • the global buffer 4 is connected between the input/output bus and the input/output buffer 3 and temporarily stores an input data received from the input/output bus and then, transmit it to the input/output buffer 3.
  • the output buffer 5 is connected between the input/output buffer 3 and the input/ output bus and temporarily stores an output data received from the input/output buffer 3 and then, transmit it to the input/output bus.
  • the control logic 2 is electrically connected to each configuration and transmits the control signals corresponding to any signals received from the host to each configuration, thereby controlling the operation of each configuration.
  • NAND flash memory will be described in detail below.
  • control logic 2 allows control signals for controlling the read operation to be applied to the input/output buffer 3 and the output buffer 5, thereby driving each buffer.
  • the input/output buffer 3 serves to temporarily store the output data outputted from the NAND flash cell array 1 and then, transmit it to the output buffer 5.
  • the output data transmitted from the input/output buffer 3 is temporarily stored in the output buffer 5 and then, transmitted to the host through the input/output bus.
  • the control logic 2 allows control signals for controlling the write operation to be applied to the global buffer 4 and the input/output buffer 3, thereby driving each buffer.
  • the global buffer 4 serves to temporarily store the input data outputted from the host through the input/output bus and then, transmit it to the input/output buffer 3.
  • the input data transmitted from the global buffer 4 is temporarily stored in the input/output buffer 3 and then transmitted to the NAND flash cell array 1, thereby recording the input data in a predetermined area of the NAND flash cell array 1.
  • the input of the data (Din) starts in the falling edge of the write enable signal.
  • an object of the present invention is to provide a dual edge accessible NAND flash memory, in that operations of the read and write are performed from both edges of the rising and falling of the read and write enable signals received from a host, whereby remarkably increasing the efficiency of the data transmittance thereof.
  • Another object of the present invention is to provide a dual edge accessible NAND flash memory, in that input/output buffers are divided into multiple bits therein, global and output buffers are connected to the multiple bits, and each configuration is synchronized with clocks, thereby remarkably increasing the speed of input and output between the buffers.
  • the present invention provides an input/output circuit of a dual edge accessible NAND flash memory comprising: first and second global buffers operated in rising and falling edges of a read control signal received from a host respectively so as to temporarily stores a writing data; first and second output buffers operated in rising and falling edges of a write control signal received from the host respectively so as to temporarily stores a reading data; first and second odd input/ output buffers operated in the rising and falling edges of the read control signal received from the host respectively so as to transmit data read from a NAND flash cell array to the first and second output buffers respectively and operated in the rising and falling edges of the write control signal received from the host respectively so as to transmit the data stored temporarily in the first and second global buffers to the NAND flash cell array; and a control logic for transmitting control signals corresponding to any signals received from the host to each configuration, thereby controlling an operation of each configuration.
  • the input/output circuit of the dual edge accessible NAND flash memory further comprises a multiplexer connected to output terminals of the first and second output buffers so as to selectively output an output data of the first output buffer in the rising edge of the read control signal and selectively output other output data of the second output buffer in the falling edge of the read control signal and a demultiplexer connected to input terminals of the first and second global buffers so as to selectively output an input data to the input terminal of the first global buffer in the rising edge of the write control signal and selectively output other input data to the input terminal of the second global buffer in the falling edge of the write control signal.
  • the present invention provides an input/output circuit of a dual edge accessible NAND flash memory comprising: first and second global buffers driven through a read control signal received from a host and operated in rising and falling edges of a synchronization clock received from the host respectively so as to temporarily stores a writing data; first and second output buffers driven through a write control signal received from the host and operated in rising and falling edges of the synchronization clock received from the host respectively so as to temporarily stores a reading data; first and second odd input/output buffers driven through the read control signal received from the host and operated in the rising and falling edges of the synchronization clock received from the host respectively so as to transmit data read from a NAND flash cell array to the first and second output buffers respectively and operated in the rising and falling edges of the synchronization clock received from the host respectively so as to transmit the data stored temporarily in the first and second global buffers to the NAND flash cell array; and a control logic for transmitting control signals corresponding to any signals received from the host to each configuration, thereby controlling an
  • the input/output circuit of the dual edge accessible NAND flash memory further comprises a multiplexer connected to output terminals of the first and second output buffers so as to selectively output an output data of the first output buffer in the rising edge of the synchronization clock and selectively output other output data of the second output buffer in the falling edge of the read control signal and a demultiplexer connected to input terminals of the first and second global buffers so as to selectively output an input data to the input terminal of the first global buffer in the rising edge of the synchronization clock and selectively output other input data to the input terminal of the second global buffer in the falling edge of the write control signal.
  • the first and input/output buffers are divided into multiple bits therein, the first and second global buffers and the first and second output buffers connected to the multiple bits, and each area of the divided multiple bits is synchronized with the synchronization clock, thereby storing and outputting the data.
  • the operations of the read and write are performed from both edges of the rising and falling of the read and write enable signals received from the host, whereby remarkably increasing the efficiency of the data transmittance thereof.
  • the input/output buffers are divided into multiple bits therein, the global and output buffers are connected to the multiple bits, and each configuration is synchronized with the clocks, thereby remarkably increasing the speed of input and output between the buffers.
  • FIG. 1 is a circuit diagram illustrating a conventional NAND flash memory
  • FIG. 2 illustrates a read timing of the conventional NAND flash memory
  • FIG 3 illustrates a write timing of the conventional NAND flash memory
  • FIG. 4 is a circuit diagram illustrating a NAND flash memory according to one embodiment of the present invention.
  • FIG. 5 illustrates a read timing of the NAND flash memory according to one embodiment of the present invention
  • FIG 6 illustrates a write timing of the NAND flash memory according to one embodiment of the present invention
  • FIG. 7 is a circuit diagram illustrating a NAND flash memory according to another embodiment of the present invention
  • FIG. 8 illustrates a read timing of the NAND flash memory according to another embodiment of the present invention
  • FIG 9 illustrates a write timing of the NAND flash memory according to another embodiment of the present invention
  • FIG. 10 is a schematic diagram illustrating an operation status of data input/output among buffers of a NAND flash memory according to further another embodiment of the present invention
  • FIG. 11 is a schematic diagram illustrating an application example of a NAND flash memory according to further another embodiment of the present invention.
  • FIG. 4 is a circuit diagram illustrating a NAND flash memory according to one embodiment of the present invention and FIG. 5 and FIG 6 illustrate a read timing and a write timing of the NAND flash memory according to one embodiment of the present invention respectively.
  • the NAND flash memory according to one embodiment of the present invention includes a NAND flash cell array 10, a control logic 20, odd and even input/output buffers 31 and 33, odd and even global buffers 41 and 43, odd and even output buffers 51 and 53, a multiplexer 60, and a demultiplexer 70.
  • the NAND flash cell array 10 is connected to the odd and even input/output buffers
  • the NAND flash cell array 10 includes a plurality memory cell strings having flash memory cells and serves to record the data.
  • the control logic 20 serves to drive the odd buffers 31, 41 and 51 from the falling edge of the read enable signal(
  • the odd global buffer 41 is connected between the demultiplexer 70 and the odd input/output buffer 31 and operated in the rising edge of the write enable signal through the control of the control logic 20, so that it serves to temporarily stores an odd input data received from the demultiplexer 70 and then, transmit it to the odd input/ output buffer 31.
  • the even global buffer 43 is connected between the demultiplexer 70 and the even input/output buffer 33 and operated in the falling edge of the write enable signal through the control of the control logic 20, so that it serves to temporarily stores an even input data received from the demultiplexer 70 and then, transmit it to the even input/output buffer 33.
  • the odd output buffer 51 is connected between the multiplexer 60 and the odd input/output buffer 31 and operated in the rising edge of the read enable signal through the control of the control logic 20, so that it serves to temporarily stores an odd output data received from the odd input/output buffer 31 and then, transmit it to the multiplexer 60.
  • the even output buffer 53 is connected between the multiplexer 60 and the even input/output buffer 33 and operated in the falling edge of the read enable signal through the control of the control logic 20, so that it serves to temporarily stores an odd output data received from the even input/output buffer 33 and then, transmit it to the multiplexer 60.
  • the even input/output buffer 33 is connected among the NAND flash cell array 10, the even global buffer 43, and the even output buffer 53.
  • the even input/output buffer 33 serves to temporarily stores the even input data received from the even global buffer 43 in the falling edge of the write enable signal and then, transmit it to the NAND flash cell array 10 and transmit the even output data outputted from the NAND flash cell array 10 in the falling edge of the write enable signal to the even output buffer 53.
  • the multiplexer 60 connected to output terminals of the odd and even output buffers 51 and 53 serves to selectively output one signal among a plurality of input signals.
  • the multiplexer 60 serves to selectively output the odd output data of the odd output buffer 51 in the rising edge of the read enable signal and serves to selectively output the even output data of the even output buffer 53 in the falling edge of the read enable signal.
  • the demultiplexer 70 connected to input terminals of the odd and even global buffers 41 and 43 serves to selectively transmit the inputting signals to one output among the plurality of outputs.
  • the demultiplexer 70 serves to selectively output the odd input data to the input terminal of the odd global buffer 41 in the rising edge of the write enable signal and serves to selectively output the even input data to the input terminal of the even global buffer 43 in the falling edge of the write enable signal.
  • the read and write operations of the input/output circuits of the NAND flash memory according to one embodiment of the present invention will be described in detail below. [72]
  • the control logic allows control signals for controlling the read operation to be applied to the odd and even input/output buffers 31 and 33 and the odd and even output buffers 51 and 53, thereby driving each buffer.
  • the even input/output buffer 33 and the even output buffer 53 are driven through the control of the control logic 20 in the falling edge of the read enable signal.
  • the even input/output buffer 33 serves to temporarily store the even output data outputted from the NAND flash cell array 10 and then, transmit it to the even output buffer 53.
  • the even output data transmitted to the even output buffer 53 is transmitted to the multiplexer 60 and then, selectively outputted through the multiplexer 60, so that it is transmitted to a host through an input/output bus.
  • the odd input/output buffer 31 and the odd output buffer 51 are driven through the control of the control logic 20 in the rising edge of the read enable signal.
  • the odd output data is transmitted to the multiplexer 60 via the odd input/ output buffer 31 and the odd output buffer 51.
  • the transmitted odd output data is selectively outputted through the multiplexer 60, so that it is transmitted to the host through the input/output bus.
  • the output of the even data (Deout) starts in the falling edge of the read enable signal and the output of the odd data (Doout) starts in the rising edge of the read enable signal.
  • control logic 20 controls the control logic 20 to control the control logic 20, the control logic allows control signals for controlling the write operation to be applied to the odd and even global buffers 41 and
  • the even global buffer 43 and the even input/output buffer 33 are driven through the control of the control logic 20 in the falling edge of the write enable signal.
  • the even global buffer 43 serves to temporarily store the even input data transmitted selectively from the demultiplexer 70 and then, transmit it to the even input/output buffer 33.
  • the even input/output buffer 33 serves to temporarily store the received even input data and then, transmit it to the NAND flash cell array 10, thereby recording the even input data in a predetermined area of the NAND flash cell array 10.
  • FIG 9 illustrate a read timing and a write timing of the NAND flash memory according to another embodiment of the present invention respectively.
  • the read and write operations are performed in the rising edge and the falling edge of the read enable signal(
  • clock signals which are not used in the conventional NAND flash memory, are applied to each circuit configuration, so that each circuit configuration is synchronized with the inputted clocks, thereby performing the operations of the read and write thereof.
  • clock signals are inputted to each buffer 31, 33, 41, 43, 51, and
  • each buffer 31, 33, 41, 43, 51, and 53 is synchronized with the clocks, thereby being operated in the rising and falling edges of each clock.
  • control logic 20 In the read operation, if the chip enable signal and the read enable signal are inputted to the control logic 20, the control logic 20 allows control signals for controlling the read operation to be applied to the odd and even input/output buffers 31 and 33 and the odd and even output buffers 51 and 53, thereby driving each buffer.
  • the odd input/output buffer 31 and the odd output buffer 51 are driven in the rising edge of the clocks inputted to each buffer, so that the odd output data is outputted to the multiplexer 60 and then, is transmitted to the host via the input/output bus.
  • the even input/output buffer 33 and the even output buffer 53 are driven in the falling edge of the clock inputted to each buffer, so that the even output data transmitted to the host.
  • the control logic 20 allows control signals for controlling the read operation to be applied to the odd and even global buffers 41 and 43 and the odd and even input/output buffers 31 and 33, thereby driving each buffer.
  • the odd global buffer 41 and the odd input/output buffer 31 are driven in the rising edge of the inputted clocks, so that the odd input data transmitted selectively from the demultiplexer 70 is transmitted to the NAND flash cell array 10, thereby recording the odd input data in a predetermined area of the NAND flash cell array 10.
  • the even global buffer 43 and the even input/output buffer 33 are driven in the falling edge of the inputted clocks, so that the even input data is recorded in a predetermined area of the NAND flash cell array 10.
  • FIG. 10 is a schematic diagram illustrating an operation status of data input/output among buffers of a NAND flash memory according to further another embodiment of the present invention.
  • the input/output buffers 31 and 33 are divided into multiple bits therein and the NAND flash cell array 10, the odd and even global buffers 41 and 43 and the odd and even output buffers 51 and 53 are connected to the multiple bits.
  • each configuration is synchronized with the inputted clocks, thereby performing the operations of the read and write thereof.
  • each configuration is synchronized with the inputted clocks, so that each data is transmitted to the multiple bits of the input/output buffers 31 and 33 in a row through the global buffers 41 and 43, and then, they are transmitted to the NAND flash cell memory 10 in a row through the input/output buffers 31 and 33.
  • each configuration is synchronized with the inputted clocks, so that each data is transmitted to the multiple bits of the input/output buffers 31 and 33 in a row through the NAND flash cell memory 10, and then, they are transmitted to the output buffers 51 and 53 in a row through the input/output buffers 31 and 33.
  • FIG. 11 is a schematic diagram illustrating an application example of a NAND flash memory according to further another embodiment of the present invention.
  • a plurality of NAND flash memories 100 are electrically connected to the corresponding controller 200 connected to each other through a loop back clock circuit for clock synchronization.
  • each controller 200 is synchronized with the clocks and controls the corresponding NAND flash memory 100 at the necessary time, thereby sending and transmitting each data.
  • the present invention relates to a dual edge accessible NAND flash memory, in that each buffer related to a data input/output with a NAND flash cell array is divided into odd and even buffers and the data of the odd and even buffers is alternately inputted or outputted from both edges of the rising and falling of signals received from a host, whereby remarkably increasing the efficiency of the data transmittance thereof.

Abstract

Disclosed is a dual edge accessible NAND flash memory in that the operations of the read and write are performed from both edges of the rising and falling of the read and write enable signals received from the host, whereby remarkably increasing the efficiency of the data transmittance thereof. The input/output circuit of a dual edge accessible NAND flash memory comprises: odd and even global buffers operated in rising and falling edges of a read control signal received from a host respectively so as to temporarily stores a writing data; odd and even output buffers operated in rising and falling edges of a write control signal received from the host respectively so as to temporarily stores a reading data; odd and even input/output buffers operated in the rising and falling edges of the read control signal received from the host respectively so as to transmit data read from a NAND flash cell array to the odd and even output buffers respectively and operated in the rising and falling edges of the write control signal received from the host re¬ spectively so as to transmit the data stored temporarily in the odd and even global buffers to the NAND flash cell array; and a control logic for transmitting control signals corresponding to any signals received from the host to each configuration, thereby controlling an operation of each configuration.

Description

Description DUAL EDGE ACCESS NAND FLASH MEMORY
Technical Field
[1] The present invention relates to a dual edge accessible NAND flash memory and more particularly, to a dual edge accessible NAND flash memory, in that each buffer related to a data input/output with a NAND flash cell array is divided into odd and even buffers and the data of the odd and even buffers is alternately inputted or outputted from both edges of the rising and falling of signals received from a host, whereby remarkably increasing the efficiency of the data transmittance thereof. Background Art
[2] Generally, a flash memory is a kind of a writable memory having a nonvolatility capable of preserving a write-once information without supply of a power like a ROM (Read Only Memory). The flash memory can be divided into a NOR flash memory having a cell arranged in parellel between a bit line and a grounding line and a AND flash memory arranged in series between them.
[3] The NOR flash memory is a kind of a device capable of reading and writing an arbitrary address by a bite unit through a random access without order of the cell. However, since it is necessary to electrically connect each cell to the contact electrodes of the bit line, there is a problem in that the area of the cell becomes large in comparison with the serial type flash memory.
[4] In the meantime, the NAND flash memory is a kind of a block type device capable of selecting the corresponding block and then reading each cell connected to each other in series.
[5] Here, the term "block" means a kind of a unit capable of deleting through a deleting-once operation and the term "page" means a size of data capable of reading and writing during read/write operation.
[6] FIG. 1 is a circuit diagram illustrating a conventional NAND flash memory and
FIG. 2 and FIG 3 illustrate a read timing and a write timing of the conventional NAND flash memory.
[7] As shown in FIG. 1, the conventional NAND flash memory includes a NAND flash cell array 1, a control logic 2, an input/output buffer 3, a global buffer 4, and an output buffer 5.
[8] The NAND flash cell array 1 is connected to the input/output buffer 3. The NAND flash cell array 1 includes a plurality memory cell strings having flash memory cells and serves to record the data.
[9] As though it is not shown, a host serves to transmit each read and write enable signal during reading and writing thereof. Falling and rising edges are formed at the changed moment of the operation status in the read and write enable signals.
[10] The global buffer 4 is connected between the input/output bus and the input/output buffer 3 and temporarily stores an input data received from the input/output bus and then, transmit it to the input/output buffer 3.
[11] The output buffer 5 is connected between the input/output buffer 3 and the input/ output bus and temporarily stores an output data received from the input/output buffer 3 and then, transmit it to the input/output bus.
[12] The input/output buffer 3 is connected among the NAND flash cell array 1, the global buffer 4, and the output buffer 5. The input/output buffer 3 serves to transmit the data received from the NAND flash cell array 1 to the output buffer 5 during receiving of the read control signals from the control logic 2. Also, where the write control signals are received, it serves to transmit the data stored temporarily in the global buffer 4 to the NAND flash cell array 1.
[13] The control logic 2 is electrically connected to each configuration and transmits the control signals corresponding to any signals received from the host to each configuration, thereby controlling the operation of each configuration.
[14] The read and write operations of the input/output circuits of the conventional
NAND flash memory will be described in detail below.
[15]
[16] Read Operation
[17] Firstly, if the chip enable signal(
L K
) and the read enable signal( ϊi~E
) are inputted to the control logic 2, the control logic 2 allows control signals for controlling the read operation to be applied to the input/output buffer 3 and the output buffer 5, thereby driving each buffer.
[18] Here, the input/output buffer 3 serves to temporarily store the output data outputted from the NAND flash cell array 1 and then, transmit it to the output buffer 5.
[19] Then, the output data transmitted from the input/output buffer 3 is temporarily stored in the output buffer 5 and then, transmitted to the host through the input/output bus.
[20] As shown in FIG. 2, in the read operation, the output of the data (Dout) starts in the falling edge of the read enable signal.
[21]
[22] Write Operation
[23] Firstly, if the chip enable signal( ) and the write enable signal(
:v\~F.
) are inputted to the control logic 2, the control logic allows control signals for controlling the write operation to be applied to the global buffer 4 and the input/output buffer 3, thereby driving each buffer. [24] Here, the global buffer 4 serves to temporarily store the input data outputted from the host through the input/output bus and then, transmit it to the input/output buffer 3. [25] Then, the input data transmitted from the global buffer 4 is temporarily stored in the input/output buffer 3 and then transmitted to the NAND flash cell array 1, thereby recording the input data in a predetermined area of the NAND flash cell array 1. [26] As shown in FIG. 3, in the write operation, the input of the data (Din) starts in the falling edge of the write enable signal. [27] Since the conventional NAND flash memory has a low price and a high capacity in comparison with the NOR flash memory, it can be widely used for saving the data of high capacity. [28] However, there is a problem in that the speed of read and write operation is slow in comparison with other memory elements. [29] Especially, since processing capability of high-speed on high capacity data has been required in a modern information-oriented society, the necessity for solving such a problem is seriously gathering strength. [30]
Disclosure of Invention
Technical Problem
[31] It is, therefore, an object of the present invention is to provide a dual edge accessible NAND flash memory, in that operations of the read and write are performed from both edges of the rising and falling of the read and write enable signals received from a host, whereby remarkably increasing the efficiency of the data transmittance thereof.
[32] Another object of the present invention is to provide a dual edge accessible NAND flash memory, in that input/output buffers are divided into multiple bits therein, global and output buffers are connected to the multiple bits, and each configuration is synchronized with clocks, thereby remarkably increasing the speed of input and output between the buffers.
[33]
Technical Solution
[34] To accomplish the objects, the present invention provides an input/output circuit of a dual edge accessible NAND flash memory comprising: first and second global buffers operated in rising and falling edges of a read control signal received from a host respectively so as to temporarily stores a writing data; first and second output buffers operated in rising and falling edges of a write control signal received from the host respectively so as to temporarily stores a reading data; first and second odd input/ output buffers operated in the rising and falling edges of the read control signal received from the host respectively so as to transmit data read from a NAND flash cell array to the first and second output buffers respectively and operated in the rising and falling edges of the write control signal received from the host respectively so as to transmit the data stored temporarily in the first and second global buffers to the NAND flash cell array; and a control logic for transmitting control signals corresponding to any signals received from the host to each configuration, thereby controlling an operation of each configuration.
[35] Preferably, the input/output circuit of the dual edge accessible NAND flash memory further comprises a multiplexer connected to output terminals of the first and second output buffers so as to selectively output an output data of the first output buffer in the rising edge of the read control signal and selectively output other output data of the second output buffer in the falling edge of the read control signal and a demultiplexer connected to input terminals of the first and second global buffers so as to selectively output an input data to the input terminal of the first global buffer in the rising edge of the write control signal and selectively output other input data to the input terminal of the second global buffer in the falling edge of the write control signal.
[36] To accomplish the objects, the present invention provides an input/output circuit of a dual edge accessible NAND flash memory comprising: first and second global buffers driven through a read control signal received from a host and operated in rising and falling edges of a synchronization clock received from the host respectively so as to temporarily stores a writing data; first and second output buffers driven through a write control signal received from the host and operated in rising and falling edges of the synchronization clock received from the host respectively so as to temporarily stores a reading data; first and second odd input/output buffers driven through the read control signal received from the host and operated in the rising and falling edges of the synchronization clock received from the host respectively so as to transmit data read from a NAND flash cell array to the first and second output buffers respectively and operated in the rising and falling edges of the synchronization clock received from the host respectively so as to transmit the data stored temporarily in the first and second global buffers to the NAND flash cell array; and a control logic for transmitting control signals corresponding to any signals received from the host to each configuration, thereby controlling an operation of each configuration. [37] Preferably, the input/output circuit of the dual edge accessible NAND flash memory further comprises a multiplexer connected to output terminals of the first and second output buffers so as to selectively output an output data of the first output buffer in the rising edge of the synchronization clock and selectively output other output data of the second output buffer in the falling edge of the read control signal and a demultiplexer connected to input terminals of the first and second global buffers so as to selectively output an input data to the input terminal of the first global buffer in the rising edge of the synchronization clock and selectively output other input data to the input terminal of the second global buffer in the falling edge of the write control signal.
[38] Preferably, the first and input/output buffers are divided into multiple bits therein, the first and second global buffers and the first and second output buffers connected to the multiple bits, and each area of the divided multiple bits is synchronized with the synchronization clock, thereby storing and outputting the data.
[39]
Advantageous Effects
[40] As described above, according to the dual edge accessible NAND flash memory, the operations of the read and write are performed from both edges of the rising and falling of the read and write enable signals received from the host, whereby remarkably increasing the efficiency of the data transmittance thereof.
[41] Also, the input/output buffers are divided into multiple bits therein, the global and output buffers are connected to the multiple bits, and each configuration is synchronized with the clocks, thereby remarkably increasing the speed of input and output between the buffers.
[42]
Brief Description of the Drawings
[43] The above as well as the other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:
[44] FIG. 1 is a circuit diagram illustrating a conventional NAND flash memory;
[45] FIG. 2 illustrates a read timing of the conventional NAND flash memory;
[46] FIG 3 illustrates a write timing of the conventional NAND flash memory;
[47] FIG. 4 is a circuit diagram illustrating a NAND flash memory according to one embodiment of the present invention;
[48] FIG. 5 illustrates a read timing of the NAND flash memory according to one embodiment of the present invention;
[49] FIG 6 illustrates a write timing of the NAND flash memory according to one embodiment of the present invention; [50] FIG. 7 is a circuit diagram illustrating a NAND flash memory according to another embodiment of the present invention; [51] FIG. 8 illustrates a read timing of the NAND flash memory according to another embodiment of the present invention; [52] FIG 9 illustrates a write timing of the NAND flash memory according to another embodiment of the present invention; [53] FIG. 10 is a schematic diagram illustrating an operation status of data input/output among buffers of a NAND flash memory according to further another embodiment of the present invention; and [54] FIG. 11 is a schematic diagram illustrating an application example of a NAND flash memory according to further another embodiment of the present invention. [55]
Best Mode for Carrying Out the Invention
[56] A preferred embodiment of the invention will be described in detail below.
[57] FIG. 4 is a circuit diagram illustrating a NAND flash memory according to one embodiment of the present invention and FIG. 5 and FIG 6 illustrate a read timing and a write timing of the NAND flash memory according to one embodiment of the present invention respectively. [58] As shown in FIG. 4, the NAND flash memory according to one embodiment of the present invention includes a NAND flash cell array 10, a control logic 20, odd and even input/output buffers 31 and 33, odd and even global buffers 41 and 43, odd and even output buffers 51 and 53, a multiplexer 60, and a demultiplexer 70. [59] The NAND flash cell array 10 is connected to the odd and even input/output buffers
31 and 33. The NAND flash cell array 10 includes a plurality memory cell strings having flash memory cells and serves to record the data. [60] The control logic 20 serves to drive the odd buffers 31, 41 and 51 from the falling edge of the read enable signal(
ΪΪE
) and the write enable signal(
\\ ¥.
) and the even buffers 33, 43 and 53 from the falling edge of the read enable signal( ϊik
) and the write enable signal(
\\ ¥.
) respectively during operation of the read and write, thereby performing the operations of the read and write of the data from both edges of the rising and falling of the read and write enable signals. [61] The odd global buffer 41 is connected between the demultiplexer 70 and the odd input/output buffer 31 and operated in the rising edge of the write enable signal through the control of the control logic 20, so that it serves to temporarily stores an odd input data received from the demultiplexer 70 and then, transmit it to the odd input/ output buffer 31.
[62] The even global buffer 43 is connected between the demultiplexer 70 and the even input/output buffer 33 and operated in the falling edge of the write enable signal through the control of the control logic 20, so that it serves to temporarily stores an even input data received from the demultiplexer 70 and then, transmit it to the even input/output buffer 33.
[63] The odd output buffer 51 is connected between the multiplexer 60 and the odd input/output buffer 31 and operated in the rising edge of the read enable signal through the control of the control logic 20, so that it serves to temporarily stores an odd output data received from the odd input/output buffer 31 and then, transmit it to the multiplexer 60.
[64] The even output buffer 53 is connected between the multiplexer 60 and the even input/output buffer 33 and operated in the falling edge of the read enable signal through the control of the control logic 20, so that it serves to temporarily stores an odd output data received from the even input/output buffer 33 and then, transmit it to the multiplexer 60.
[65] The odd input/output buffer 31 is connected among the NAND flash cell array 10, the odd global buffer 41, and the odd output buffer 51. The odd input/output buffer 31 serves to temporarily stores the odd input data received from the odd global buffer 41 in the rising edge of the write enable signal and then, transmit it to the NAND flash cell array 10 and transmit the odd output data read and outputted through the NAND flash cell array 10 in the rising edge of the read enable signal to the odd output buffer 51.
[66] The even input/output buffer 33 is connected among the NAND flash cell array 10, the even global buffer 43, and the even output buffer 53. The even input/output buffer 33 serves to temporarily stores the even input data received from the even global buffer 43 in the falling edge of the write enable signal and then, transmit it to the NAND flash cell array 10 and transmit the even output data outputted from the NAND flash cell array 10 in the falling edge of the write enable signal to the even output buffer 53.
[67] The multiplexer 60 connected to output terminals of the odd and even output buffers 51 and 53 serves to selectively output one signal among a plurality of input signals.
[68] Also, the multiplexer 60 serves to selectively output the odd output data of the odd output buffer 51 in the rising edge of the read enable signal and serves to selectively output the even output data of the even output buffer 53 in the falling edge of the read enable signal. [69] The demultiplexer 70 connected to input terminals of the odd and even global buffers 41 and 43 serves to selectively transmit the inputting signals to one output among the plurality of outputs. [70] Also, the demultiplexer 70 serves to selectively output the odd input data to the input terminal of the odd global buffer 41 in the rising edge of the write enable signal and serves to selectively output the even input data to the input terminal of the even global buffer 43 in the falling edge of the write enable signal. [71] The read and write operations of the input/output circuits of the NAND flash memory according to one embodiment of the present invention will be described in detail below. [72]
[73] Read Operation
[74] Firstly, if the chip enable signal(
) and the read enable signal(
ΪΪE
) are inputted to the control logic 20, the control logic allows control signals for controlling the read operation to be applied to the odd and even input/output buffers 31 and 33 and the odd and even output buffers 51 and 53, thereby driving each buffer. [75] Continuously, the even input/output buffer 33 and the even output buffer 53 are driven through the control of the control logic 20 in the falling edge of the read enable signal. Also, the even input/output buffer 33 serves to temporarily store the even output data outputted from the NAND flash cell array 10 and then, transmit it to the even output buffer 53. [76] Then, the even output data transmitted to the even output buffer 53 is transmitted to the multiplexer 60 and then, selectively outputted through the multiplexer 60, so that it is transmitted to a host through an input/output bus. [77] On the contrary, the odd input/output buffer 31 and the odd output buffer 51 are driven through the control of the control logic 20 in the rising edge of the read enable signal. Also, the odd output data is transmitted to the multiplexer 60 via the odd input/ output buffer 31 and the odd output buffer 51. [78] Moreover, the transmitted odd output data is selectively outputted through the multiplexer 60, so that it is transmitted to the host through the input/output bus. [79] As shown in FIG. 5, in the read operation, the output of the even data (Deout) starts in the falling edge of the read enable signal and the output of the odd data (Doout) starts in the rising edge of the read enable signal. [80]
[81] Write Operation
[82] Firstly, if the chip enable signal(
L K
) and the write enable signal(
\\ ¥.
) are inputted to the control logic 20, the control logic allows control signals for controlling the write operation to be applied to the odd and even global buffers 41 and
43 and the odd and even input/output buffers 31 and 33, thereby driving each buffer. [83] Continuously, the even global buffer 43 and the even input/output buffer 33 are driven through the control of the control logic 20 in the falling edge of the write enable signal. At this time, the even global buffer 43 serves to temporarily store the even input data transmitted selectively from the demultiplexer 70 and then, transmit it to the even input/output buffer 33. [84] The even input/output buffer 33 serves to temporarily store the received even input data and then, transmit it to the NAND flash cell array 10, thereby recording the even input data in a predetermined area of the NAND flash cell array 10. [85] On the contrary, the odd global buffer 41 and the odd input/output buffer 31 are driven through the control of the control logic 20 in the rising edge of the write enable signal. Also, the odd input data transmitted selectively from the demultiplexer 70 is transmitted to the NAND flash cell array 10 via the odd global buffer 41 and the odd input/output buffer 31, thereby recording the odd input data in a predetermined area of the NAND flash cell array 10. [86] As shown in FIG. 6, in the write operation, the input of the even data (Dein) starts in the falling edge of the write enable signal and the input of the odd data (Doin) starts in the rising edge of the write enable signal. [87] FIG. 7 is a circuit diagram illustrating a NAND flash memory according to another embodiment of the present invention and FIG. 8 and FIG 9 illustrate a read timing and a write timing of the NAND flash memory according to another embodiment of the present invention respectively. [88] Generally, in the circuit of the NAND flash memory, the read and write operations are performed in the rising edge and the falling edge of the read enable signal(
U~E
) and the write enable signal(
\\ T.
) transmitted from the host. [89] Meanwhile, in each circuit configuration of the NAND flash memory according to another embodiment of the present invention, clock signals, which are not used in the conventional NAND flash memory, are applied to each circuit configuration, so that each circuit configuration is synchronized with the inputted clocks, thereby performing the operations of the read and write thereof.
[90] As shown in FIG. 7, clock signals are inputted to each buffer 31, 33, 41, 43, 51, and
53, the multiplexer 60, and the demultiplexer 70.
[91] That is, the read and write operations start through the chip enable signal(
L K
) and the read enable signal( ΪΪE
) and the write enable signal( \\ ¥.
) transmitted from the host and each buffer 31, 33, 41, 43, 51, and 53 is synchronized with the clocks, thereby being operated in the rising and falling edges of each clock.
[92] In the read operation, if the chip enable signal and the read enable signal are inputted to the control logic 20, the control logic 20 allows control signals for controlling the read operation to be applied to the odd and even input/output buffers 31 and 33 and the odd and even output buffers 51 and 53, thereby driving each buffer.
[93] Here, the odd input/output buffer 31 and the odd output buffer 51 are driven in the rising edge of the clocks inputted to each buffer, so that the odd output data is outputted to the multiplexer 60 and then, is transmitted to the host via the input/output bus. Also, the even input/output buffer 33 and the even output buffer 53 are driven in the falling edge of the clock inputted to each buffer, so that the even output data transmitted to the host.
[94] As shown in FIG. 8, in the read operation, the output of the even data (Deout) starts in the falling edge of the clocks and the output of the odd data (Doout) starts in the rising edge of the clocks.
[95] In the meantime, in the write operation, the chip enable signal and the write enable signal are inputted to the control logic 20, the control logic allows control signals for controlling the read operation to be applied to the odd and even global buffers 41 and 43 and the odd and even input/output buffers 31 and 33, thereby driving each buffer.
[96] Here, the odd global buffer 41 and the odd input/output buffer 31 are driven in the rising edge of the inputted clocks, so that the odd input data transmitted selectively from the demultiplexer 70 is transmitted to the NAND flash cell array 10, thereby recording the odd input data in a predetermined area of the NAND flash cell array 10. Also, the even global buffer 43 and the even input/output buffer 33 are driven in the falling edge of the inputted clocks, so that the even input data is recorded in a predetermined area of the NAND flash cell array 10.
[97] As shown in FIG. 9, in the write operation, the input of the even data (Dein) starts in the falling edge of the clocks and the input of the odd data (Doin) starts in the rising edge of the clocks.
[98] FIG. 10 is a schematic diagram illustrating an operation status of data input/output among buffers of a NAND flash memory according to further another embodiment of the present invention.
[99] As shown in FIG. 10, in the NAND flash memory according to further another embodiment of the present invention, the input/output buffers 31 and 33 are divided into multiple bits therein and the NAND flash cell array 10, the odd and even global buffers 41 and 43 and the odd and even output buffers 51 and 53 are connected to the multiple bits. Here, each configuration is synchronized with the inputted clocks, thereby performing the operations of the read and write thereof.
[100] In the read operation, each configuration is synchronized with the inputted clocks, so that each data is transmitted to the multiple bits of the input/output buffers 31 and 33 in a row through the global buffers 41 and 43, and then, they are transmitted to the NAND flash cell memory 10 in a row through the input/output buffers 31 and 33.
[101] Also, in the write operation, each configuration is synchronized with the inputted clocks, so that each data is transmitted to the multiple bits of the input/output buffers 31 and 33 in a row through the NAND flash cell memory 10, and then, they are transmitted to the output buffers 51 and 53 in a row through the input/output buffers 31 and 33.
[102] FIG. 11 is a schematic diagram illustrating an application example of a NAND flash memory according to further another embodiment of the present invention.
[103] As shown in Fig. 11, a plurality of NAND flash memories 100 are electrically connected to the corresponding controller 200 connected to each other through a loop back clock circuit for clock synchronization.
[104] Accordingly, each controller 200 is synchronized with the clocks and controls the corresponding NAND flash memory 100 at the necessary time, thereby sending and transmitting each data.
[105] While this invention has been described in connection with what are presently considered to be the most practical and preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments and the drawings, but, on the contrary, it is intended to cover various modifications and variations within the spirit and scope of the appended claims.
[106]
Industrial Applicability
[107] The present invention relates to a dual edge accessible NAND flash memory, in that each buffer related to a data input/output with a NAND flash cell array is divided into odd and even buffers and the data of the odd and even buffers is alternately inputted or outputted from both edges of the rising and falling of signals received from a host, whereby remarkably increasing the efficiency of the data transmittance thereof.

Claims

Claims
[1] An input/output circuit of a dual edge accessible NAND flash memory comprising: first and second global buffers operated in rising and falling edges of a write control signal received from a host respectively so as to temporarily stores a data; first and second output buffers operated in rising and falling edges of a read control signal received from the host respectively so as to temporarily stores a reading data; first and second odd input/output buffers operated in the rising and falling edges of the read control signal received from the host respectively so as to transmit data read from a NAND flash cell array to the first and second output buffers respectively and operated in the rising and falling edges of the write control signal received from the host respectively so as to transmit the data stored temporarily in the first and second global buffers to the NAND flash cell array; and a control logic for transmitting control signals corresponding to any signals received from the host to each configuration, thereby controlling an operation of each configuration.
[2] An input/output circuit of a dual edge accessible NAND flash memory as claimed in claim 1, further comprising a multiplexer connected to output terminals of the first and second output buffers so as to selectively output an output data of the first output buffer in the rising edge of the read control signal and selectively output other output data of the second output buffer in the falling edge of the read control signal and a demultiplexer connected to input terminals of the first and second global buffers so as to selectively output an input data to the input terminal of the first global buffer in the rising edge of the write control signal and selectively output other input data to the input terminal of the second global buffer in the falling edge of the write control signal.
[3] An input/output circuit of a dual edge accessible NAND flash memory comprising: first and second global buffers driven through a write control signal received from a host and operated in rising and falling edges of a synchronization clock received from the host respectively so as to temporarily stores a writing data; first and second output buffers driven through a read control signal received from the host and operated in rising and falling edges of the synchronization clock received from the host respectively so as to temporarily stores a reading data; first and second odd input/output buffers driven through the read control signal received from the host and operated in the rising and falling edges of the syn- chronization clock received from the host respectively so as to transmit data read from a NAND flash cell array to the first and second output buffers respectively and operated in the rising and falling edges of the synchronization clock received from the host respectively so as to transmit the data stored temporarily in the first and second global buffers to the NAND flash cell array; and a control logic for transmitting control signals corresponding to any signals received from the host to each configuration, thereby controlling an operation of each configuration.
[4] An input/output circuit of a dual edge accessible NAND flash memory as claimed in claim 3, further comprising a multiplexer connected to output terminals of the first and second output buffers so as to selectively output an output data of the first output buffer in the rising edge of the synchronization clock and selectively output other output data of the second output buffer in the falling edge of the read control signal and a demultiplexer connected to input terminals of the first and second global buffers so as to selectively output an input data to the input terminal of the first global buffer in the rising edge of the synchronization clock and selectively output other input data to the input terminal of the second global buffer in the falling edge of the write control signal.
[5] An input/output circuit of a dual edge accessible NAND flash memory as claimed in claim 3, wherein the first and input/output buffers are divided into multiple bits therein, the first and second global buffers and the first and second output buffers connected to the multiple bits, and each area of the divided multiple bits is synchronized with the synchronization clock, thereby storing and outputting the data.
PCT/KR2008/000309 2007-01-29 2008-01-18 Dual edge access nand flash memory WO2008093947A1 (en)

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