WO2008143980A3 - Dynamic processor power management device and method thereof - Google Patents

Dynamic processor power management device and method thereof Download PDF

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Publication number
WO2008143980A3
WO2008143980A3 PCT/US2008/006294 US2008006294W WO2008143980A3 WO 2008143980 A3 WO2008143980 A3 WO 2008143980A3 US 2008006294 W US2008006294 W US 2008006294W WO 2008143980 A3 WO2008143980 A3 WO 2008143980A3
Authority
WO
WIPO (PCT)
Prior art keywords
processor
software
power mode
hardware
management device
Prior art date
Application number
PCT/US2008/006294
Other languages
French (fr)
Other versions
WO2008143980A2 (en
Inventor
Alex Branover
Frank P. Helms
Jonathan M. Owen
Kurt Lewchuk
Maurice Steinman
Paul Mackey
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Priority to KR1020097026553A priority Critical patent/KR101462564B1/en
Priority to GB0920862.0A priority patent/GB2462046B/en
Priority to CN200880024649A priority patent/CN101755250A/en
Publication of WO2008143980A2 publication Critical patent/WO2008143980A2/en
Publication of WO2008143980A3 publication Critical patent/WO2008143980A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power

Abstract

A processor (105) can operate in different power modes. In an active power mode, the processor executes software (303). In response to receiving a halt indication (304) from the software, hardware at the processor evaluates bus transactions (306) for the processor. If the bus transactions meet a heuristic (307), hardware places a processor core in a lower power mode, such as a retention mode (308). Because the bus transactions are evaluated by hardware, rather than by software, and the software is not required to perform handshakes and other protocols to place the processor in the lower power mode, the processor is able to place the processor core into the lower power mode more quickly, thereby conserving power.
PCT/US2008/006294 2007-05-18 2008-05-16 Dynamic processor power management device and method thereof WO2008143980A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020097026553A KR101462564B1 (en) 2007-05-18 2008-05-16 Dynamic processor power management device and method thereof
GB0920862.0A GB2462046B (en) 2007-05-18 2008-05-16 Dynamic processor power management device and method thereof
CN200880024649A CN101755250A (en) 2007-05-18 2008-05-16 Dynamic processor power management device and method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/750,365 2007-05-18
US11/750,365 US7870407B2 (en) 2007-05-18 2007-05-18 Dynamic processor power management device and method thereof

Publications (2)

Publication Number Publication Date
WO2008143980A2 WO2008143980A2 (en) 2008-11-27
WO2008143980A3 true WO2008143980A3 (en) 2009-11-05

Family

ID=40028740

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2008/006294 WO2008143980A2 (en) 2007-05-18 2008-05-16 Dynamic processor power management device and method thereof

Country Status (6)

Country Link
US (1) US7870407B2 (en)
KR (1) KR101462564B1 (en)
CN (1) CN101755250A (en)
GB (1) GB2462046B (en)
TW (1) TWI439849B (en)
WO (1) WO2008143980A2 (en)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5384959B2 (en) * 2009-01-28 2014-01-08 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー Electronic circuit
US8185678B1 (en) * 2009-06-19 2012-05-22 Xilinx, Inc. Method and apparatus for controlling a data bus
US8601302B2 (en) * 2009-06-22 2013-12-03 Amazon Technologies, Inc. Processor system in low power state retention mode with linear regulator off and switch regulator low in power management IC
US8990591B2 (en) * 2009-12-31 2015-03-24 Intel Corporation Power management system for selectively changing the power state of devices using an OS power management framework and non-OS power management framework
JP5537392B2 (en) * 2010-11-18 2014-07-02 オリンパス株式会社 Data processing device
FR2967797A1 (en) * 2010-11-18 2012-05-25 St Microelectronics Sa Method for controlling power supply of e.g. processor, involves applying auxiliary voltage higher/equal to minimum voltage and lower than power supply level, to terminals when residual voltage is lower than threshold
US9069555B2 (en) * 2011-03-21 2015-06-30 Intel Corporation Managing power consumption in a multi-core processor
US8977878B2 (en) * 2011-05-19 2015-03-10 Texas Instruments Incorporated Reducing current leakage in L1 program memory
US8650422B1 (en) * 2011-07-01 2014-02-11 Xilinx, Inc. Time adjustment for implementation of low power state
US9158693B2 (en) * 2011-10-31 2015-10-13 Intel Corporation Dynamically controlling cache size to maximize energy efficiency
KR101885857B1 (en) * 2012-01-04 2018-08-06 삼성전자주식회사 Temperature management unit, system on chip including the same and method of managing temperature in a system on chip
CN102662822B (en) * 2012-04-26 2015-02-04 华为技术有限公司 Load monitoring device and load monitoring method
US9229524B2 (en) * 2012-06-27 2016-01-05 Intel Corporation Performing local power gating in a processor
JPWO2014006722A1 (en) * 2012-07-05 2016-06-02 富士通株式会社 Semiconductor integrated circuit and control method thereof
KR102001414B1 (en) * 2012-09-27 2019-07-18 삼성전자주식회사 System-on-chip controlling power supply correspond to data transaction and operating method thereof
JP2014102710A (en) * 2012-11-20 2014-06-05 Toshiba Corp Communication device and method therefor
US9372526B2 (en) 2012-12-21 2016-06-21 Intel Corporation Managing a power state of a processor
US9317094B2 (en) 2012-12-28 2016-04-19 Nvidia Corporation Distributed power delivery to a processing unit
US9081577B2 (en) * 2012-12-28 2015-07-14 Intel Corporation Independent control of processor core retention states
WO2014175866A1 (en) * 2013-04-23 2014-10-30 Hewlett-Packard Development Company, L.P. Retrieving system boot code from a non-volatile memory
US10733288B2 (en) 2013-04-23 2020-08-04 Hewlett-Packard Development Company, L.P. Verifying controller code and system boot code
CN104122967B (en) * 2013-04-24 2019-04-05 深圳市祈飞科技有限公司 A kind of power on and off reset control circuit and computer
US9305632B2 (en) 2013-04-29 2016-04-05 Qualcomm Incorporated Frequency power manager
US11399344B2 (en) 2015-01-26 2022-07-26 Apple Inc. System and method for SoC idle power state control based on I/O operation characterization
US10234932B2 (en) * 2015-07-22 2019-03-19 Futurewei Technologies, Inc. Method and apparatus for a multiple-processor system
CN105843370A (en) * 2016-05-31 2016-08-10 合肥联宝信息技术有限公司 Electronic device and power saving control method thereof
WO2020159533A1 (en) 2019-02-01 2020-08-06 Hewlett-Packard Development Company, L.P. Security credential derivation
WO2020167283A1 (en) 2019-02-11 2020-08-20 Hewlett-Packard Development Company, L.P. Recovery from corruption
US11169841B2 (en) 2020-03-17 2021-11-09 Internationl Business Machines Corporation Tunable power save loop for processor chips

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396635A (en) * 1990-06-01 1995-03-07 Vadem Corporation Power conservation apparatus having multiple power reduction levels dependent upon the activity of the computer system
US20040255176A1 (en) * 2003-06-10 2004-12-16 Varghese George Method and apparatus for improved reliability and reduced power in a processor by automatic voltage control during processor idle states

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2974950B2 (en) * 1995-10-26 1999-11-10 インターナショナル・ビジネス・マシーンズ・コーポレイション Information processing system
US5692202A (en) * 1995-12-29 1997-11-25 Intel Corporation System, apparatus, and method for managing power in a computer system
US5926640A (en) * 1996-11-01 1999-07-20 Digital Equipment Corporation Skipping clock interrupts during system inactivity to reduce power consumption
US6018803A (en) * 1996-12-17 2000-01-25 Intel Corporation Method and apparatus for detecting bus utilization in a computer system based on a number of bus events per sample period
US6240521B1 (en) * 1998-09-10 2001-05-29 International Business Machines Corp. Sleep mode transition between processors sharing an instruction set and an address space
US6754837B1 (en) * 2000-07-17 2004-06-22 Advanced Micro Devices, Inc. Programmable stabilization interval for internal stop grant state during which core logic is supplied with clocks and power to minimize stabilization delay
JP3544932B2 (en) * 2000-10-05 2004-07-21 Ｎｅｃエレクトロニクス株式会社 Electronic device and power control method thereof
US6816977B2 (en) * 2001-12-03 2004-11-09 Hewlett-Packard Development Company, L.P. Power reduction in computing devices using micro-sleep intervals
US20040128416A1 (en) * 2002-12-11 2004-07-01 Tsvika Kurts Apparatus and method for address bus power control
KR100481873B1 (en) * 2003-02-04 2005-04-11 삼성전자주식회사 Media access controller with power-save mode
US7197652B2 (en) * 2003-12-22 2007-03-27 International Business Machines Corporation Method and system for energy management in a simultaneous multi-threaded (SMT) processing system including per-thread device usage monitoring
US7228446B2 (en) * 2004-12-21 2007-06-05 Packet Digital Method and apparatus for on-demand power management
US7337335B2 (en) * 2004-12-21 2008-02-26 Packet Digital Method and apparatus for on-demand power management
US7689849B2 (en) * 2006-08-28 2010-03-30 Ati Technologies Ulc Reduction of power consumption by throttling processor requests

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396635A (en) * 1990-06-01 1995-03-07 Vadem Corporation Power conservation apparatus having multiple power reduction levels dependent upon the activity of the computer system
US20040255176A1 (en) * 2003-06-10 2004-12-16 Varghese George Method and apparatus for improved reliability and reduced power in a processor by automatic voltage control during processor idle states

Also Published As

Publication number Publication date
KR101462564B1 (en) 2014-11-18
GB0920862D0 (en) 2010-01-13
US20080288799A1 (en) 2008-11-20
TW200903245A (en) 2009-01-16
CN101755250A (en) 2010-06-23
GB2462046B (en) 2012-05-30
US7870407B2 (en) 2011-01-11
TWI439849B (en) 2014-06-01
WO2008143980A2 (en) 2008-11-27
KR20100017874A (en) 2010-02-16
GB2462046A (en) 2010-01-27

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