WO2008148481A1

WO2008148481A1 - Integrated capacitive sensor

Info

Publication number: WO2008148481A1
Application number: PCT/EP2008/004206
Authority: WO
Inventors: Johann Hauer; Claudia Schuhmann; Robert Dorn; Stefan MÖDL
Original assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Priority date: 2007-06-04
Filing date: 2008-05-27
Publication date: 2008-12-11
Also published as: DE102007025947A1; EP2162987A1; DE102007025947B4

Abstract

The invention relates to an integrated capacitive sensor circuit, having a capacitive sensor (24) formed in an upper metallization layer (22) of the integrated capacitive sensor circuit, having at least two electrodes (22a, 22b) disposed in the upper metallization layer, and an electronic analysis circuit (14) coupled to the capacitive sensor (24) for determining a change in capacity of the capacitive sensor (24), wherein the capacitive sensor (24) and the analysis circuit (14) are mutually integrated on a semiconductor substrate (12).

Description

Integrated capacitive sensor

description

The present invention relates to an integrated capacitive sensor which can be used, for example, as a non-contact switch.

Capacitive sensors are widely used in measurement technology and sensor technology. For example, distances between two measurement points can be determined if the capacitance between the two measurement points is precisely measured so that, knowing the theoretical relationship between capacitance and distance, the measured capacitance can be used to deduce the distance between the two measurement points. Generally, a capacitance between two surfaces is determined by a geometry of the surfaces and a dielectric surrounding the surfaces. If one changes the properties of the dielectric, for example by bringing a material with different dielectric properties close to the surfaces, the capacitance between the two surfaces changes in part considerably.

Many technical applications take advantage of this by using a capacity change to detect touching an object or surface. Capacitive proximity and proximity switches used for this purpose have long been known. The patent DE 101 31 243 Cl, for example, describes a capacitive proximity switch with two sensor electrodes, which are arranged such that one of the two sensor electrodes protrudes outwards relative to the other. If, for example, a person or an electrically conductive object approaches the proximity switch, the capacitance of the two sensor electrodes changes. For the sensor electrode which protrudes further, a higher here capacity than the less protruding sensor electrode. By the difference signal, at least one electrical switch can be actuated and thereby, for example, a robot can be put out of action.

The published patent application DE 32 21 223 A1 deals with a capacitive proximity switch operated with alternating current, which can be used, for example, for monitoring a fill level in a container. The utility model DE 299 15 014 Ul describes a capacitive proximity switch with an electrical bridge circuit for detecting an approaching or removing object. DE 3815698 A1 discloses a self-checking proximity switch with an oscillator which can be influenced by approaching an object to its sensor surface. EP 0 766 398 A1 also describes a capacitive switch with a capacitive probe having a sensor electrode and a shield electrode and an electrode having an oscillator formed by a feedback system of two amplifiers. EP 1 505 734 A2 deals with a capacitive proximity switch for detecting a capacitance change, in particular for use in a door handle of a motor vehicle.

In the known sensors and their applications, a change in capacitance or impedance between a sensor surface relative to the reference mass or a plurality of sensor surfaces relative to each other upon approaching and / or touching an object or a human body part is detected and evaluated.

A disadvantage of the known methods is an expensive construction of the sensor circuits by a separation of sensor surfaces and transmitter for signal detection in different modules. The object of the present invention is therefore to provide a compact, cost-effective capacitive sensor circuit.

This object is achieved by an integrated capacitive sensor circuit according to claim 1 and a method for producing the same according to claim 16.

The present invention is based on the finding that a capacitive sensor circuit having the desired properties can be realized as an integrated component. For this purpose, in embodiments of the present invention, a capacitive sensor or measuring capacitor with at least two electrodes and evaluation electronics for controlling the capacitive sensor and for signal detection are jointly applied to a semiconductor substrate in a CMOS process. The capacitive sensor is preferably arranged in an uppermost metallization layer of the integrated component and separated from it by at least one insulation layer between the uppermost metallization layer and the evaluation electronics. In order that the electronic evaluation circuit and the capacitive sensor do not interfere with one another, exemplary embodiments have a metallic shielding layer between the uppermost metallization layer of the integrated sensor circuit and the electronic evaluation circuit.

According to exemplary embodiments, the at least two electrodes of the capacitive sensor are arranged planar in the uppermost metallization layer. A geometrical arrangement of the at least two electrodes of the capacitive sensor can be optimized depending on the application in order to form a sensitive electrical or electromagnetic field as possible above or between individual sensor electrodes.

The electronic evaluation circuit implements a capacitive excitation and measurement method which generates an electric field or an electromagnetic field above the capacitive sensor. beautiful alternating field builds up. A damping of the field by an introduced into the field electrically conductive body (usually a human body part) is detected by the capacitive measurement method of the electronic evaluation circuit and then evaluated. Different capacitive measuring methods can be used for the evaluation. For example, a tunable oscillator (excited RCL circuit) may be used in which the resonant frequency is affected by the capacitance sensor's changing capacitance C _sens . In this case, for example, the voltage dropping across an ohmic resistance R can be determined as a measured variable, which is proportional to the capacitance Csens for a fixed resistance R and a fixed inductance L. The measured voltage can still be digitized in order to calculate the capacitance C _sens from a proportional relationship.

Furthermore, the electronic evaluation circuit can realize a charge transfer method (charge transfer method) in which a first capacitor is charged in a first phase and the charge is transferred in a second phase into a second capacitor. Here, both the first and the second capacity can be used as a sensor capacity. The size of the sensor capacitance must be known in order to determine the capacitance C _sens of the capacitor to be measured. Usually, the voltage drop across the sensor capacitance is determined as the measured variable.

The transmitter can also have a bridge circuit up, so that the measured capacitance C _s can be determined ns of the capaci tive ^¬ sensor by a calibration method in which, for example, a diagonal voltage of the bridge circuit is adjusted to zero.

In one embodiment of the present invention, the electronic evaluation circuit implements a differential delta-sigma method, which is disclosed in US Pat. DE 10 2005 038 875 Al is described in detail.

An advantage of the present invention is the fact that all components of the corresponding electronic evaluation circuit for the signal detection and evaluation can be integrated in a CMOS process and thus no external components are required. Thus, a capacitive sensor can be realized as an integrated component in inexpensive and compact form.

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings

Drawings explained in more detail. Show it:

1 is a side view of a layer structure of an integrated capacitive sensor circuit according to an embodiment of the present invention;

2A-F show various geometries of sensor surfaces in a metallization layer according to embodiments of the present invention;

3 is a side view and plan view of a layer structure of an integrated capacitive sensor circuit according to another embodiment of the present invention;

4 is a schematic block diagram of an integrated electronic evaluation circuit according to an embodiment of the present invention;

5 is a block diagram of an electronic evaluation circuit with self-calibration functionality according to an embodiment of the present invention; and Fig. 6 is a schematic representation of a capacitive digital-to-analog converter according to an embodiment.

With regard to the following description, it should be noted that in the different exemplary embodiments, identical or equivalent functional elements have the same reference numerals, and thus the descriptions of these functional elements in the various exemplary embodiments shown below are interchangeable.

A method for producing an integrated capacitive sensor circuit comprises, according to exemplary embodiments, an embodiment of an electronic control and evaluation circuit on a semiconductor substrate and an application of a capacitive sensor in a metallization layer over the electronic evaluation circuit, wherein the capacitive sensor is coupled to the drive and evaluation circuit , The production and application are parts of a CMOS process.

1 shows a schematic side view of a layer structure of an integrated capacitive sensor 10 according to an embodiment of the present invention.

The integrated sensor circuit 10 has an electronic evaluation circuit 14 integrated on a semiconductor substrate 12 in a standard CMOS process. Via the electronic evaluation circuit 14, an insulation layer 16 is applied, which may possibly have required (not shown) plated-through holes from the electronic evaluation circuit 14 to a first metallization 18. Above the first metallization level 18, a further insulation layer 20 is arranged, with possible through-contacts (not shown) from the first metallization level 18 to a second or uppermost metallization level 22. According to exemplary embodiments, the uppermost metallization level 22 represents a capacitive sensor surface. To this end, at least two partial areas 22a, 22b are structured in the uppermost metallization level 22, which act as electrodes of a capacitive sensor 24. Via the through contacts of the insulation layers 20, 16, the capacitive sensor 24 or the sensor surface is coupled to the electronic evaluation circuit 14.

With the evaluation electronics 14, a drive signal can now be applied to the electrodes 22a, b of the capacitive sensor 24 of the sensor surface. This may be, for example, a DC voltage or else an AC voltage. By the drive signal applied to the electrodes 22a, b, an electrical or electromagnetic field is formed above the electrodes 22a, b. This field, whose field lines are indicated by way of example in FIG. 1, is dependent on the geometric arrangement of the electrodes 22a, b and the dielectric properties of the medium surrounding the electrodes 22a, b.

If an object with different dielectric properties than the medium surrounding the electrodes 22a, b is introduced into the electrical or electromagnetic field, the capacitance C _{sens of} the capacitive sensor 24 changes. This change in the capacitance C _sens can be detected by the electronic evaluation circuit 14, which is coupled to the measuring capacitor 24 can be determined.

Depending on the application, the geometric arrangement of the electrodes or sensor surfaces 22a, b can be optimized in order to form a sensitive electric or electromagnetic field. Some geometry variants are shown by way of example in FIGS. 2A to 2F.

FIGS. 2A to 2F show schematic plan views of integrated capacitive sensor circuits 10a to 10f. With the reference numeral 30 connecting pins of the integrated components 10a to 10f are indicated. The at least two electrodes 22a, b in the uppermost metallization layer 22 can be patterned depending on the application.

2A and B show two electrodes 22a, b arranged parallel to one another in the uppermost metallization layer, wherein the variants shown in the two figures differ by the width and spacing of the electrodes 22a, b. For example, "parallel" refers to opposite sides of the electrodes 22a, b, and a parallel arrangement also means a slightly different orientation due to unavoidable manufacturing process tolerances, ie an angle included from opposite sides of the electrodes 22a, b is, for example less than 1 °.

Similarly, Fig. 2C shows a substantially parallel arrangement of four metallic electrode elements 32-1 to 32- 4, of which, for example, two each form an electrode. According to exemplary embodiments, in FIG. 2C, for example, the electrode elements 32-1 and 32-2 could form an electrode and the electrode elements 32-3 and 32-4 could form a second electrode of a capacitive sensor 24. It would also be conceivable to connect the four electrode elements 32-1 to 32-4 so that two separate measuring capacitors or capacitive sensors are formed, which can then be driven in antiphase, for example.

The same applies to the geometric arrangements shown in FIGS. 2D and 2E. Here, too, two of the exemplary four electrode elements 32-1 to 32-4 could be combined into one electrode of the capacitive sensor 24. 32-1 to 32-4 two separate Messkondensa ^¬ factors or capacitive sensors form an embodiment in which the four E- lektrodenelemente, is also possible. The integrated components 10d and 10e or their capacitive sensors have a (fictitious) point of symmetry 34, to which the four electrode elements 32-1 to 32-4 are arranged point-symmetrically. Furthermore, symmetry axes could also be defined by the point of symmetry 34, to which the electrodes or electrode elements 32-1 to 32-4 are axisymmetric.

In all the configurations shown in FIGS. 2A-E, the electrodes or electrode elements are thus arranged symmetrically, in particular axially symmetrically.

FIG. 2F shows two metallic electrodes 22a, 22b, each of which is comb-shaped and overlappingly interlocking in the manner shown in FIG. 2F, so that a meander-shaped surface is formed between the two electrodes 22a, b.

It should be noted at this point that the geometry variants shown in FIGS. 2a to 2f are meant to be exemplary only and in no way intended to represent a concluding enumeration. As already mentioned, the geometry of the sensor surface or of the capacitive sensor 24 in the metallization layer 22 is to be adapted to the particular application in order to achieve an optimized sensor effect.

For a variety of methods for measuring a capacitance or change in capacitance, a reference capacitance in addition to the sensor capacitance C _ref C _Sens or a Referenzkon ^¬ capacitor needed. A schematic side view of a layer structure of an integrated capacitive sensor circuit 40 with a reference capacitor is shown in FIG. 3.

The integrated sensor circuit 40 has a first metallization layer as the wiring level 42, which is insulated from the following metallization layer 18 by an insulation layer 44 via the insulation layer 16 lying above the electronic evaluation circuit 14. Over the second metallization layer 18 follows a Insulation layer 20 on which the next metallization layer 22, etc. is applied. In the embodiment of the present invention shown in FIG. 3, the metallization layer 22 is an uppermost metallization layer. Depending on the process, different numbers of metallization layers can be realized. At least three metallization layers are desirable for the sensor.

In the metallization layer 18 between the uppermost metallization layer 22 and the electronic evaluation circuit 14, a reference capacitor 46 is formed with a reference capacitance C _ref according to embodiments. In embodiments, the reference capacitor 46 has the same geometric structure as the measuring capacitor or the capacitive sensor 24 in the uppermost metallization plane 22. Here, the same geometrical structure also means a slightly different geometrical structure due to unavoidable manufacturing process tolerances. This means that geometric deviations between the reference capacitor 46 and the capacitive sensor 24 are below 1 ° / oo (1 per thousand).

Examples of geometries of measuring or reference capacitors have already been explained above with reference to FIGS. 2A to 2F.

As can be seen from Fig. 3, the reference capacitor is offset laterally with respect to the measuring capacitor 24 46, so that the two capacitors laterally ^¬ not overlap. To the reference capacitor 46 is in the example shown in Fig. 3 embodiment in the top metallization layer 22 approximately ^¬ a screen surface 48 formed for electromagnetic shielding of the reference capacitor 46 of external influences. In the metallization 18 Zvi ^¬ rule the topmost metallization 22 and the electro ^¬ African evaluation circuit 14, a further shielding surface 50 is similar to below the reference capacitor 24 of the Screen surface 48 formed. The shielding surface 50 serves to shield the capacitive sensor 24 from the active electronic evaluation circuit 14, and vice versa.

A schematic plan view of the integrated capacitive sensor circuit 40 is shown in the lower part of FIG. 3. In this case, the surfaces shown in gray are located in the uppermost metallization layer 22, whereas the surfaces shown in white are located in the underlying metallization layer 18.

After having discussed in the foregoing construction possibilities of the capacitive sensor circuit integrated in CMOS technology according to exemplary embodiments, in the following implementation possibilities of the electronic evaluation circuit 14 will be described in more detail.

As already mentioned, there are numerous possibilities for constructing electronic evaluation circuits.

For example, tunable oscillators, such as RCL circuits or non-linear Wien-Robinson oscillators, may be used in the integrated evaluation circuit 14. With them, a resonance frequency can be influenced by the changing sensor capacitance C _sens .

Another possibility is to provide bridge circuits in the integrated evaluation circuit 14, in which the capacitance C _sens to be measured can be determined by a balancing method by usually regulating a diagonal voltage of the bridge circuit to zero.

A block diagram of a preferred electronic evaluation teschaltung 14, with the sensor capacitance C s _sen having a high resolution can be measured with only a relatively low component cost is necessary, as shown in Fig. 4. 4 shows a delta-sigma ADC 50 (ADC = Analogue Digital Converter) coupled to both the capacitive sensor or the measuring capacitor 24 with the sensor capacitance C _sens and the reference capacitor 46 to the reference capacitance C _ref , the output side having a digital comparator 52 is coupled. In this case, the delta-sigma ADC 50 and the digital comparator 52 are parts of the electronic evaluation circuit 14.

The delta sigma ADC 50 includes a delta sigma modulator 54 and a filter and decimator block 56. The delta sigma modulator 54 typically includes an operational amplifier. According to embodiments, the at least two electrodes 22a, b of the capacitive sensor 24 and the capacitance C _{sens are} connected to the inverting and non-inverting input of the operational amplifier. Furthermore, the electrodes 22a, b are connected to a reference signal source of the electronic evaluation circuit 14 in order to generate an electrical or electromagnetic alternating field.

The delta-sigma modulator 54 forms in its input integrator (not shown) a difference between the charges of the sensor capacitance C _sens and the reference capacitance C _re f. If both capacities are exactly the same, the charge difference becomes zero. If the electric or electromagnetic field is then influenced by the sensor capacitance C _{sens of} the capacitive sensor 24, this leads to a change in the charge quantity in the sensor capacitance C _sen s, which is transferred to the integrator of the delta-sigma modulator 54. The delta-sigma modulator 54 generates at its output a digital bit stream, which is converted into a digital value by a low-pass filter and a sampling rate decimator in the filter and decoder block 56. The digital value at the output of the filter and decimator block 56 represents the difference in charge between the two capacitors C _REF and C _sens - A specification of a digita ^¬ len switching threshold, in the digital comparator 52, a be achieved by a strength of the sensor damping or the capacitance change ΔC _S ens dependent switching function of the integrated component or sensor. This switching threshold is usefully adjustable to realize.

The operation of electronic evaluation circuits according to embodiments with delta-sigma ADCs or modulators is detailed and described in detail in the published patent application DE 10 2005 038 875 A1, so that at this point for the sake of clarity, a more detailed description should be dispensed with.

The reference _capacitance C _{rβf of} the reference _capacitor 46 should correspond as _closely as possible to the sensor capacitance C _{sens of} the capacitive sensor 24 in the rest position, ie without external influence on the electrical or electromagnetic field of the capacitive sensor 24. In a preferred embodiment, this can be achieved by _{virtue of} the reference capacitor C _ref or the reference capacitor 46 being given exactly the same geometric structure as the measuring capacitor 24, as has already been described above with reference to FIG. 3. In contrast to the sensor capacitance C _sens , the reference capacitance C _re f should not be damped or changed by an external influence. The shield surface 48 of the upper metallization layer 22 shields the reference capacitance 46 against external influences.

It should also be noted that within the scope of a CMOS process, the capacitive sensors or capacitors 24, 46, in particular the reference capacitor 46, can also be realized differently than with reference to FIGS. 1 to 3. Conceivable, for example, in the reverse direction operated pn junctions, poly-silicon / diffusion capacitances, poly-silicon / poly-silicon capacitances or metal / metal capacitances. Process and production variations can sometimes lead to significant fluctuations in the production of integrated capacitors or capacitors. Therefore, in embodiments of the present invention, a fine balance between the sensor capacitance C _sens and reference capacitance C _re f is performed by a self-calibration algorithm. According to embodiments, the reference _capacitance C _rβ f is replaced or supplemented by a capacitive digital-to-analog converter. In this case, a capacitive digital-to-analog converter should be understood to mean an arrangement of binary weighted capacitances which can be applied via digital switches, for example to a reference input of the delta-sigma modulator 54. In a calibration mode, the digital switches of the capacitive digital-to-analog converter are switched on according to a successive approximation principle until the output of the decimator 56 at rest reaches the digital value "zero" and thus indicates that the charges (Q _ie t, Qsen _s ) in reference and sensor capacitance C _re f, C _{sens are} at least approximately identical, ie within a predetermined tolerance range, such as 0.95Q _re f <Q _s ns <l-05Q _re f this calibration method also for the reference capacitance C _ref and the reference capacitor 46 shown in FIG. 3, when the surface of the reference capacitor 46 is divided into different sized interconnectable faces and switch the part surfaces are switched such that the total capacitance C _re f of the reference capacitor 46 is formed according to the calibration method so that it corresponds to the sensor capacitance C _sens in rest position corresponds exactly lent.

FIG. 5 shows a schematic block diagram for the realization of the above-described calibration method of the evaluation circuit 14.

In FIG. 5, the reference capacitor .C _{ref is} replaced by a capacitive digital-to-analog converter 60 compared to FIG. The output of the low The pass filter and / or decimator 56 is fed back to an SA register 64 (SA = Successive Approximation Register) via a SAR controller 62 (SA = Successive Approximation Register) so that the SA register 64 has a reference capacitance C _re f of the capacitive digital-to-analog converter 60 can set via digital switches, so that at rest at the output of the decimator 56, the value "zero" occurs.

In the case of the successive approximation or the stepwise approximation, the analog output, that is to say the capacitance, of the capacitive digital / analog converter 60 is compared via a comparator 54, 56 with a desired value, that is, the sensor capacitance Csens _> . Successively, the individual bits or switches of the capacitive digital-to-analog converter 60 via the SA register 64, starting at the most significant bit (MSB = Most Significant Bit) down to the least significant bit (LSB = Least Significant bit) successively. In each clock cycle, the SAR controller 62 sets the bit in progress on a trial basis and the capacitive digital-to-analog converter 60 generates the reference capacitance C _ref corresponding to the current digital value. The comparator 54, 56 compares the reference _capacitance C _rβf with the sensor _capacitance Cg _e n _s and causes the SAR controller 62 to reset the bit in progress when the reference capacitance Cref is higher than the sensor capacitance C _sen s- Reference capacitance C _re f is less than or equal to the sensor capacitance Cg _ens , the bit remains set. Thus, a (successive) approximation of the reference capacitance Cr _ef to the sensor capacitance C _sens takes place step by step. After n (n is the number of bits or switches), the output value C _{ref of} the capacitive digital-to-analog converter 60 is as close as possible to the reference value C _sens at rest. A block diagram of the capacitive digital-to-analog converter 60 according to an exemplary embodiment is shown in FIG. 6.

In one embodiment, the capacitive digital-to-analog converter 60 has, between its two terminals, a parallel connection of capacitors C _re f, i to C _re f _{f5 which can be} switched via switches 70-1 to 70-5. The switch positions of the switches 70-1 to 70-5 may be controlled via the SA register 64 and the SAR controller 62. Accordingly, those capacitances C _{ref / n} (n = 1,..., 5) which are required in order to approximate the resulting total reference capacitance C _ref as exactly as possible to the value of the sensor capacitance C _sens in the rest position can be switched on successively. If, for example, a deviation from the sensor capacitance C _{Sens is} relatively small, which manifests itself in a small value at the output of the device 56, then the SAR controller 62 can instruct the SA register 64, a capacitance deviation at least approximately corresponding capacitance C _ref , _{x on} or off, depending on whether the total reference capacitance C _{ref is} smaller or larger than the sensor capacitance C _sens . In the case of a large deviation, accordingly, a corresponding larger capacity of the capacitances C _r e _f , _{x is} added or removed.

According to exemplary embodiments, an integrated capacitive sensor circuit 10, 40 is encapsulated hermetically and electrically insulating in a standard plastic housing customary for semiconductor production. The field lines of the at least two electrodes 22a, b or of the capacitive sensor 24 can propagate to the outside almost unhindered through the plastic material of the housing. A user is thus already galvanically separated from the current-carrying parts of the integrated capacitive sensor 10, 40 by the construction technique.

In summary, embodiments of the present invention thus provide a compact integrated capacitive Semiconductor-based sensor that can be fabricated in conventional CMOS process steps. An electronic evaluation circuit 14 integrated on a semiconductor substrate can measure a sensor capacitance C _sens with high resolution, whereby only a relatively small component expenditure is required. Thus, in embodiments sensor surfaces and signal detection can be integrated together in one component, whereby a complex construction of conventional capacitive sensors can be avoided.

Finally, it should be noted that the present invention is not limited to the respective components of the integrated sensor or the explained procedure, since these components and methods may vary. The terms used herein are intended only to describe particular embodiments and are not intended to be limiting. When the singular or indefinite articles are used in the specification and claims, they also refer to the majority of these elements unless the context clearly indicates otherwise. The same applies in the opposite direction.

Claims

claims

1. Integrated capacitive sensor circuit (10; 40) with

a capacitive sensor (24) formed in an uppermost metallization layer (22) of the integrated capacitive sensor circuit with at least two electrodes (22a, b) arranged in the uppermost metallization layer (22); and

an electronic evaluation circuit (14) coupled to the capacitive sensor (24) for detecting a capacitance change of the capacitive sensor (24),

wherein the capacitive sensor (24) and the evaluation circuit (14) are integrated together on a semiconductor substrate (12).

2. Integrated capacitive sensor circuit according to claim

1, in which a reference capacitor (46) with a reference capacitance (C _ref ) is formed in a metallization layer (18) between the uppermost metallization layer (22) and the electronic evaluation circuit (14).

3. Integrated capacitive sensor circuit according to claim

2, wherein the reference capacitor (46) has a same geometric structure as the capacitive sensor (24) in the uppermost metallization layer (22).

4. Integrated capacitive sensor circuit according to claim 2 or 3, wherein the reference capacitor (46) to the capacitive sensor (24) is laterally offset and above the reference capacitor (46) in the uppermost Metalli ^¬ sierungsschicht (22) a shielding surface (48) for electromagnetic Shielding of the reference capacitor (46) is formed.

5. Integrated capacitive sensor circuit according to one of claims 2 to 4, wherein the reference capacitance (C _ref ) of the reference capacitor (46) is variable in order to set a predefined resting capacity (C _se ns) of the capacitive sensor (24) without external influences can ,

6. Integrated capacitive sensor circuit according to claim 5, wherein the reference capacitor (46) can be divided into different sized, interconnectable sub-areas in order to vary its capacity (C _rβf ) can.

7. Integrated capacitive sensor circuit according to one of the preceding claims, wherein in a metallization layer (18) between the uppermost metallization layer (22) and the electrical evaluation circuit (14) a shielding surface (50) for electromagnetic see shielding the transmitter before the measuring capacitor, and conversely, is formed.

8. An integrated capacitive sensor circuit according to one of the preceding claims, wherein opposite sides of the at least two electrodes (22a, b) of the capacitive sensor (24) in the uppermost metallization layer (22) are arranged parallel to each other.

9. Integrated capacitive sensor circuit according to one of the preceding claims, wherein the at least two

Electrodes (22a, b) are comb-shaped and Ü overlap overlap, so that a meander-shaped surface between the two electrodes (22a, b) is formed.

10. Integrated capacitive sensor circuit according to one of the preceding claims, wherein the capacitive sensor (24) has a point of symmetry (34) and the weak at least two electrodes (22a, b) are arranged point-by-point to the point of symmetry.

11. Device according to one of the preceding claims, wherein the electronic evaluation circuit (14) is designed to apply an alternating voltage to the at least two electrodes (22a, b) of the capacitive sensor (24) in order to generate an electromagnetic alternating field.

12. Integrated capacitive sensor circuit according to one of the preceding claims, wherein the electronic evaluation circuit (14) comprises a delta-sigma modulator (54) with an operational amplifier.

13. An integrated capacitive sensor circuit according to claim 12, wherein the at least two electrodes (22a, b) of the capacitive sensor (24) are connected to the inverting and non-inverting input of the operational amplifier and wherein the at least two electrodes (22a, b) further with a reference signal source of the electronic evaluation circuit (14) are connected.

14. An integrated capacitive sensor circuit according to one of the preceding claims, wherein the integrated sensor circuit (10, 40) is manufactured in a CMOS technology.

15. Integrated capacitive sensor circuit according to one of the preceding claims, which is housed by a plastic housing.

16. A method for fabricating an integrated kapaziti ^¬ ven sensor circuit, comprising the steps of:

Generating an electronic evaluation circuit (14) on a semiconductor substrate (12); and Applying a capacitive sensor (24) in a metallization layer (22) over the electronic evaluation circuit (14),

wherein the generating and applying are parts of a CMOS process.