WO2009037691A3 - Programming orders for reducing distortion in arrays of multi-level analog memory cells - Google Patents

Programming orders for reducing distortion in arrays of multi-level analog memory cells Download PDF

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Publication number
WO2009037691A3
WO2009037691A3 PCT/IL2008/001188 IL2008001188W WO2009037691A3 WO 2009037691 A3 WO2009037691 A3 WO 2009037691A3 IL 2008001188 W IL2008001188 W IL 2008001188W WO 2009037691 A3 WO2009037691 A3 WO 2009037691A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory cells
programming
arrays
given row
analog memory
Prior art date
Application number
PCT/IL2008/001188
Other languages
French (fr)
Other versions
WO2009037691A2 (en
Inventor
Ofir Shalvi
Eyal Gurgi
Original Assignee
Anobit Technologies
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Anobit Technologies filed Critical Anobit Technologies
Publication of WO2009037691A2 publication Critical patent/WO2009037691A2/en
Publication of WO2009037691A3 publication Critical patent/WO2009037691A3/en
Priority to US12/721,585 priority Critical patent/US8174905B2/en
Priority to US13/412,780 priority patent/US8300478B2/en
Priority to US13/412,731 priority patent/US8437185B2/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/005—Electric analogue stores, e.g. for storing instantaneous values with non-volatile charge storage, e.g. on floating gate or MNOS
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/564—Miscellaneous aspects
    • G11C2211/5648—Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant

Abstract

A method for data storage includes predefining an order of programming a plurality of analog memory cells (32) that are arranged in rows (68). The order specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the memory cells in the neighboring rows on at least one of the sides are in an erased state, and that the memory cells in the given row are programmed to assume a highest programming level, which corresponds to a largest analog value among the programming levels of the cells, only after programming all the memory cells in the given row to assume the programming levels other than the highest level. Data is stored in the memory cells by programming the memory cells in accordance with the predefined order.
PCT/IL2008/001188 2007-09-19 2008-09-03 Programming orders for reducing distortion in arrays of multi-level analog memory cells WO2009037691A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US12/721,585 US8174905B2 (en) 2007-09-19 2010-03-11 Programming orders for reducing distortion in arrays of multi-level analog memory cells
US13/412,780 US8300478B2 (en) 2007-09-19 2012-03-06 Reducing distortion using joint storage
US13/412,731 US8437185B2 (en) 2007-09-19 2012-03-06 Programming orders for reducing distortion based on neighboring rows

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US97345307P 2007-09-19 2007-09-19
US60/973,453 2007-09-19
US1242407P 2007-12-08 2007-12-08
US61/012,424 2007-12-08
US1293307P 2007-12-12 2007-12-12
US61/012,933 2007-12-12
US5449308P 2008-05-20 2008-05-20
US61/054,493 2008-05-20

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/721,585 Continuation-In-Part US8174905B2 (en) 2007-09-19 2010-03-11 Programming orders for reducing distortion in arrays of multi-level analog memory cells

Publications (2)

Publication Number Publication Date
WO2009037691A2 WO2009037691A2 (en) 2009-03-26
WO2009037691A3 true WO2009037691A3 (en) 2010-03-04

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IL2008/001188 WO2009037691A2 (en) 2007-09-19 2008-09-03 Programming orders for reducing distortion in arrays of multi-level analog memory cells

Country Status (1)

Country Link
WO (1) WO2009037691A2 (en)

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US8174905B2 (en) 2007-09-19 2012-05-08 Anobit Technologies Ltd. Programming orders for reducing distortion in arrays of multi-level analog memory cells
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US7924613B1 (en) 2008-08-05 2011-04-12 Anobit Technologies Ltd. Data storage in analog memory cells with protection against programming interruption
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