WO2009063033A3 - Modem with improved receive power for connection to a two-wire current loop and measuring transducer, position controller and input and output unit comprising said modem - Google Patents

Modem with improved receive power for connection to a two-wire current loop and measuring transducer, position controller and input and output unit comprising said modem Download PDF

Info

Publication number
WO2009063033A3
WO2009063033A3 PCT/EP2008/065523 EP2008065523W WO2009063033A3 WO 2009063033 A3 WO2009063033 A3 WO 2009063033A3 EP 2008065523 W EP2008065523 W EP 2008065523W WO 2009063033 A3 WO2009063033 A3 WO 2009063033A3
Authority
WO
WIPO (PCT)
Prior art keywords
modem
input
signal
output unit
connection
Prior art date
Application number
PCT/EP2008/065523
Other languages
German (de)
French (fr)
Other versions
WO2009063033A2 (en
Inventor
Thomas Hauschulz
Original Assignee
Siemens Ag
Thomas Hauschulz
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag, Thomas Hauschulz filed Critical Siemens Ag
Publication of WO2009063033A2 publication Critical patent/WO2009063033A2/en
Publication of WO2009063033A3 publication Critical patent/WO2009063033A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/10—Frequency-modulated carrier systems, i.e. using frequency-shift keying
    • H04L27/14—Demodulator circuits; Receiver circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
    • H04L25/063—Setting decision thresholds using feedback techniques only

Abstract

A receiving circuit (1) is adapted to receive a frequency shift keyed input signal (ES) having a desired pulse duty factor. The receiving circuit comprises a high-pass filter (12) at the input side for decoupling the steady component of the input signal (UE) and for producing a filtered signal (FS), a downstream amplifier (16) and a downstream comparator (13) for producing a digital output signal (AS). The invention is characterized in that the receiving circuit (1) comprises an integrator (30) to which the digital output signal (AS) is supplied on the input side and which makes a correction signal (KS) available on the output side. The correction signal (KS) is retransmitted to the amplifier (16) for adjusting a steady component of the filtered signal (FS) to adjust deviations of the duty factor of the digital output signal (AS) from the desired duty factor.
PCT/EP2008/065523 2007-11-14 2008-11-14 Modem with improved receive power for connection to a two-wire current loop and measuring transducer, position controller and input and output unit comprising said modem WO2009063033A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE200710054326 DE102007054326A1 (en) 2007-11-14 2007-11-14 Reception circuit for a frequency-keyed input signal, modem with such a receiving circuit, transmitter, positioner and input and output module
DE102007054326.5 2007-11-14

Publications (2)

Publication Number Publication Date
WO2009063033A2 WO2009063033A2 (en) 2009-05-22
WO2009063033A3 true WO2009063033A3 (en) 2009-08-06

Family

ID=40560657

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2008/065523 WO2009063033A2 (en) 2007-11-14 2008-11-14 Modem with improved receive power for connection to a two-wire current loop and measuring transducer, position controller and input and output unit comprising said modem

Country Status (2)

Country Link
DE (1) DE102007054326A1 (en)
WO (1) WO2009063033A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102013107904A1 (en) * 2013-07-24 2015-01-29 Endress + Hauser Flowtec Ag Measuring device with switchable measuring and operating electronics for the transmission of a measuring signal

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4250458A (en) * 1979-05-31 1981-02-10 Digital Communications Corporation Baseband DC offset detector and control circuit for DC coupled digital demodulator
EP0343899A2 (en) * 1988-05-23 1989-11-29 Advanced Micro Devices, Inc. Circuit for generating pulses having controlled duty cycle
US5453714A (en) * 1993-03-10 1995-09-26 National Semiconductor Corporation Binary FM demodulator with self-adjusting resonant operating frequency according to demodulated binary output signal duty cycle
DE10233243A1 (en) * 2002-07-18 2004-02-12 Infineon Technologies Ag Circuit for regenerating clock signals especially in high frequency cmos has offset compensation circuit to equalize output signals

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4250458A (en) * 1979-05-31 1981-02-10 Digital Communications Corporation Baseband DC offset detector and control circuit for DC coupled digital demodulator
EP0343899A2 (en) * 1988-05-23 1989-11-29 Advanced Micro Devices, Inc. Circuit for generating pulses having controlled duty cycle
US5453714A (en) * 1993-03-10 1995-09-26 National Semiconductor Corporation Binary FM demodulator with self-adjusting resonant operating frequency according to demodulated binary output signal duty cycle
DE10233243A1 (en) * 2002-07-18 2004-02-12 Infineon Technologies Ag Circuit for regenerating clock signals especially in high frequency cmos has offset compensation circuit to equalize output signals

Also Published As

Publication number Publication date
WO2009063033A2 (en) 2009-05-22
DE102007054326A1 (en) 2009-05-20

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