WO2009072101A2 - Apparatus and methods for generating row-specific reading thresholds in flash memory - Google Patents
Apparatus and methods for generating row-specific reading thresholds in flash memory Download PDFInfo
- Publication number
- WO2009072101A2 WO2009072101A2 PCT/IL2008/001231 IL2008001231W WO2009072101A2 WO 2009072101 A2 WO2009072101 A2 WO 2009072101A2 IL 2008001231 W IL2008001231 W IL 2008001231W WO 2009072101 A2 WO2009072101 A2 WO 2009072101A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- page
- threshold
- bit error
- reading
- row
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1032—Reliability improvement, data loss prevention, degraded operation etc
Definitions
- the present invention relates generally to flash memory devices.
- Read-disturb is a known phenomenon whereby following a great many read operations performed on one or more particular physical pages within an erase sector, there is a deterioration in the quality of those physical pages or more typically in the quality of the entire erase sector. Typically, un-programmed cells tend to behave as though they were programmed, causing read errors.
- Bit error rate (BER) a parameter that a flash memory device manufacturer commits to vis a vis its customers, expressing the maximum proportion of wrongly read bits (wrongly read bits/ total number of bits) that users of the flash memory device need to expect at any time during the stipulated lifetime of the flash memory device e.g. 10 years.
- Block a set of flash memory device cells which must, due to physical limitations of the flash memory device, be erased together. Also termed erase sector, erase block.
- Cell A component of flash memory that stores one bit of information (in single-level cell devices) or n bits of information (in a multi-level device having 2 exp n levels).
- each cell comprises a floating-gate transistor, n may or may not be an integer.
- Multi-level means that the physical levels in the cell are, to an acceptable level of certainty, statistically partitionable into multiple distinguishable regions, plus a region corresponding to zero, such that digital values each comprising multiple bits can be represented by the cell.
- the physical levels in the cell are assumed to be statistically partitionable into only two regions, one corresponding to zero and one other, non-zero region, such that only one bit can be represented by a single-level cell.
- Charge level the measured voltage of a cell which reflects its electric charge.
- Decision regions Regions extending between adjacent decision levels, e.g. if decision levels are 0, 2 and 4 volts respectively, the decision regions are under 0 V, 0 V - 2 V, 2V - 4 V, and over 4 V.
- Demapping basic cell-level reading function in which a digital n-tuple originally received from an outside application is derived from a physical value representing a physical state in the cell having a predetermined correspondence to the digital n-tuple.
- Digital value or "logical value” n-tuple of bits represented by a cell in flash memory capable of generating 2 exp n distinguishable levels of a typically continuous physical value such as charge , where n may or may not be an integer.
- Erase cycle The relatively slow process of erasing a block of cells (erase sector), each block typically comprising more than one page, or, in certain non-flash memory devices, of erasing a single cell or the duration of so doing.
- Erase-write cycle The process of erasing a block of cells (erase sector), each block typically comprising a plurality of pages, and subsequently writing new data into at least some of them.
- program and “write” are used herein generally interchangeably.
- Flash memory Non-volatile computer memory including cells that are erased block by block, each block typically comprising more than one page, but are written into and read from, page by page. Includes NOR-type flash memory, NAND-type flash memory, and PRAM, e.g. Samsung PRAM, inter alia, and flash memory devices with any suitable number of levels per cell, such as but not limited to 2, 4, or 8.
- Logical page a portion of typically sequential data, whose amount is typically less than or equal to a predetermined amount of data defined to be a pageful of data, which has typically been defined by a host (data source/destination) or user thereof, as a page, and which is sent by the host to a flash memory device for storage and is subsequently read by the host from the flash memory device.
- Physical Page A portion, typically 512 or 2048 or 4096 bytes in size, of a flash memory e.g. a NAND or NOR flash memory device. Writing and reading is typically performed physical page by physical page, as opposed to erasing which can be performed only erase sector by erase sector. A few bytes, typically 16 - 32 for every 512 data bytes are associated with each page (typically 16, 64 or 128 per page), for storage of error correction information.
- a typical block may include 32 512-byte pages or 64 2048-byte pages.
- a physical page is an ordered set (e.g. sequence or array) of flash memory cells which are all written in simultaneously by each write operation, the set typically comprising a predetermined number of typically physically adjacent flash memory cells containing actual data written by and subsequently read by the host, as well as, typically error correction information and back pointers used for recognizing the true address of a page.
- Charge level The amount of charge in the cell. The Amount of charge currently existing in a cell, at the present time, as opposed to "program level", the amount of charge originally induced in the cell (i.e. at the end of programming). Program: same as "write”.
- Program level (programmed level, programming level): amount of charge originally induced in a cell to represent a given logical value, as opposed to "present level”.
- Reliability of a flash memory device may be operationalized as the probability that a worst-case logical page written and stored in that device for a predetermined long time period such as 10 years will be successfully read i.e. that sufficiently few errors, if any, will be present in the physical page/s storing each logical page such that the error code appended to the logical page will suffice to overcome those few errors.
- Np An aspect of flash memory quality. This is typically operationalized by a reprogrammability parameter, also termed herein "Np", denoting the number of times that a flash memory can be re-programmed (number of erase-write cycles that the device can withstand) before the level of errors is so high as to make an unacceptably high proportion of those errors irrecoverable given a predetermined amount of memory devoted to redundancy.
- Np a reprogrammability parameter
- Np denoting the number of times that a flash memory can be re-programmed (number of erase-write cycles that the device can withstand) before the level of errors is so high as to make an unacceptably high proportion of those errors irrecoverable given a predetermined amount of memory devoted to redundancy.
- recoverability is investigated following a conventional aging simulation process which simulates or approximates the data degradation effect that a predetermined time period e.g. a 10 year period has on the flash memory device, in an attempt to accommodate for a period of up to 10
- Resolution Number of levels in each cell, which in turn determines the number of bits the cell can store; typically a cell with 2 ⁇ n levels stores n bits.
- Low resolution partitioning the window, W, of physical values a cell can assume into a small rather than large number of levels per cell) provides high reliability.
- Retention Retention of original physical levels induced in the flash memory cells despite time which has elapsed and despite previous erase/write cycles; retention is typically below 100% resulting in deterioration of original physical levels into present levels.
- Retention time The amount of time that data has been stored in a flash device, typically without, or substantially without, voltage having been supplied to the flash device i.e. the time which elapses between programming of a page and reading of the same page.
- Threshold level or “decision level” the voltage (e.g.) against which the charge level of a cell is measured.
- a cell may be said to store a particular digital n-tuple D if the charge level or other physical level of the cell falls between two threshold values T.
- Code rate ratio of redundancy bits to data bits in flash memory.
- Data cells cells storing data provided by host as opposed to "non-data cells" which do not store host-provided data, and may, for example, store instead error correction information, management information, redundancy information, spare bits or parity bits.
- Logical page a set of bits defined as a page typically having a unique page address, by a host external to a flash memory device.
- row and column refer to rows of cells and columns of cells, respectively and are not references to sub-divisions of a logical page.
- MSB is used herein to denote the bit which is programmed into a multi-level cell, storing several bits, first.
- LSB is used herein to denote the bit which is programmed into the multi-level cell, last.
- CSB is used herein to denote the bit which is programmed into a 3-level cell, storing 3 bits, second, i.e. after the MSB and before the LSB. It is appreciated that more generally, e.g. if the multi-level cell stores 4 or more levels, there are more than one CSBs and use of the term "CSB” herein, which implies that the cell is a 3-level cell, is merely by way of example and is not intended to be limiting.
- a logical page is a set of bytes which is meaningful to an application.
- the location of a logical page in memory is termed herein a physical page. This location may comprise certain cells in their entirety, or, more commonly, may comprise only one or some bits within certain cells.
- the locations of each of a sequence of logical pages (page 0, page 1, page 2,.7) within memory is pre-determined by a suitable mapping scheme mapping logical pages into the bits of the cells of a particular erase sector (block) in flash memory.
- Bit errors are those errors found in the physical page corresponding to a logical page, which typically are corrected using ECC (error correction code) such that the page is successfully reconstructed despite these errors.
- ECC error correction code
- reading threshold and “detection threshold” are used generally interchangeably.
- directed threshold errors refers to events in which a cell which was programmed to one program level is erroneously interpreted, upon performing a read operation, as being programmed to another program level.
- a directed threshold error is described by stating the index of the threshold lying between the cell's program level and the erroneously read program level and which is closest to the cell's actual program level, as well as the direction of the error, i.e. "right to left” if the cell was misinterpreted as being programmed to a program level residing to the left of the cell's program level, and "left to right” if the cell was misinterpreted as being programmed to a program level residing to the right of the cell's program level.
- Certain embodiments of the present invention seek to provide improved flash memory device. Certain embodiments of the present invention seek to provide inference methods in Flash Memory Devices based on analysis of bit error patterns. Certain embodiments of the present invention seek to provide a method for correcting at least one detection threshold for reading the data of at least one page within an erase sector of a flash memory device, the method comprising associating the bit errors of at least one previous successfully read page to corresponding directed threshold errors and choosing a corrected threshold based on the previous detection threshold and number of the directed threshold errors.
- Certain embodiments of the present invention seek to provide a method for associating at least one bit error of at least one successfully decoded page within an erase sector of a flash device to a corresponding directed threshold error. Certain embodiments of the present invention seek to provide a method for performing tracking of at least one detection threshold for reading the data of at least one page within an erase sector of a flash memory device wherein previously decoded pages are used.
- Certain embodiments of the present invention seek to provide a method for identifying read disturb in at least one erase sector of a flash memory device wherein at least one previously decoded page is used.
- a method for generating a set of at least one row-specific reading threshold for reading at least portions of pages of data within an erase sector of a flash memory device comprising predetermining at least one initial reading threshold, performing the following steps for at least one current logical page: generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and computing at least one row-specific reading threshold based on the bit error characterizing information and on a previous threshold initially comprising the initial threshold and subsequently comprising a row-specific reading threshold computed for a successfully reconstructed previous logical page; and reading at least a portion of the current logical page using the at least one row-specific reading threshold.
- the above row-specific method is performed locally, i.e. for local regions within a flash memory device being read, e.g. for each row in the flash memory, or for some individual rows, or for each of a number of sets each comprising a relatively small number of typically adjacent rows.
- the number of threshold errors from left to right with respect to the detection threshold is compared to the number of threshold errors from right to left with respect to the detection threshold, wherein the corrected detection threshold is modified according to the sign and magnitude of the difference between the two numbers of threshold errors.
- the number of directional threshold errors with respect to at least one detection threshold in the page is used to determine if the erase sector suffers from read disturb.
- the detection thresholds are corrected only for a subset of pages in the erase sector wherein the subset of pages is chosen such that the correction will be done on detection thresholds which were used on a subset of rows within an erase sector.
- thresholds are corrected only if the difference between the total error count associated with the decoding of the page and the total error count associated with the decoding of the previous page is larger than some number.
- the association between bit errors and threshold errors in CSB and/or LSB pages is done based on reading the corresponding MSB and/or CSB pages from the flash device.
- the association is done based on the corresponding MSB and/or CSB pages which are stored in a buffer.
- the bit error characterizing information comprises identification of a reading threshold associated with the bit error.
- the bit error characterizing information comprises a direction of the bit error.
- a reading threshold is associated with each bit error in that a wrong logical value is assigned to a bit when a physical value induced in the cell in which the bit resides, falls so far along one of the two tail ends of the voltage (e.g.) distribution of the logical value as to exceed the upper threshold of the programmed value or so as to fall below the lower threshold of the programmed value.
- the upper threshold is associated with the bit error and the direction of the bit error is termed "left to right”.
- the lower threshold is associated with the bit error and the direction of the bit error is termed "right to left”.
- a first number of threshold errors whose direction, with respect to the reading threshold, is from left to right is compared to a second number of threshold errors whose direction, with respect to the reading threshold, is from right to left, wherein the row-specific reading threshold depends upon at least one of the sign and magnitude of the difference between the first and second numbers of threshold errors.
- the method also comprises selecting a subset of rows within the erase sector; identifying a set of logical pages residing within the subset of rows; and performing the generating, computing and reading for the set of logical pages and for less than all pages in the erase sector.
- the generating, computing and reading are performed only for the set of logical pages.
- the reading thresholds are corrected only if the number of bit errors per page is in a process of change of at least a predetermined magnitude.
- the reading thresholds are corrected only if the difference between the number of bit errors encountered during reconstruction of the current page and the number of bit errors occurring during reconstruction of at least one previous page is larger than a predetermined number.
- the predetermined number is typically selected to be relatively large so that the reading threshold correction process is only initiated when a very significant rise in bit error frequency is detected. For example, if the page size is, say, 4K bytes, an increase in the number of bit errors per page of the order of magnitude of dozens or hundreds of bit errors might trigger a reading threshold correction process such as those shown and described herein.
- the generating is performed for at least one CSB page residing in a row corresponding to an MSB page also residing in the row, based at least partly on values read from the MSB page.
- the generating is performed for an LSB page residing in a row corresponding to an MSB and at least one CSB page also residing in the row, based at least partly on values read from at least one of the MSB and CSB pages.
- the generating performed for the CSB page is based at least partly on values read on-the-fly from the MSB page.
- the generating performed for the LSB page is based at least partly on values read on-the-fly from at least one of the MSB and CSB pages.
- the generating performed for the CSB page is based at least partly on stored values previously read from the MSB page. Further in accordance with certain embodiments of the present invention, the generating performed for the LSB page is based at least partly on stored values previously read from at least one of the MSB and CSB pages.
- the values read from the MSB and/or CSB pages may be read from a buffer which stored these pages, perhaps when they were originally read, or may be a re-read of a page which has already been read at least once either only for reading its own data, or also in order to perform the teachings of this invention, say, for a CSB page preceding the current page which is an LSB page.
- the buffer is typically located within a controller external to a flash memory device although alternatively it may be located within an internal controller.
- a method for using flash memory to store data comprising writing at least one page of data to the flash memory, reading the at least one page of data from the flash memory using a set of reading thresholds, including generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and subsequently, using the flash memory so as to take into account the bit error characterizing information.
- the bit error characterizing information comprises identification of a reading threshold which is associated with the bit error. Still further in accordance with certain embodiments of the present invention, the bit error characterizing information comprises a direction of the bit error.
- the using comprises reading at least one subsequent page of data so as to take into account the bit error characterizing information. Further in accordance with certain embodiments of the present invention, the using comprises detecting portions of the flash memory which suffer from read-disturb phenomenon based on the bit error characterizing information.
- portions of the flash memory which suffer from read-disturb phenomenon are detected rather than merely deducing that a particular portion of memory, e.g. erase sector, suffers from the phenomenon based on the number of times that portion, or a sub-portion e.g. page within it, has been read.
- the detecting comprises detecting an overly large number of bit errors whose source is a reading threshold which is closest, within the set of reading thresholds, to zero voltage, and whose direction is from left to right.
- a system for generating a set of at least one row-specific reading threshold for reading at least portions of pages of data within an erase sector of a flash memory device comprising apparatus for predetermining at least one initial reading threshold; a bit error analyzer operative, for at least one current logical page, to generate bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and a bit error-based threshold generator operative to compute at least one row-specific reading threshold based on the bit error characterizing information and on a previous threshold initially comprising the initial threshold and subsequently comprising a row-specific reading threshold computed for a successfully reconstructed previous logical page; and a flash memory cell reader operative to read at least a portion of the current logical page using the at least one row-specific reading threshold.
- a system for using flash memory to store data comprising apparatus for writing in flash memory operative to write at least one page of data to the flash memory; a bit error characterizing reader operative to read the at least one page of data from the flash memory using a set of reading thresholds, including generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and a bit error-based controller operative to control the flash memory so as to take into account the bit error characterizing information.
- processors Any suitable processor, display and input means may be used to process, display, store and accept information, including computer programs, in accordance with some or all of the teachings of the present invention, such as but not limited to a conventional personal computer processor, workstation or other programmable device or computer or electronic computing device, either general-purpose or specifically constructed, for processing; a display screen and/or printer and/or speaker for displaying; machine- readable memory such as optical disks, CDROMs, magnetic-optical discs or other discs; RAMs, ROMs, EPROMs, EEPROMs, magnetic or optical or other cards, for storing, and keyboard or mouse for accepting.
- the term "process” as used above is intended to include any type of computation or manipulation or transformation of data represented as physical, e.g. electronic, phenomena which may occur or reside e.g. within registers and /or memories of a computer.
- the above devices may communicate via any conventional wired or wireless digital communication means, e.g. via a wired or cellular telephone network or a computer network such as the Internet.
- the apparatus of the present invention may include, according to certain embodiments of the invention, machine readable memory containing or otherwise storing a program of instructions which, when executed by the machine, implements some or all of the apparatus, methods, features and functionalities of the invention shown and described herein.
- the apparatus of the present invention may include, according to certain embodiments of the invention, a program as above which may be written in any conventional programming language, and optionally a machine for executing the program such as but not limited to a general purpose computer which may optionally be configured or activated in accordance with the teachings of the present invention.
- Fig. 1 is a simplified block diagram of a flash memory system constructed and operative in accordance with certain embodiments of the present invention
- Fig. 2 is a simplified functional block diagram illustration of the bit-error analyzing controller 102 of Fig. 1, according to certain embodiments of the present invention
- Fig. 3 is a theoretical graph of voltage distributions conditional on program levels which is useful in understanding certain embodiments of the present invention
- Fig. 4A - 4C taken together, are a diagram depicting mapping from data bits to program levels and threshold crossover errors which is useful in understanding certain embodiments of the present invention
- Figs. 5A - 5B taken together, form a simplified flowchart illustration of a method for correcting reading thresholds by tracking bit error patterns, which method may for example be performed by the system of Figs. 1 - 2, the method being operative according to certain embodiments of the present invention
- Fig. 6 is a simplified flowchart illustration of a method for performing the "bit error to threshold error" step in Figs. 5A - 5B for an MSB page, the method identifying, for each bit error, a reading threshold associated therewith and a direction thereof;
- Fig. 7 is a simplified flowchart illustration of a method for performing the "bit error to threshold error" step in Figs. 5A - 5B for a CSB page, assuming, which of course need not be the case, that the cells in each page are 3-level cells (i.e. assuming for simplicity that there is only one CSB page), the method identifying, for each bit error, a reading threshold associated therewith and a direction thereof;
- Figs. 8A - 8B taken together, form a simplified flowchart illustration of a method for performing the "bit error to threshold error" step in Figs. 5A - 5B for an LSB page, the method identifying, for each bit error, a reading threshold associated therewith and a direction thereof;
- Fig. 9 is a simplified flowchart illustration of a method for performing the threshold updating step in Figs. 5A - 5B for either an MSB, CSB, or an LSB page;
- Fig. 10 is a simplified flowchart illustration of a method for read disturb identification by tracking bit error patterns, the method being operative according to certain embodiments of the present invention
- Fig. 1 1 is a simplified flowchart illustration of a modification of the method of Figs. 5A - 5B in which tracking activation is diluted;
- Fig. 12 is a simplified flowchart illustration of a method for accessing the page-to- row lookup table corresponding to the mapping type
- Fig. 13 is a table comprising a mapping between logical pages and physical pages which is useful in understanding certain embodiments of the present invention
- Fig. 14 is a table comprising another mapping between logical pages and physical pages which is useful in understanding certain embodiments of the present invention.
- Fig. 15 is a look-up-table based on the mapping in Fig. 13 which associates for each page index the corresponding row index where the logical page resides, and which is useful in understanding certain embodiments of the present invention
- Fig. 16 is a look-up-table based on the mapping in Fig. 14 which associates for each page index the corresponding row index where the logical page resides, and which is useful in understanding certain embodiments of the present invention
- Fig. 17 is a simplified flowchart illustration of a modification of the method of
- Fig. 18 is a generalized flowchart illustration of a method of operation of the system of Figs. 1 - 2, the method being operative according to certain embodiments of the present invention.
- Fig. 19 is a simplified flowchart illustration of a method for using flash memory to store data, the method being operative in accordance with certain embodiments of the present invention.
- row and column as used herein are intended to include rows of cells and columns of cells, respectively and are not references to sub-divisions of a logical page.
- MSB as used herein is intended to include the bit which is programmed into a multi-level cell, storing several bits, first.
- LSB as used herein is intended to include the bit which is programmed into the multi-level cell, last.
- CSB as used herein is intended to include the bit which is programmed into a 3-level cell, storing 3 bits, second, i.e. after the MSB and before the LSB. It is appreciated that more generally, e.g. if the multi-level cell stores 4 or more levels, there are more than one CSBs and use of the term "CSB” herein, which implies that the cell is a 3-level cell, is merely by way of example and is not intended to be limiting.
- a logical page as used herein is intended to include a set of bytes which is meaningful to an application.
- the location of a logical page in memory is termed herein a physical page. This location may comprise certain cells in their entirety, or, more commonly, may comprise only one or some bits within certain cells.
- the locations of each of a logical sequence of logical pages (page 0, page 1, page 2,.7) within memory is pre-determined by a suitable mapping scheme mapping logical pages into the bits of the cells of a particular erase sector (block) in flash memory.
- Bit errors as used herein is intended to include those errors found in the physical page corresponding to a logical page, which typically are corrected using ECC (error correction code) such that the page is successfully reconstructed despite these errors.
- ECC error correction code
- Fig. 1 is a simplified block diagram of a flash memory system constructed and operative in accordance with certain embodiments of the present invention.
- the flash memory system of Fig. 1 includes a host or outside application 100 which interfaces, via an interface controller 102, with a flash memory device 105.
- An internal microcontroller 1 10 typically manages the functional units of the flash memory device 105.
- the storage portion of the flash memory device includes one or more typically many erase sectors 120 each storing one or more typically many physical pages 130 each including one or more typically many cells 140 having more than one possible state such that logical values may be stored therein.
- Erasing circuitry 150 is provided to erase data from cells, writing circuitry 160 writes data into cells, and reading circuitry 170 reads data from cells.
- FIG. 1 is a simplified functional block diagram illustration of the bit-error analyzing controller 102 of Fig. 1, according to certain embodiments of the present invention.
- the controller 102 may include a bit error characterization block 200 which provides information regarding bit errors' characteristics, particularly joint characteristics, to application functionalities such as but not limited to a read threshold computation unit 210 and/or a read-disturb event finder 220.
- a buffer 230 is provided which is useful for reading MSB and CSB pages as described in detail herein.
- the buffer 230 serves the characterizer of bit errors 200 which in turn serves read threshold computation unit 210 and/or read-disturb event finder 220.
- the system of Figs. 1 - 2 is particularly suitable for generating a set of at least one row-specific reading threshold for reading at least portions of pages of data within an erase sector of a flash memory device.
- This method may comprise some or all of the following steps, as shown in Fig. 18:
- Step 3010 predetermining at least one initial reading threshold
- Step 3020 performing steps 3030 and 3040 for each of at least one current logical pages.
- Step 3030 generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page.
- Step 3040 computing at least one row-specific reading threshold based on the bit error characterizing information and on a previous threshold initially comprising the initial threshold and subsequently comprising a row-specific reading threshold computed for a successfully reconstructed previous logical page.
- Step 3050 When steps 3030 and 3040 have been performed for a set of current logical pages, step 3050 is performed, involving reading at least a portion of the current logical page using the at least one row-specific reading threshold.
- flash memory devices store information as charge in "cells", each made of either a floating gate transistor or an NROM transistor.
- each cell stores only one bit of information.
- Multi-level cell (MLC) devices can store more than one bit per cell by choosing between multiple levels of electrical charge to apply to the floating gates of their cells.
- the amount of charge (also known as charge level) is then measured by a detector, by comparing the voltage of the transistor gate (also known as charge level and denoted V T ) to a decision threshold voltage (also known as charge level boundary point and denoted V D ).
- the amount of charge is then used to determine the programmed level (logical value) of the cell.
- Prior art Fig. 3 illustrates an example of the eight separate probability distributions of a cell which can be programmed with one of eight corresponding program levels (1 1 1, 1 10, 100, 101, 001, 000, 010, and 011, respectively).
- the Y-axis represents the probability that the cell is programmed to the corresponding level, given the value of the charge level V ⁇ (represented by the x- axis).
- a particular feature of certain embodiments of the present invention is that changes in the distributions of the programming lobes illustrated in Fig. 3 are tracked between pages, using a suitable indicator of such changes such as bit error characteristics including associated threshold and direction of each bit error, all as described in detail below.
- the cell's programmed level may be determined using several methods. One method is to apply a voltage to the cell's gate and measure if the cell conducts current. The cell has a certain threshold voltage such that if voltage above that threshold is applied to the gate, the gate will conduct. Below that threshold voltage the gate will not conduct current (or will conduct a small amount of current, below a certain demarcation level).
- the charge may be inferred by dete ⁇ nining at which voltage the cell starts to conduct current.
- the programmed level is determined by iteratively applying different voltages to the gate and measuring whether the cells conduct or not. Another method is based on the fact that when applying a voltage above the threshold voltage, the cell conducts current and the amount of current depends on the difference between the applied voltage and the threshold voltage. As the threshold voltage changes as a function of the amount of charge in the cell, the programmed level may be inferred by measuring the current going through the cell.
- the programmed level may be obtained by simultaneously comparing the conducted current with a given set of fixed currents distinguishing between all programmed levels.
- each cell's programmed level is determined by simultaneously comparing the VT level against several decision threshold levels (detection thresholds). For example, if there are eight possible programmed levels, the cell's V T is simultaneously compared against seven decision threshold levels which divide the voltage axis into eight regions, as demonstrated in Fig. 3.
- L-I decision threshold levels are employed. As the probability distributions extend beyond the decision threshold levels, there is a probability of detection error, i.e. detecting the wrong program level. In order to minimize the detection error, one wishes to set the decision threshold levels optimally.
- the optimal placement of the decision thresholds levels in terms of minimizing the detection error probability generally depends on the probability distribution associated with the V ⁇ level of the cells.
- the statistical behavior of the cells' V T level can be approximated by Gaussian distributions.
- the optimal placement of the detection threshold for the Gaussian case is a known function of the means and standard deviations (STDs) of the Gaussian distributions. In other words, knowledge of good decision thresholds (assuming the Gaussian assumption is correct) is possible if the means and STDs of the cells' V x distributions are known.
- this situation calls for a training stage in which the flash device's controller learns the "state" of the page/block and determines a set of decision thresholds which will yield preferably as little detection errors as possible when used to read the page. Since some variations exist in the statistics of the program levels between different blocks within one flash device, and between different pages within one erase sector, it is appreciated that one cannot hope to find a single choice of thresholds which will be appropriate, i.e. yield a sufficiently high uncoded bit error rate (UBER), for all the pages in the flash device.
- UBER uncoded bit error rate
- One solution is to use the training process for every page to be read, or for every page for which it is suspected that the detection thresholds previously obtained are not sufficiently accurate. Depending on the complexity of the training process, such a solution might be too costly, and might jeopardize the feasibility of certain flash applications.
- Certain embodiments of this invention include a way for adapting the detection thresholds from one page to the next in such a way which considerably limits the number of training operations employed to read an entire population of blocks of a flash device.
- the adaptation is done either without or with very little additional reading operations from the flash device.
- the adaptation is done based on the bit error pattern obtained after successful decoding of the error correcting code (ECC).
- ECC error correcting code
- Read disturb is a situation where the voltages applied to the row and column of a target memory floating gate cell in order to perform the read operation, cause unwanted programming to erased cells which lie on the same column as the target cell. This unwanted programming accumulates over time after successive read operations to the degree of causing cells in the erased state to be in programmed states. Certain embodiments of this invention use the bit error patterns to identify a block which is suffering from a severe read disturb and if left unchanged might reach a state where the data stored in it becomes undetectable.
- tracking of the changes in the detection thresholds which occur between successive pages in a flash array is provided.
- the tracking is performed by analyzing the asymmetry between errors which occur due to cells' V 1 levels crossing the detection thresholds from left to right and errors which occur due to cells' V T levels crossing the detection thresholds from right to left.
- the detection thresholds are modified according to the sign and magnitude of the difference between the two types of threshold errors.
- the tracking operation guarantees that detection thresholds adapt to the changes in the threshold voltage distributions without the need to perform multiple training procedures which may be costly in terms of flash read operations.
- Certain embodiments of this invention seek to perform the above functionalities in a manner which saves memory requirements e.g. by performing read operations from the flash "on the fly” in order to associate bit errors to the threshold errors.
- Certain embodiments of this invention seek to identify erase sectors which suffer from read disturb. This is done by identifying erased cells which have become programmed due to repetitive read operations.
- a threshold error association mechanism is used here to identify programming of erased cells by checking the number of directed threshold errors from left to right with respect to the detection threshold closest to the erased level.
- the pages of one block are read sequentially.
- Fig. 4 the mapping between data bits and cell program levels is depicted in prior art Fig. 4.
- Each combination of bits corresponding to a specific selection of MSB, CSB, and LSB is mapped to one of eight program levels as shown in Fig. 4.
- the dashed vertical lines mark the reading thresholds.
- a single threshold is used. Cells which conduct current when this threshold is applied to their gate are interpreted as having their MSB equal to 1, while the remaining cells are identified as having their MSB equal 0.
- the reading of the CSB employs two thresholds.
- Cells which conduct when the left threshold is applied to them and cells which do not conduct (even) if the right threshold is applied to them are identified as having their CSB equal 1, while the cells which do not conduct when the left threshold is applied to them but conduct current when the right threshold is applied to them are interpreted as having their CSB equal 0.
- For the LSB four thresholds are employed. Cells whose V T lies between Ti and T 2 or between T 3 and T 4 are interpreted as having their LSB equal 0, while for the remaining cells, the LSB is read as 1.
- the curved arrows above each detection threshold designate errors resulting from threshold voltages of some cells appearing in the detection regions of their neighboring cells. For example, assume a cell was programmed to level 3, but due to programming error and/or retention effects, the actual threshold voltage at the time the cell is to be read is just to the left of Ti in the second graph of Fig. 4. When Ti is applied to this cell, it will conduct current and its CSB bit will be erroneously interpreted as a 1 even though its CSB was 0. Such an error event is marked by the bold solid curved arrow above Ti in the second graph of Fig. 4. Similarly, the remaining dashed curved arrows designate threshold errors from left to right, while the solid arrows mark errors from right to left. These threshold errors are termed herein "directed threshold errors”.
- the tracking process is based on the assumption that when the thresholds are not optimally placed, e.g. due to the shifting of the means of the program levels between successive rows, an asymmetry is present between the errors from left to right and the errors from right to left.
- the tracking process may proceed as depicted in Figs. 5A - 5B. It is appreciated that Tl - T4 in Figs. 5A - 5B are defined by Fig. 4.
- the corrected page bits are passed to the tracking block along with the location of the erroneous bits, the page bit type (MSB, CSB, or LSB), and the set of thresholds which was used to read the page. If the page is an MSB page, only one threshold is supplied. If the page is a CSB page, 2 thresholds are given, and finally, tracking of an LSB page uses knowledge of four detection thresholds.
- the process maps each bit error to a directed threshold error event and updates an appropriate counter. For each threshold, two counters are used, one counting threshold errors from left to right, and another which counts errors from right to left. Once all the errors in the page are processed, the corresponding thresholds are corrected in the appropriate direction as a function of the asymmetry in the number of threshold errors. In one embodiment, the difference between the threshold errors from left to right and from right to left is computed for every threshold, and according to the difference's sign and magnitude an appropriate quantity is either added to or subtracted from the original threshold. The procedure described in Figs. 5A - 5B is repeated for every page which is successfully decoded.
- Fig. 6 is a simplified flowchart illustration of a method for performing the "bit error to threshold error" step in Figs. 5A - 5B for an MSB page, the method identifying, for each bit error, a reading threshold associated therewith and a direction thereof.
- Fig. 7 is a simplified flowchart illustration of a method for performing the "bit error to threshold error” step in Figs.
- FIGs. 8A - 8B taken together, form a simplified flowchart illustration of a method for performing the "bit error to threshold error" step in Figs. 5A - 5B for an LSB page, the method identifying, for each bit error, a reading threshold associated therewith and a direction thereof.
- each bit error of the form 0-> 1 corresponds to a threshold error from right to left
- each bit error of the form l->0 is a result of a threshold error from left to right.
- the mapping depends on the corresponding bit in the MSB page residing in the same physical row. For instance, a bit error event of the form 0->l can be interpreted as a right-to-left threshold error event of threshold Ti, if the MSB bit equals 1 , or as a left-to-right threshold error event of threshold T 2 , if the MSB bit equals 0.
- the mapping of bit errors to threshold error events for an LSB page typically comprises using knowledge of the MSB and CSB bits in the corresponding cells residing in the same physical row.
- a buffer may be used in order to store the values of the MSB and CSB pages for future tracking of CSB and LSB pages.
- a buffer of length at least d may be used to guarantee that upon decoding of the LSB page, the MSB page of the same row is available.
- the read procedure involves the application of certain voltages to the word line corresponding to the row address of the read cell as well as the bit line corresponding to the column address of the cell. These voltages are of the same kind as those which are applied during programming, only lower in magnitude.
- the voltage applied to the bit line may induce a small charge transfer to the floating gate. While the charge transfer which occurs in any individual read operation is limited due to the relatively low voltage applied to the bit line, the cumulative effect of many (-100,000) read operations might cause a significant charge increase in the floating gate. This phenomenon may cause cells which are in the erased state and which share the same bit line as the cell being read to become programmed. Furthermore, since all the cells along a bit line are affected by this disturb, the excessive reading of even a single page might have a deleterious effect on the entire block.
- Any suitable action may be initiated if a read-disturb phenomenon has been detected.
- the content of the block can be copied to another available block, and the block suffering from read disturb can be erased and used subsequently as an available block. Performance trade-off considerations according to certain embodiments of the present invention are now described in detail.
- some previously read pages may be kept in appropriate buffers.
- the length of the buffer may depend on the particular order in which logical pages are mapped to physical pages within an erase sector. In some applications, the buffer might impose limitations on the scope of these applications.
- the tracking is employed only on pages which lie in rows which are multiples of a certain integer values (e.g. 2, 3 ).
- a certain integer values e.g. 2, 3 .
- the advantages of this approach are twofold. First, the processing of the bit errors is circumvented in some of the rows in the block, leading to saving in processing times. Second, the MSB and CSB pages which belong to the untracked rows need not be saved in the buffer, leading to savings in the system's memory requirements. An example of this procedure is shown in Fig. 1 1.
- the mapping between logical pages and physical pages is such that in order to implement the tracking procedure a large number of pages is employed such as several dozen pages. It is therefore sometimes advantageous to trade-off memory resources with time resources.
- the buffer is relinquished and replaced by occasional read operations from the flash. Based on the reasoning described above, it is expected that tracking will hardly be employed within the block. Tracking is typically employed when the distributions of the program levels have changed significantly with respect to the ones which were obtained last. Such a situation can be identified by checking if the total number of errors has significantly increased with respect to the previous row or page.
- Example implementations Two specific implementations of the invention shown and described herein are now described, by way of example, which pertain respectively to different mappings of a sequence of logical pages numbered for convenience 0, 1, 2,... each including a multiplicity of data bytes such as 4K data bytes, into an erase block including an array of physical cells arranged in physical rows numbered for convenience 0, 1, 2,... and physical columns.
- Mapping 1 pertains to a mapping scheme termed Mapping 1 and described below
- Implementation 2 pertains to a mapping scheme termed Mapping 2 and described below. It is appreciated that alternatively, any other suitable mappings may be used.
- Mapping 1 comprises the following mapping scheme: A sequence of logical pages is mapped into an erase block including an array of physical multi-level e.g. 3-level cells as follows:
- Logical page 0 is stored in the MSBs of cells 0, 2, 4 etc. in row 0.
- Logical page 1 is stored in the MSBs of cells 1, 3, 5 etc. in row 0.
- Logical page 2 is stored in the MSBs of cells 0, 2, 4, etc. in row 1.
- Logical page 3 is stored in the MSBs of cells 1, 3, 5, etc. in row 1.
- Logical page 4 is stored in the MSBs of cells 0, 2, 4, etc. in row 2.
- Logical page 5 is stored in the MSBs of cells 1, 3, 5, etc. in row 2.
- Logical page 6 is stored in the MSBs of cells 0, 2, 4, etc. in row 3.
- Logical page 7 is stored in the MSBs of cells 1, 3, 5, etc. in row 3.
- Logical page 8 is stored in the MSBs of cells 0, 2, 4, etc. in row 4.
- Logical page 9 is stored in the MSBs of cells 1, 3, 5, etc. in row 4.
- Logical page 10 is stored in the CSBs of cells 0, 2, 4, etc. in row 0.
- Logical page 11 is stored in the CSBs of cells 1, 3, 5, etc. in row 0.
- Logical page 12 is stored in the MSBs of cells 0, 2, 4, etc. in row 5.
- Logical page 13 is stored in the MSBs of cells 1, 3, 5, etc. in row 5.
- Logical page 14 is stored in the CSBs of cells 0, 2, 4, etc. in row 1.
- Logical page 15 is stored in the CSBs of cells 1, 3, 5, etc. in row 1.
- Example implementation 1 is now described. As for tracking an MSB page, the implementation is not dependent on the mapping and is depicted in Fig. 6.
- the step 705 comprises looking in the table appearing in Fig. 16, and finding the row in which the page resides. Then, the row number is used to access the table in Fig. 14 and obtain the page number of the corresponding MSB page residing in the same row. The page itself is located in the buffer appearing in Fig. 2.
- the step 810 comprises looking in the table appearing in Fig. 16, and finding the row in which the page resides. Then, the row number is used to access the table in Fig. 14 and obtain the page numbers of the corresponding MSB and CSB pages residing in the same row. The pages themselves are located in the buffer appearing in Fig. 2.
- Mapping 2 comprises the following mapping scheme:
- a sequence of logical pages is mapped into an erase block including an array of physical multi-level e.g. 3-level cells as follows:
- Logical page 0 is stored in the MSBs of cells 0, 2, 4 etc. in row 0.
- Logical page 1 is stored in the MSBs of cells 1, 3, 5 etc. in row 0.
- Logical page 2 is stored in the CSBs of cells 0, 2, 4, etc. in row 0.
- Logical page 3 is stored in the CSBs of cells 1, 3, 5, etc. in row 0.
- Logical page 4 is stored in the LSBs of cells 0, 2, 4, etc. in row 0.
- Logical page 5 is stored in the LSBs of cells 1, 3, 5, etc. in row 0.
- Logical page 6 is stored in the MSBs of cells 0, 2, 4, etc. in row 1.
- Logical page 7 is stored in the MSBs of cells 1, 3, 5, etc. in row 1.
- step 705 comprises looking in the table appearing in
- step 810 comprises looking in the table appearing in Fig. 15. and finding the row in which the page resides. Then, the row number is used to access the table in Fig. 13 and obtain the page numbers of the corresponding MSB and CSB pages residing in the same row.
- the pages themselves are located in the buffer appearing in Fig. 2.
- Fig. 18 is a generalized flowchart illustration of a method of operation of the system of Figs. 1 - 2, the method being operative according to certain embodiments of the present invention.
- Step 3010 predetermine at least one initial reading threshold.
- Step 3020 perform steps 3030 and 3040 for each of at least one current logical pages.
- Step 3030 generate bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page.
- Step 3040 compute at least one row-specific reading threshold based on the bit error characterizing information and on a previous threshold initially comprising the initial threshold and subsequently comprising a row-specific reading threshold computed for a successfully reconstructed previous logical page.
- Step 3050 When steps 3030 and 3040 have been performed for a set of current logical pages, step 3050 is performed, involving reading at least a portion of the current logical page using the at least one row-specific reading threshold.
- Fig. 19 is a simplified flowchart illustration of a method for using flash memory to store data, the method being operative in accordance with certain embodiments of the present invention.
- the method of Fig. 19 typically comprises some or all of the following steps, suitably ordered e.g. as shown: Step 3110: Write at least one page of data to flash memory Step 3120: Read at least one page of data from flash memory using a set of reading thresholds, including generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page
- Step 3130 Subsequently, use flash memory so as to take into account bit error characterizing information.
- software components of the present invention including programs and data may, if desired, be implemented in ROM (read only memory) form including CD-ROMs, EPROMs and EEPROMs, or may be stored in any other suitable computer-readable medium such as but not limited to disks of various kinds, cards of various kinds and RAMs.
- ROM read only memory
- EEPROM electrically erasable programmable read-only memory
- Components described herein as software may, alternatively, be implemented wholly or partly in hardware, if desired, using conventional techniques.
- Any data described as being stored at a specific location in memory may alternatively be stored elsewhere, in conjunction with an indication of the location in memory with which the data is associated.
- the same may be stored within the flash memory device's internal microcontroller or within a microcontroller interfacing between the flash memory device and the host, and an indication may be stored of the specific page or erase sector associated with the cells.
- the flash controlling apparatus controls a flash memory array and may comprise either a controller external to the flash array or a microcontroller on-board the flash array or otherwise incorporated therewithin.
- flash memory arrays examples include Samsung's K9XXG08UXM series, Hynix' HY27UK08BGFM Series, Micron's MT29F64G08TAAWP or other arrays such as but not limited to NOR or phase change memory.
- controllers which are external to the flash array they control include STMicroelectrocincs's ST7265x microcontroller family, STMicroelectrocincs's ST72681 microcontroller, and SMSCs USB97C242, Traspan Technologies' TS-4811, Chipsbank CBM2090/CBM1 190.
- Example of commercial IP software for Flash file systems are: Denali's SpectraTM NAND Flash File System, Aarsan's NAND Flash Controller IP Core and Arasan's NAND Flash File System. It is appreciated that the flash controller apparatus need not be NAND-type and can alternatively, for example, be NOR-type or phase change memory-type.
- Flash controlling apparatus whether external or internal to the controlled flash array, typically includes the following components: a Memory Management/File system, a NAND interface (or other flash memory array interface), a Host Interface (USB, SD or other), error correction circuitry (ECC) typically comprising an Encoder and matching decoder, and a control system managing all of the above.
- a Memory Management/File system typically includes the following components: a Memory Management/File system, a NAND interface (or other flash memory array interface), a Host Interface (USB, SD or other), error correction circuitry (ECC) typically comprising an Encoder and matching decoder, and a control system managing all of the above.
- ECC error correction circuitry
- the present invention may for example interface with or modify, as per any of the embodiments described herein, one, some or all of the above components.
Abstract
A method for generating a set of at least one row-specific reading threshold for reading at least portions of pages of data within an erase sector of a flash memory device, the method comprising predetermining at least one initial reading threshold; performing the following steps for at least one current logical page: generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and computing at least one row-specific reading threshold based on said bit error characterizing information and on a previous threshold initially comprising said initial threshold and subsequently comprising a row-specific reading threshold computed for a successfully reconstructed previous logical page; and reading at least a portion of said current logical page using said at least one row-specific reading threshold.
Description
APPARATUS AND METHODS FOR GENERATING ROW-SPECIFIC READING
THRESHOLDSIN FLASH MEMORY
REFERENCE TO CO-PENDING APPLICATIONS
Priority is claimed from the following co-pending applications: US Provisional Application No. 61/129,608, filed July 8, 2008 and entitled "A Method for Acquiring and Tracking Detection Thresholds in Flash Devices", US Provisional Application No. 60/996,782, filed December 5, 2007 and entitled "Systems and Methods for Using a Training Sequence in Flash Memory", US Provisional Application No. 61/064,853, filed March 31, 2008 and entitled "Flash Memory Device with Physical Cell Value Deterioration Accommodation and Methods Useful in Conjunction Therewith", US Provisional Application No. 61/006,805, filed January 31, 2008 and entitled "A Method for Extending the Life of Flash Devices" and US Provisional Application No. 61/071,465, filed April 30, 2008 and entitled "Systems and Methods for Temporarily Retiring Memory Portions".
Other co-pending applications include: US Provisional Application No. 60/960,207, filed September 20, 2007 and entitled "Systems and Methods for Coupling Detection in Flash Memory", US Provisional Application No. 61/071,467, filed April 30, 2008 and entitled "Improved Systems and Methods for Determining Logical Values of Coupled Flash Memory Cells", US Provisional Application No. 60/960,943, filed October 22, 2007 and entitled "Systems and methods to reduce errors in Solid State Disks and Large Flash Devices" and US Provisional Application No. 61/071,469, filed April 30, 2008 and entitled "Systems and Methods for Averaging Error Rates in Non- Volatile Devices and Storage Systems", US Provisional Application No. 60/996,027, filed October 25, 2007 and entitled "Systems and Methods for Coping with Variable Bit Error Rates in Flash Devices", US Provisional Application No. 61/071,466, filed April 30, 2008 and entitled "Systems and Methods for Multiple Coding Rates in Flash Devices", US Provisional Application No. 61/006,120, filed December 19, 2007 and entitled "Systems and Methods for Coping with Multi Stage Decoding in Flash Devices", US Provisional Application No. 61/071,464, filed April 30, 2008 and entitled "A Decoder
Operative to Effect A Plurality of Decoding Stages Upon Flash Memory Data and Methods Useful in Conjunction Therewith", US Provisional Application No. 61/006,385, filed January 10, 2008 and entitled "A System for Error Correction Encoder and Decoder Using the Lee Metric and Adapted to Work on Multi-Level Physical Media", US Provisional Application No. 61/064,995, filed April 8, 2008 and entitled "Systems and Methods for Error Correction and Decoding on Multi-Level Physical Media", US Provisional Application No. 60/996,948, filed December 12, 2007 and entitled "Low Power BCH/RS Decoding: a Low Power Chien-Search Implementation", US Provisional Application No. 61/071,487, filed May 1, 2008 and entitled "Chien-Search System Employing a Clock-Gating Scheme to Save Power for Error Correction Decoder and other Applications", US Provisional Application No. 61/071,468, filed April 30, 2008 and entitled "A Low Power Chien-Search Based BCH/RS Recoding System for Flash Memory, Mobile Communications Devices and Other Applications", US Provisional Application No. 61/006,806, filed January 31, 2008 and entitled "Systems and Methods for using a Erasure Coding in Flash memory", US Provisional Application No. 61/071,486, filed May 1, 2008 and entitled "Systems and Methods for Handling Immediate Data Errors in Flash Memory", US Provisional Application No. 61/006,078, filed December 18, 2007 and entitled "Systems and Methods for Multi Rate Coding in Multi Level Flash Devices", US Provisional Application No. 61/064,923, filed April 30, 2008 and entitled "Apparatus For Coding At A Plurality Of Rates In Multi-Level Flash Memory Systems, And Methods Useful In Conjunction Therewith", US Provisional Application No. 61/064,760, filed March 25, 2008 and entitled "Hardware efficient implementation of rounding in fixed-point arithmetic", US Provisional Application No. 61/071,404, filed April 28, 2008 and entitled "Apparatus and Methods for Hardware- Efficient Unbiased Rounding", US Provisional Application No. 61/136,234, filed August 20, 2008 and entitled "A Method Of Reprogramming A Non-Volatile Memory Device Without Performing An Erase Operation", US Provisional Application No. 61/129,414, filed June 25, 2008 and entitled "Improved Programming Speed in Flash Devices Using Adaptive Programming", and several other co-pending patent applications being filed concurrently (same day).
FIELD OF THE INVENTION
The present invention relates generally to flash memory devices.
BACKGROUND OF THE INVENTION
Conventional flash memory technology is described in the following publications inter alia: [1] Paulo Cappelletti, Clara Golla, Piero Olivo, Enrico Zanoni, "Flash Memories", Kluwer Academic Publishers, 1999.
[2] G. Campardo, R. Micheloni, D. Novosel, "VLSI-Design of Non- Volatile Memories", Springer Berlin Heidelberg New York, 2005.
Other relevant technologies and state of the art systems are described in the following documents:
[3] G. Proakis, "Digital Communications," 3rd ed., New York: McGraw-Hill, 1995. [4] P. Cappelletti et al., "Flash Memories," Kluwer, 1999.
"Read-disturb" is a known phenomenon whereby following a great many read operations performed on one or more particular physical pages within an erase sector, there is a deterioration in the quality of those physical pages or more typically in the quality of the entire erase sector. Typically, un-programmed cells tend to behave as though they were programmed, causing read errors.
The disclosures of all publications and patent documents mentioned in the specification, and of the publications and patent documents cited therein directly or indirectly, are hereby incorporated by reference.
SUMMARY OF THE INVENTION
The following terms may be construed either in accordance with any definition thereof appearing in the prior art literature or in accordance with the specification, or as follows:
Bit error rate (BER) = a parameter that a flash memory device manufacturer commits to vis a vis its customers, expressing the maximum proportion of wrongly read bits (wrongly read bits/ total number of bits) that users of the flash memory device need to expect at any time during the stipulated lifetime of the flash memory device e.g. 10 years.
Block = a set of flash memory device cells which must, due to physical limitations of the flash memory device, be erased together. Also termed erase sector, erase block.
Cell: A component of flash memory that stores one bit of information (in single-level cell devices) or n bits of information (in a multi-level device having 2 exp n levels). Typically, each cell comprises a floating-gate transistor, n may or may not be an integer. "Multi-level" means that the physical levels in the cell are, to an acceptable level of certainty, statistically partitionable into multiple distinguishable regions, plus a region corresponding to zero, such that digital values each comprising multiple bits can be represented by the cell. In contrast, in single-level cells, the physical levels in the cell are assumed to be statistically partitionable into only two regions, one corresponding to zero and one other, non-zero region, such that only one bit can be represented by a single-level cell.
Charge level: the measured voltage of a cell which reflects its electric charge.
Cycling: Repeatedly writing new data into flash memory cells and repeatedly erasing the cells between each two writing operations.
Decision regions: Regions extending between adjacent decision levels, e.g. if decision levels are 0, 2 and 4 volts respectively, the decision regions are under 0 V, 0 V - 2 V, 2V - 4 V, and over 4 V.
Demapping: basic cell-level reading function in which a digital n-tuple originally received from an outside application is derived from a physical value representing a physical state in the cell having a predetermined correspondence to the digital n-tuple.
Digital value or "logical value": n-tuple of bits represented by a cell in flash memory capable of generating 2 exp n distinguishable levels of a typically continuous physical value such as charge , where n may or may not be an integer.
Erase cycle: The relatively slow process of erasing a block of cells (erase sector), each block typically comprising more than one page, or, in certain non-flash memory devices, of erasing a single cell or the duration of so doing. An advantage of erasing cells collectively in blocks as in flash memory, rather than individually, is enhanced programming speed: Many cells and typically even many pages of cells are erased in a single erase cycle.
Erase-write cycle: The process of erasing a block of cells (erase sector), each block typically comprising a plurality of pages, and subsequently writing new data into at least some of them. The terms "program" and "write" are used herein generally interchangeably.
Flash memory: Non-volatile computer memory including cells that are erased block by block, each block typically comprising more than one page, but are written into and read from, page by page. Includes NOR-type flash memory, NAND-type flash memory, and PRAM, e.g. Samsung PRAM, inter alia, and flash memory devices with any suitable number of levels per cell, such as but not limited to 2, 4, or 8.
Logical page: a portion of typically sequential data, whose amount is typically less than or equal to a predetermined amount of data defined to be a pageful of data, which has typically been defined by a host (data source/destination) or user thereof, as a page, and which is sent by the host to a flash memory device for storage and is subsequently read by the host from the flash memory device.
Mapping: basic cell-level writing function in which incoming digital n-tuple is mapped to a program level by inducing a program level in the cell, having a predetermined correspondence to the incoming logical value. Physical Page = A portion, typically 512 or 2048 or 4096 bytes in size, of a flash memory e.g. a NAND or NOR flash memory device. Writing and reading is typically performed physical page by physical page, as opposed to erasing which can be performed only erase sector by erase sector. A few bytes, typically 16 - 32 for every 512 data bytes are associated with each page (typically 16, 64 or 128 per page), for storage of error correction information. A typical block may include 32 512-byte pages or 64 2048-byte pages. Alternatively, a physical page is an ordered set (e.g. sequence or array) of flash memory cells which are all written in simultaneously by each write operation, the set typically comprising a predetermined number of typically physically adjacent flash memory cells containing actual data written by and subsequently read by the host, as well as, typically error correction information and back pointers used for recognizing the true address of a page.
Precise read, soft read: Cell threshold voltages are read at a precision (number of bits) greater than the number of Mapping levels (2Λn). The terms precise read or soft read are interchangeable. In contrast, in "hard read", cell threshold voltages are read at a precision (number of bits) smaller than, or equal to, the number of mapping levels (2Λn where n = number of bits per cell).
Present level, Charge level: The amount of charge in the cell. The Amount of charge currently existing in a cell, at the present time, as opposed to "program level", the amount of charge originally induced in the cell (i.e. at the end of programming).
Program: same as "write".
Program level (programmed level, programming level): amount of charge originally induced in a cell to represent a given logical value, as opposed to "present level".
Reliability: Reliability of a flash memory device may be operationalized as the probability that a worst-case logical page written and stored in that device for a predetermined long time period such as 10 years will be successfully read i.e. that sufficiently few errors, if any, will be present in the physical page/s storing each logical page such that the error code appended to the logical page will suffice to overcome those few errors.
Reprogrammability (Np): An aspect of flash memory quality. This is typically operationalized by a reprogrammability parameter, also termed herein "Np", denoting the number of times that a flash memory can be re-programmed (number of erase-write cycles that the device can withstand) before the level of errors is so high as to make an unacceptably high proportion of those errors irrecoverable given a predetermined amount of memory devoted to redundancy. Typically recoverability is investigated following a conventional aging simulation process which simulates or approximates the data degradation effect that a predetermined time period e.g. a 10 year period has on the flash memory device, in an attempt to accommodate for a period of up to 10 years between writing of data in flash memory and reading of the data therefrom.
Resolution: Number of levels in each cell, which in turn determines the number of bits the cell can store; typically a cell with 2Λn levels stores n bits. Low resolution (partitioning the window, W, of physical values a cell can assume into a small rather than large number of levels per cell) provides high reliability.
Retention: Retention of original physical levels induced in the flash memory cells despite time which has elapsed and despite previous erase/write cycles; retention is typically below 100% resulting in deterioration of original physical levels into present levels.
Retention time: The amount of time that data has been stored in a flash device, typically without, or substantially without, voltage having been supplied to the flash device i.e. the time which elapses between programming of a page and reading of the same page.
Symbol: Logical value
Threshold level or "decision level": the voltage (e.g.) against which the charge level of a cell is measured. For example, a cell may be said to store a particular digital n-tuple D if the charge level or other physical level of the cell falls between two threshold values T.
Code rate: ratio of redundancy bits to data bits in flash memory.
Data cells: cells storing data provided by host as opposed to "non-data cells" which do not store host-provided data, and may, for example, store instead error correction information, management information, redundancy information, spare bits or parity bits.
Logical page: a set of bits defined as a page typically having a unique page address, by a host external to a flash memory device.
In the present specification, the terms "row" and "column" refer to rows of cells and columns of cells, respectively and are not references to sub-divisions of a logical page.
The term "MSB" is used herein to denote the bit which is programmed into a multi-level cell, storing several bits, first. The term "LSB" is used herein to denote the bit which is programmed into the multi-level cell, last. The term "CSB" is used herein to denote the bit which is programmed into a 3-level cell, storing 3 bits, second, i.e. after the MSB and before the LSB. It is appreciated that more generally, e.g. if the multi-level cell stores 4 or more levels, there are more than one CSBs and use of the term "CSB" herein,
which implies that the cell is a 3-level cell, is merely by way of example and is not intended to be limiting.
A logical page is a set of bytes which is meaningful to an application. The location of a logical page in memory is termed herein a physical page. This location may comprise certain cells in their entirety, or, more commonly, may comprise only one or some bits within certain cells. The locations of each of a sequence of logical pages (page 0, page 1, page 2,....) within memory is pre-determined by a suitable mapping scheme mapping logical pages into the bits of the cells of a particular erase sector (block) in flash memory. "Successfully reconstructed " means that using error correction code, the original logical page has been reconstructed generally satisfactorily, e.g., typically, that the logical page has been read, using reading thresholds, has undergone error correction as appropriate and has successfully passed its CRC (cyclic redundancy check) criterion.
"Bit errors" are those errors found in the physical page corresponding to a logical page, which typically are corrected using ECC (error correction code) such that the page is successfully reconstructed despite these errors.
The term "reading threshold" and "detection threshold" are used generally interchangeably.
The term "directed threshold errors" refers to events in which a cell which was programmed to one program level is erroneously interpreted, upon performing a read operation, as being programmed to another program level. A directed threshold error is described by stating the index of the threshold lying between the cell's program level and the erroneously read program level and which is closest to the cell's actual program level, as well as the direction of the error, i.e. "right to left" if the cell was misinterpreted as being programmed to a program level residing to the left of the cell's program level, and "left to right" if the cell was misinterpreted as being programmed to a program level residing to the right of the cell's program level.
Certain embodiments of the present invention seek to provide improved flash memory device. Certain embodiments of the present invention seek to provide inference methods in Flash Memory Devices based on analysis of bit error patterns.
Certain embodiments of the present invention seek to provide a method for correcting at least one detection threshold for reading the data of at least one page within an erase sector of a flash memory device, the method comprising associating the bit errors of at least one previous successfully read page to corresponding directed threshold errors and choosing a corrected threshold based on the previous detection threshold and number of the directed threshold errors.
Certain embodiments of the present invention seek to provide a method for associating at least one bit error of at least one successfully decoded page within an erase sector of a flash device to a corresponding directed threshold error. Certain embodiments of the present invention seek to provide a method for performing tracking of at least one detection threshold for reading the data of at least one page within an erase sector of a flash memory device wherein previously decoded pages are used.
Certain embodiments of the present invention seek to provide a method for identifying read disturb in at least one erase sector of a flash memory device wherein at least one previously decoded page is used.
There is thus provided, in accordance with certain embodiments of the present invention, a method for generating a set of at least one row-specific reading threshold for reading at least portions of pages of data within an erase sector of a flash memory device, the method comprising predetermining at least one initial reading threshold, performing the following steps for at least one current logical page: generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and computing at least one row-specific reading threshold based on the bit error characterizing information and on a previous threshold initially comprising the initial threshold and subsequently comprising a row-specific reading threshold computed for a successfully reconstructed previous logical page; and reading at least a portion of the current logical page using the at least one row-specific reading threshold. It is appreciated that the above row-specific method is performed locally, i.e. for local regions within a flash memory device being read, e.g. for each row in the flash
memory, or for some individual rows, or for each of a number of sets each comprising a relatively small number of typically adjacent rows.
According to certain embodiments of the present invention the number of threshold errors from left to right with respect to the detection threshold is compared to the number of threshold errors from right to left with respect to the detection threshold, wherein the corrected detection threshold is modified according to the sign and magnitude of the difference between the two numbers of threshold errors.
According to certain embodiments of the present invention, the number of directional threshold errors with respect to at least one detection threshold in the page is used to determine if the erase sector suffers from read disturb.
According to certain embodiments of the present invention the detection thresholds are corrected only for a subset of pages in the erase sector wherein the subset of pages is chosen such that the correction will be done on detection thresholds which were used on a subset of rows within an erase sector. According to certain embodiments of the present invention thresholds are corrected only if the difference between the total error count associated with the decoding of the page and the total error count associated with the decoding of the previous page is larger than some number.
According to certain embodiments of the present invention the association between bit errors and threshold errors in CSB and/or LSB pages is done based on reading the corresponding MSB and/or CSB pages from the flash device.
According to certain embodiments of the present invention the association is done based on the corresponding MSB and/or CSB pages which are stored in a buffer.
Further in accordance with certain embodiments of the present invention, the bit error characterizing information comprises identification of a reading threshold associated with the bit error.
Still further in accordance with certain embodiments of the present invention, the bit error characterizing information comprises a direction of the bit error.
It is appreciated that a reading threshold is associated with each bit error in that a wrong logical value is assigned to a bit when a physical value induced in the cell in which the bit resides, falls so far along one of the two tail ends of the voltage (e.g.) distribution
of the logical value as to exceed the upper threshold of the programmed value or so as to fall below the lower threshold of the programmed value. In the first instance, the upper threshold is associated with the bit error and the direction of the bit error is termed "left to right". In the second instance, the lower threshold is associated with the bit error and the direction of the bit error is termed "right to left".
Still further in accordance with certain embodiments of the present invention, a first number of threshold errors whose direction, with respect to the reading threshold, is from left to right is compared to a second number of threshold errors whose direction, with respect to the reading threshold, is from right to left, wherein the row-specific reading threshold depends upon at least one of the sign and magnitude of the difference between the first and second numbers of threshold errors.
Further in accordance with certain embodiments of the present invention, the method also comprises selecting a subset of rows within the erase sector; identifying a set of logical pages residing within the subset of rows; and performing the generating, computing and reading for the set of logical pages and for less than all pages in the erase sector.
Still further in accordance with certain embodiments of the present invention, the generating, computing and reading are performed only for the set of logical pages.
Additionally in accordance with certain embodiments of the present invention, the reading thresholds are corrected only if the number of bit errors per page is in a process of change of at least a predetermined magnitude.
Further in accordance with certain embodiments of the present invention, the reading thresholds are corrected only if the difference between the number of bit errors encountered during reconstruction of the current page and the number of bit errors occurring during reconstruction of at least one previous page is larger than a predetermined number.
The predetermined number is typically selected to be relatively large so that the reading threshold correction process is only initiated when a very significant rise in bit error frequency is detected. For example, if the page size is, say, 4K bytes, an increase in the number of bit errors per page of the order of magnitude of dozens or hundreds of bit
errors might trigger a reading threshold correction process such as those shown and described herein.
Further in accordance with certain embodiments of the present invention, the generating is performed for at least one CSB page residing in a row corresponding to an MSB page also residing in the row, based at least partly on values read from the MSB page.
Additionally in accordance with certain embodiments of the present invention, the generating is performed for an LSB page residing in a row corresponding to an MSB and at least one CSB page also residing in the row, based at least partly on values read from at least one of the MSB and CSB pages.
Further in accordance with certain embodiments of the present invention, the generating performed for the CSB page is based at least partly on values read on-the-fly from the MSB page.
Still further in accordance with certain embodiments of the present invention, the generating performed for the LSB page is based at least partly on values read on-the-fly from at least one of the MSB and CSB pages.
Additionally in accordance with certain embodiments of the present invention, the generating performed for the CSB page is based at least partly on stored values previously read from the MSB page. Further in accordance with certain embodiments of the present invention, the generating performed for the LSB page is based at least partly on stored values previously read from at least one of the MSB and CSB pages.
It is appreciated that the values read from the MSB and/or CSB pages may be read from a buffer which stored these pages, perhaps when they were originally read, or may be a re-read of a page which has already been read at least once either only for reading its own data, or also in order to perform the teachings of this invention, say, for a CSB page preceding the current page which is an LSB page. The buffer is typically located within a controller external to a flash memory device although alternatively it may be located within an internal controller. Also provided, in accordance with another embodiment of the present invention, is a method for using flash memory to store data, the method comprising writing at least
one page of data to the flash memory, reading the at least one page of data from the flash memory using a set of reading thresholds, including generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and subsequently, using the flash memory so as to take into account the bit error characterizing information.
Further in accordance with certain embodiments of the present invention, the bit error characterizing information comprises identification of a reading threshold which is associated with the bit error. Still further in accordance with certain embodiments of the present invention, the bit error characterizing information comprises a direction of the bit error.
Additionally in accordance with certain embodiments of the present invention, the using comprises reading at least one subsequent page of data so as to take into account the bit error characterizing information. Further in accordance with certain embodiments of the present invention, the using comprises detecting portions of the flash memory which suffer from read-disturb phenomenon based on the bit error characterizing information.
It is appreciated that typically, portions of the flash memory which suffer from read-disturb phenomenon are detected rather than merely deducing that a particular portion of memory, e.g. erase sector, suffers from the phenomenon based on the number of times that portion, or a sub-portion e.g. page within it, has been read.
Further in accordance with certain embodiments of the present invention, the detecting comprises detecting an overly large number of bit errors whose source is a reading threshold which is closest, within the set of reading thresholds, to zero voltage, and whose direction is from left to right.
Also provided, in accordance with another embodiment of the present invention, is a system for generating a set of at least one row-specific reading threshold for reading at least portions of pages of data within an erase sector of a flash memory device, the system comprising apparatus for predetermining at least one initial reading threshold; a bit error analyzer operative, for at least one current logical page, to generate bit error characterizing information regarding at least one corresponding bit error within at least
one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and a bit error-based threshold generator operative to compute at least one row-specific reading threshold based on the bit error characterizing information and on a previous threshold initially comprising the initial threshold and subsequently comprising a row-specific reading threshold computed for a successfully reconstructed previous logical page; and a flash memory cell reader operative to read at least a portion of the current logical page using the at least one row-specific reading threshold.
Further provided, in accordance with yet another embodiment of the present invention, is a system for using flash memory to store data, the system comprising apparatus for writing in flash memory operative to write at least one page of data to the flash memory; a bit error characterizing reader operative to read the at least one page of data from the flash memory using a set of reading thresholds, including generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and a bit error-based controller operative to control the flash memory so as to take into account the bit error characterizing information.
Any suitable processor, display and input means may be used to process, display, store and accept information, including computer programs, in accordance with some or all of the teachings of the present invention, such as but not limited to a conventional personal computer processor, workstation or other programmable device or computer or electronic computing device, either general-purpose or specifically constructed, for processing; a display screen and/or printer and/or speaker for displaying; machine- readable memory such as optical disks, CDROMs, magnetic-optical discs or other discs; RAMs, ROMs, EPROMs, EEPROMs, magnetic or optical or other cards, for storing, and keyboard or mouse for accepting. The term "process" as used above is intended to include any type of computation or manipulation or transformation of data represented as physical, e.g. electronic, phenomena which may occur or reside e.g. within registers and /or memories of a computer.
The above devices may communicate via any conventional wired or wireless digital communication means, e.g. via a wired or cellular telephone network or a computer network such as the Internet.
The apparatus of the present invention may include, according to certain embodiments of the invention, machine readable memory containing or otherwise storing a program of instructions which, when executed by the machine, implements some or all of the apparatus, methods, features and functionalities of the invention shown and described herein. Alternatively or in addition, the apparatus of the present invention may include, according to certain embodiments of the invention, a program as above which may be written in any conventional programming language, and optionally a machine for executing the program such as but not limited to a general purpose computer which may optionally be configured or activated in accordance with the teachings of the present invention.
The embodiments referred to above, and other embodiments, are described in detail in the next section.
Any trademark occurring in the text or drawings is the property of its owner and occurs herein merely to explain or illustrate one example of how an embodiment of the invention may be implemented.
Unless specifically stated otherwise, as apparent from the following discussions, it is appreciated that throughout the specification discussions, utilizing terms such as, "processing", "computing", "estimating", "selecting", "ranking", "grading", "calculating", "determining", "generating", "reassessing", "classifying", "generating", "producing", "stereo-matching", "registering", "detecting", "associating", "superimposing", "obtaining" or the like, refer to the action and/or processes of a computer or computing system, or processor or similar electronic computing device, that manipulate and/or transform data represented as physical, such as electronic, quantities within the computing system's registers and/or memories, into other data similarly represented as physical quantities within the computing system's memories, registers or other such information storage, transmission or display devices.
BRIEF DESCRIPTION OF THE DRAWINGS
Certain embodiments of the present invention are illustrated in the following drawings: Fig. 1 is a simplified block diagram of a flash memory system constructed and operative in accordance with certain embodiments of the present invention;
Fig. 2 is a simplified functional block diagram illustration of the bit-error analyzing controller 102 of Fig. 1, according to certain embodiments of the present invention; Fig. 3 is a theoretical graph of voltage distributions conditional on program levels which is useful in understanding certain embodiments of the present invention;
Fig. 4A - 4C, taken together, are a diagram depicting mapping from data bits to program levels and threshold crossover errors which is useful in understanding certain embodiments of the present invention; Figs. 5A - 5B, taken together, form a simplified flowchart illustration of a method for correcting reading thresholds by tracking bit error patterns, which method may for example be performed by the system of Figs. 1 - 2, the method being operative according to certain embodiments of the present invention;
Fig. 6 is a simplified flowchart illustration of a method for performing the "bit error to threshold error" step in Figs. 5A - 5B for an MSB page, the method identifying, for each bit error, a reading threshold associated therewith and a direction thereof;
Fig. 7 is a simplified flowchart illustration of a method for performing the "bit error to threshold error" step in Figs. 5A - 5B for a CSB page, assuming, which of course need not be the case, that the cells in each page are 3-level cells (i.e. assuming for simplicity that there is only one CSB page), the method identifying, for each bit error, a reading threshold associated therewith and a direction thereof;
Figs. 8A - 8B, taken together, form a simplified flowchart illustration of a method for performing the "bit error to threshold error" step in Figs. 5A - 5B for an LSB page, the method identifying, for each bit error, a reading threshold associated therewith and a direction thereof;
Fig. 9 is a simplified flowchart illustration of a method for performing the threshold updating step in Figs. 5A - 5B for either an MSB, CSB, or an LSB page;
Fig. 10 is a simplified flowchart illustration of a method for read disturb identification by tracking bit error patterns, the method being operative according to certain embodiments of the present invention;
Fig. 1 1 is a simplified flowchart illustration of a modification of the method of Figs. 5A - 5B in which tracking activation is diluted;
Fig. 12 is a simplified flowchart illustration of a method for accessing the page-to- row lookup table corresponding to the mapping type; Fig. 13 is a table comprising a mapping between logical pages and physical pages which is useful in understanding certain embodiments of the present invention;
Fig. 14 is a table comprising another mapping between logical pages and physical pages which is useful in understanding certain embodiments of the present invention;
Fig. 15 is a look-up-table based on the mapping in Fig. 13 which associates for each page index the corresponding row index where the logical page resides, and which is useful in understanding certain embodiments of the present invention;
Fig. 16 is a look-up-table based on the mapping in Fig. 14 which associates for each page index the corresponding row index where the logical page resides, and which is useful in understanding certain embodiments of the present invention; Fig. 17 is a simplified flowchart illustration of a modification of the method of
Figs. 5A - 5B in which tracking activation is conditional, the method being operative according to certain embodiments of the present invention;
Fig. 18 is a generalized flowchart illustration of a method of operation of the system of Figs. 1 - 2, the method being operative according to certain embodiments of the present invention; and
Fig. 19 is a simplified flowchart illustration of a method for using flash memory to store data, the method being operative in accordance with certain embodiments of the present invention.
DETAILED DESCRIPTION OF CERTAIN EMBODIMENTS
In the present specification, the terms "row" and "column" as used herein are intended to include rows of cells and columns of cells, respectively and are not references to sub-divisions of a logical page.
The term "MSB" as used herein is intended to include the bit which is programmed into a multi-level cell, storing several bits, first. The term "LSB" as used herein is intended to include the bit which is programmed into the multi-level cell, last. The term "CSB" as used herein is intended to include the bit which is programmed into a 3-level cell, storing 3 bits, second, i.e. after the MSB and before the LSB. It is appreciated that more generally, e.g. if the multi-level cell stores 4 or more levels, there are more than one CSBs and use of the term "CSB" herein, which implies that the cell is a 3-level cell, is merely by way of example and is not intended to be limiting.
A logical page as used herein is intended to include a set of bytes which is meaningful to an application. The location of a logical page in memory is termed herein a physical page. This location may comprise certain cells in their entirety, or, more commonly, may comprise only one or some bits within certain cells. The locations of each of a logical sequence of logical pages (page 0, page 1, page 2,....) within memory is pre-determined by a suitable mapping scheme mapping logical pages into the bits of the cells of a particular erase sector (block) in flash memory.
"Successfully reconstructed " as used herein is intended to include situations in which, using error correction code, the original logical page has been reconstructed generally satisfactorily, e.g., typically, that the logical page has been read, using reading thresholds, has undergone error correction as appropriate and has successfully passed its CRC (cyclic redundancy check) criterion.
"Bit errors" as used herein is intended to include those errors found in the physical page corresponding to a logical page, which typically are corrected using ECC (error correction code) such that the page is successfully reconstructed despite these errors.
The terms "reading threshold" and "detection threshold" are used generally interchangeably.
Reference is now made to Fig. 1 which is a simplified block diagram of a flash memory system constructed and operative in accordance with certain embodiments of the present invention. As shown, the flash memory system of Fig. 1 includes a host or outside application 100 which interfaces, via an interface controller 102, with a flash memory device 105. An internal microcontroller 1 10 typically manages the functional units of the flash memory device 105. The storage portion of the flash memory device includes one or more typically many erase sectors 120 each storing one or more typically many physical pages 130 each including one or more typically many cells 140 having more than one possible state such that logical values may be stored therein. Erasing circuitry 150 is provided to erase data from cells, writing circuitry 160 writes data into cells, and reading circuitry 170 reads data from cells.
A particular feature of the system shown in Fig. 1 by way of example is the bit- error analyzing functionalities of the I/F controller 102 and/or of the internal microcontroller 1 10. Fig. 2 is a simplified functional block diagram illustration of the bit-error analyzing controller 102 of Fig. 1, according to certain embodiments of the present invention. As shown, the controller 102 may include a bit error characterization block 200 which provides information regarding bit errors' characteristics, particularly joint characteristics, to application functionalities such as but not limited to a read threshold computation unit 210 and/or a read-disturb event finder 220. Optionally, a buffer 230 is provided which is useful for reading MSB and CSB pages as described in detail herein. The buffer 230 serves the characterizer of bit errors 200 which in turn serves read threshold computation unit 210 and/or read-disturb event finder 220.
The system of Figs. 1 - 2 is particularly suitable for generating a set of at least one row-specific reading threshold for reading at least portions of pages of data within an erase sector of a flash memory device. This method may comprise some or all of the following steps, as shown in Fig. 18:
Step 3010: predetermining at least one initial reading threshold
Step 3020: performing steps 3030 and 3040 for each of at least one current logical pages.
Step 3030: generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page.
Step 3040: computing at least one row-specific reading threshold based on the bit error characterizing information and on a previous threshold initially comprising the initial threshold and subsequently comprising a row-specific reading threshold computed for a successfully reconstructed previous logical page.
Step 3050: When steps 3030 and 3040 have been performed for a set of current logical pages, step 3050 is performed, involving reading at least a portion of the current logical page using the at least one row-specific reading threshold.
Conventionally, flash memory devices store information as charge in "cells", each made of either a floating gate transistor or an NROM transistor. In single-level cell (SLC) devices, each cell stores only one bit of information. Multi-level cell (MLC) devices can store more than one bit per cell by choosing between multiple levels of electrical charge to apply to the floating gates of their cells. The amount of charge (also known as charge level) is then measured by a detector, by comparing the voltage of the transistor gate (also known as charge level and denoted VT) to a decision threshold voltage (also known as charge level boundary point and denoted VD). The amount of charge is then used to determine the programmed level (logical value) of the cell. Due to inaccuracies during the programming procedure and charge loss due to time and temperature (also known as retention), the measured levels suffer from a random distortion. Prior art Fig. 3 illustrates an example of the eight separate probability distributions of a cell which can be programmed with one of eight corresponding program levels (1 1 1, 1 10, 100, 101, 001, 000, 010, and 011, respectively). For each distribution curve, the Y-axis represents the probability that the cell is programmed to the corresponding level, given the value of the charge level Vτ (represented by the x- axis).
A particular feature of certain embodiments of the present invention, is that changes in the distributions of the programming lobes illustrated in Fig. 3 are tracked between pages, using a suitable indicator of such changes such as bit error characteristics including associated threshold and direction of each bit error, all as described in detail below.
The cell's programmed level may be determined using several methods. One method is to apply a voltage to the cell's gate and measure if the cell conducts current. The cell has a certain threshold voltage such that if voltage above that threshold is applied to the gate, the gate will conduct. Below that threshold voltage the gate will not conduct current (or will conduct a small amount of current, below a certain demarcation level). As the amount of charge in the cell changes this threshold voltage, the charge may be inferred by deteπnining at which voltage the cell starts to conduct current. Thus, the programmed level is determined by iteratively applying different voltages to the gate and measuring whether the cells conduct or not. Another method is based on the fact that when applying a voltage above the threshold voltage, the cell conducts current and the amount of current depends on the difference between the applied voltage and the threshold voltage. As the threshold voltage changes as a function of the amount of charge in the cell, the programmed level may be inferred by measuring the current going through the cell.
Thus, the programmed level may be obtained by simultaneously comparing the conducted current with a given set of fixed currents distinguishing between all programmed levels. In other words, each cell's programmed level is determined by simultaneously comparing the VT level against several decision threshold levels (detection thresholds). For example, if there are eight possible programmed levels, the cell's VT is simultaneously compared against seven decision threshold levels which divide the voltage axis into eight regions, as demonstrated in Fig. 3.
In general, if there are L possible program levels, then L-I decision threshold levels are employed. As the probability distributions extend beyond the decision threshold levels, there is a probability of detection error, i.e. detecting the wrong program level. In order to minimize the detection error, one wishes to set the decision threshold levels optimally. The optimal placement of the decision thresholds levels in terms of minimizing the detection error probability generally depends on the probability distribution associated with the Vτ level of the cells. The statistical behavior of the cells' VT level can be approximated by Gaussian distributions. The optimal placement of the detection threshold for the Gaussian case is a known function of the means and standard deviations (STDs) of the Gaussian distributions. In other words, knowledge of good
decision thresholds (assuming the Gaussian assumption is correct) is possible if the means and STDs of the cells' Vx distributions are known.
Since the means and STDs of the the probability distributions change as a result of cycling and retention, it is not clear how to set the decision thresholds when attempting to read a given page storing information. Setting the decision thresholds to the optimal position corresponding to a fresh device might show acceptable performance only if the page was recently programmed and not retained for a significant amount of time. Similarly, setting the decision thresholds to fit a device which was cycled 1000 times and retained for 10 years might not work, i.e. cause too many detection errors, if the page in question was recently written to a non-cycled flash device.
In some applications, this situation calls for a training stage in which the flash device's controller learns the "state" of the page/block and determines a set of decision thresholds which will yield preferably as little detection errors as possible when used to read the page. Since some variations exist in the statistics of the program levels between different blocks within one flash device, and between different pages within one erase sector, it is appreciated that one cannot hope to find a single choice of thresholds which will be appropriate, i.e. yield a sufficiently high uncoded bit error rate (UBER), for all the pages in the flash device. One solution is to use the training process for every page to be read, or for every page for which it is suspected that the detection thresholds previously obtained are not sufficiently accurate. Depending on the complexity of the training process, such a solution might be too costly, and might jeopardize the feasibility of certain flash applications.
Certain embodiments of this invention include a way for adapting the detection thresholds from one page to the next in such a way which considerably limits the number of training operations employed to read an entire population of blocks of a flash device. The adaptation is done either without or with very little additional reading operations from the flash device. In certain embodiments, the adaptation is done based on the bit error pattern obtained after successful decoding of the error correcting code (ECC). The embodiment described above also has applications for coping with read disturb.
Read disturb is a situation where the voltages applied to the row and column of a target
memory floating gate cell in order to perform the read operation, cause unwanted programming to erased cells which lie on the same column as the target cell. This unwanted programming accumulates over time after successive read operations to the degree of causing cells in the erased state to be in programmed states. Certain embodiments of this invention use the bit error patterns to identify a block which is suffering from a severe read disturb and if left unchanged might reach a state where the data stored in it becomes undetectable.
Also described herein are variations on the above embodiments which account for performance trade-offs. According to certain embodiments of the present invention, tracking of the changes in the detection thresholds which occur between successive pages in a flash array is provided. The tracking is performed by analyzing the asymmetry between errors which occur due to cells' V1 levels crossing the detection thresholds from left to right and errors which occur due to cells' VT levels crossing the detection thresholds from right to left. The detection thresholds are modified according to the sign and magnitude of the difference between the two types of threshold errors. The tracking operation guarantees that detection thresholds adapt to the changes in the threshold voltage distributions without the need to perform multiple training procedures which may be costly in terms of flash read operations. Certain embodiments of this invention seek to perform the above functionalities in a manner which saves processing time e.g. by performing the tracking procedure only for certain rows/pages within an erase sector, and/or by performing the tracking procedure only when the total number of errors increases drastically with respect to previous rows/pages. Certain embodiments of this invention seek to perform the above functionalities in a manner which saves memory requirements e.g. by performing read operations from the flash "on the fly" in order to associate bit errors to the threshold errors.
Certain embodiments of this invention seek to identify erase sectors which suffer from read disturb. This is done by identifying erased cells which have become programmed due to repetitive read operations. A threshold error association mechanism is used here to identify programming of erased cells by checking the number of directed
threshold errors from left to right with respect to the detection threshold closest to the erased level.
By way of example, consider a floating gate flash memory device where each cell has 8 possible charge levels (or program levels), thus storing 3 bits per cell. That said, certain embodiments of this invention are also applicable to NROM flash devices and/or flash devices with less or more charge levels. The page to be read has been written to a flash device after an unknown number of program/erase cycles, and the data in the page was retained for an unknown period of time. Denote the number of cells in the page by ^rc . Denote the means of the cells' VT level distributions by ^i 'Pz > - ^s , where the index 1 corresponds to the erase level, index 2 corresponds to the program level closest to the erased state, and so on. Furthermore, denote by σi - σz > ■•• > σs the standard deviations (STDs) of these distributions, respectively. Finally, denote by T1 . T2 , ... , T7 the detection thresholds which are to be used for reading the page. An approximation to the optimal detection thresholds is given by the following formula:
1 % = ; , K = 1,1, ...,/ .
Tracking of Detection Thresholds according to certain embodiments of the present invention is now described in detail.
In many occasions, the pages of one block are read sequentially. When examining the threshold voltage distributions of the pages in one block, it is observed that some variations occur from page to page. In some situations, the total variations across the rows of a single block can be comparatively large. This implies that employing the same detection thresholds for reading all the pages of the block will result in too many errors, which the error correcting code will not be able to correct.
One solution is to perform a training procedure for every row in the block. This approach might be less favorable due to the potential delay inherent to the training process. A low cost alternative is described herein which need not employ any extra reading operations from the flash other than those which actually read the page.
In the example shown and described herein, the mapping between data bits and cell program levels is depicted in prior art Fig. 4. Each combination of bits corresponding to a specific selection of MSB, CSB, and LSB is mapped to one of eight program levels as
shown in Fig. 4. The dashed vertical lines mark the reading thresholds. In order to read the MSB, a single threshold is used. Cells which conduct current when this threshold is applied to their gate are interpreted as having their MSB equal to 1, while the remaining cells are identified as having their MSB equal 0. The reading of the CSB employs two thresholds. Cells which conduct when the left threshold is applied to them and cells which do not conduct (even) if the right threshold is applied to them are identified as having their CSB equal 1, while the cells which do not conduct when the left threshold is applied to them but conduct current when the right threshold is applied to them are interpreted as having their CSB equal 0. For the LSB, four thresholds are employed. Cells whose VT lies between Ti and T2 or between T3 and T4 are interpreted as having their LSB equal 0, while for the remaining cells, the LSB is read as 1.
The curved arrows above each detection threshold designate errors resulting from threshold voltages of some cells appearing in the detection regions of their neighboring cells. For example, assume a cell was programmed to level 3, but due to programming error and/or retention effects, the actual threshold voltage at the time the cell is to be read is just to the left of Ti in the second graph of Fig. 4. When Ti is applied to this cell, it will conduct current and its CSB bit will be erroneously interpreted as a 1 even though its CSB was 0. Such an error event is marked by the bold solid curved arrow above Ti in the second graph of Fig. 4. Similarly, the remaining dashed curved arrows designate threshold errors from left to right, while the solid arrows mark errors from right to left. These threshold errors are termed herein "directed threshold errors".
The tracking process is based on the assumption that when the thresholds are not optimally placed, e.g. due to the shifting of the means of the program levels between successive rows, an asymmetry is present between the errors from left to right and the errors from right to left.
The tracking process may proceed as depicted in Figs. 5A - 5B. It is appreciated that Tl - T4 in Figs. 5A - 5B are defined by Fig. 4. Once a page within a block of a flash device is successfully decoded, the corrected page bits are passed to the tracking block along with the location of the erroneous bits, the page bit type (MSB, CSB, or LSB), and the set of thresholds which was used to read the page. If the page is an MSB page, only
one threshold is supplied. If the page is a CSB page, 2 thresholds are given, and finally, tracking of an LSB page uses knowledge of four detection thresholds.
Next, the process maps each bit error to a directed threshold error event and updates an appropriate counter. For each threshold, two counters are used, one counting threshold errors from left to right, and another which counts errors from right to left. Once all the errors in the page are processed, the corresponding thresholds are corrected in the appropriate direction as a function of the asymmetry in the number of threshold errors. In one embodiment, the difference between the threshold errors from left to right and from right to left is computed for every threshold, and according to the difference's sign and magnitude an appropriate quantity is either added to or subtracted from the original threshold. The procedure described in Figs. 5A - 5B is repeated for every page which is successfully decoded.
The way in which the bit errors are mapped to threshold error events depends on the type of page which is being tracked. For example, assuming here and throughout the present specification, that standard gray level coding is used, the mapping may be as shown in Figs. 6 - 8. Specifically, Fig. 6 is a simplified flowchart illustration of a method for performing the "bit error to threshold error" step in Figs. 5A - 5B for an MSB page, the method identifying, for each bit error, a reading threshold associated therewith and a direction thereof. Fig. 7 is a simplified flowchart illustration of a method for performing the "bit error to threshold error" step in Figs. 5A - 5B for a CSB page, assuming that the cells in each page are 3-level cells (i.e. assuming for simplicity that there is only one CSB page), the method identifying, for each bit error, a reading threshold associated therewith and a direction thereof. Figs. 8A - 8B, taken together, form a simplified flowchart illustration of a method for performing the "bit error to threshold error" step in Figs. 5A - 5B for an LSB page, the method identifying, for each bit error, a reading threshold associated therewith and a direction thereof.
It is appreciated that in the case of an MSB page, as shown in Fig. 6, each bit error of the form 0-> 1 corresponds to a threshold error from right to left, and each bit error of the form l->0 is a result of a threshold error from left to right. As shown in Fig. 7, in the
case of a CSB page in a certain physical row, the mapping depends on the corresponding bit in the MSB page residing in the same physical row. For instance, a bit error event of the form 0->l can be interpreted as a right-to-left threshold error event of threshold Ti, if the MSB bit equals 1 , or as a left-to-right threshold error event of threshold T2, if the MSB bit equals 0. Similarly, as shown in Figs. 8A - 8B, the mapping of bit errors to threshold error events for an LSB page typically comprises using knowledge of the MSB and CSB bits in the corresponding cells residing in the same physical row. Depending on the order in which the pages are written to and read from the erase sector, and depending on the mapping between logical pages and physical pages (and rows), a buffer may be used in order to store the values of the MSB and CSB pages for future tracking of CSB and LSB pages.
For instance, if the LSB page of a certain row is always written d pages after the MSB page of the same row, a buffer of length at least d may be used to guarantee that upon decoding of the LSB page, the MSB page of the same row is available. Identification of Read Disturbs according to certain embodiments of the present invention is now described in detail.
In flash memories, the read procedure involves the application of certain voltages to the word line corresponding to the row address of the read cell as well as the bit line corresponding to the column address of the cell. These voltages are of the same kind as those which are applied during programming, only lower in magnitude. The voltage applied to the bit line may induce a small charge transfer to the floating gate. While the charge transfer which occurs in any individual read operation is limited due to the relatively low voltage applied to the bit line, the cumulative effect of many (-100,000) read operations might cause a significant charge increase in the floating gate. This phenomenon may cause cells which are in the erased state and which share the same bit line as the cell being read to become programmed. Furthermore, since all the cells along a bit line are affected by this disturb, the excessive reading of even a single page might have a deleterious effect on the entire block.
While it is possible to identify such a situation by maintaining counters for each block in the flash device and checking if for a particular block the number of read
operations exceeded a certain threshold, such an approach involving a multitude of counters might be prohibitively complex in some applications.
According to certain embodiments of the present invention, a determination is made as to whether a given block is reaching the state where the excessive read operations from it are about to render the data undetectable, by using the ingredients of the tracking process which was described above. Specifically, a determination may be made as to whether the cells within a particular page which are in the erased state have begun shifting to a programmed state. This can be done by associating the bit errors to their corresponding threshold errors and checking if the number of threshold errors from left to right with respect to the detection threshold closest to the erase state has increased beyond some prescribed threshold. Once the above threshold is crossed, proper measures can be taken in order to prevent the data stored in the block from being distorted beyond repair. For instance, the content of the block can be copied to another block, and the block which was identified as suffering from read disturb can be erased. An example of this procedure is shown in Fig. 10.
Any suitable action may be initiated if a read-disturb phenomenon has been detected. To give one possible example among many suitable remedial actions, the content of the block can be copied to another available block, and the block suffering from read disturb can be erased and used subsequently as an available block. Performance trade-off considerations according to certain embodiments of the present invention are now described in detail.
In order to implement the tracking of detection thresholds as described hereinabove and the identification of blocks which suffer from read disturb also described hereinabove some previously read pages may be kept in appropriate buffers. The length of the buffer may depend on the particular order in which logical pages are mapped to physical pages within an erase sector. In some applications, the buffer might impose limitations on the scope of these applications.
Several methods by which memory consumption stemming from the buffer may be reduced, are described below. It is appreciated that the presentation of these in the context of the tracking application described above is merely by way of example and the applicability of these methods is not limited to the tracking application described above.
Dilution of Tracking Activation according to certain embodiments of the present invention is now described in detail. In some applications, the voltage variation across the rows of a block are such which employ only a few threshold corrections within the block. In the tracking method described above, the procedure for tracking the detection thresholds is activated for every page in the block. This implies that most of the times, the tracking is activated in vain.
In certain embodiments of the present invention, the tracking is employed only on pages which lie in rows which are multiples of a certain integer values (e.g. 2, 3 ). The advantages of this approach are twofold. First, the processing of the bit errors is circumvented in some of the rows in the block, leading to saving in processing times. Second, the MSB and CSB pages which belong to the untracked rows need not be saved in the buffer, leading to savings in the system's memory requirements. An example of this procedure is shown in Fig. 1 1.
Conditional activation of tracking according to certain embodiments of the present invention is now described in detail.
In some applications, the mapping between logical pages and physical pages is such that in order to implement the tracking procedure a large number of pages is employed such as several dozen pages. It is therefore sometimes advantageous to trade-off memory resources with time resources. In certain embodiments of this invention, the buffer is relinquished and replaced by occasional read operations from the flash. Based on the reasoning described above, it is expected that tracking will hardly be employed within the block. Tracking is typically employed when the distributions of the program levels have changed significantly with respect to the ones which were obtained last. Such a situation can be identified by checking if the total number of errors has significantly increased with respect to the previous row or page. Only if the number of errors has risen drastically, is the tracking procedure employed, and in case of tracking a CSB or a LSB page, appropriate read operations will be performed to enable association of bit errors to threshold errors. It is assumed that the scarcity of the tracking procedures employed within one block is sufficient to render the performance loss or increased time delay, due to the additional read operation, negligible.
Example implementations: Two specific implementations of the invention shown and described herein are now described, by way of example, which pertain respectively to different mappings of a sequence of logical pages numbered for convenience 0, 1, 2,... each including a multiplicity of data bytes such as 4K data bytes, into an erase block including an array of physical cells arranged in physical rows numbered for convenience 0, 1, 2,... and physical columns. Implementation 1 pertains to a mapping scheme termed Mapping 1 and described below, and Implementation 2 pertains to a mapping scheme termed Mapping 2 and described below. It is appreciated that alternatively, any other suitable mappings may be used. Mapping 1 comprises the following mapping scheme: A sequence of logical pages is mapped into an erase block including an array of physical multi-level e.g. 3-level cells as follows:
Logical page 0 is stored in the MSBs of cells 0, 2, 4 etc. in row 0.
Logical page 1 is stored in the MSBs of cells 1, 3, 5 etc. in row 0. Logical page 2 is stored in the MSBs of cells 0, 2, 4, etc. in row 1.
Logical page 3 is stored in the MSBs of cells 1, 3, 5, etc. in row 1.
Logical page 4 is stored in the MSBs of cells 0, 2, 4, etc. in row 2.
Logical page 5 is stored in the MSBs of cells 1, 3, 5, etc. in row 2.
Logical page 6 is stored in the MSBs of cells 0, 2, 4, etc. in row 3. Logical page 7 is stored in the MSBs of cells 1, 3, 5, etc. in row 3.
Logical page 8 is stored in the MSBs of cells 0, 2, 4, etc. in row 4.
Logical page 9 is stored in the MSBs of cells 1, 3, 5, etc. in row 4.
Logical page 10 is stored in the CSBs of cells 0, 2, 4, etc. in row 0.
Logical page 11 is stored in the CSBs of cells 1, 3, 5, etc. in row 0. Logical page 12 is stored in the MSBs of cells 0, 2, 4, etc. in row 5.
Logical page 13 is stored in the MSBs of cells 1, 3, 5, etc. in row 5.
Logical page 14 is stored in the CSBs of cells 0, 2, 4, etc. in row 1.
Logical page 15 is stored in the CSBs of cells 1, 3, 5, etc. in row 1.
Logical pages 0, 2, etc. are termed herein "even pages" whereas pages 1, 3, etc. are termed herein "odd pages". For the case of erase sectors comprising 192 logical pages
mapped to 32 physical rows, the mapping of pages to cells is listed in its entirety in Fig. 14.
Example implementation 1 is now described. As for tracking an MSB page, the implementation is not dependent on the mapping and is depicted in Fig. 6. As for tracking a CSB page, e.g. as shown in Fig. 7, the step 705 comprises looking in the table appearing in Fig. 16, and finding the row in which the page resides. Then, the row number is used to access the table in Fig. 14 and obtain the page number of the corresponding MSB page residing in the same row. The page itself is located in the buffer appearing in Fig. 2. As for tracking an LSB page e.g. as shown in Figs. 8A - 8B, the step 810 comprises looking in the table appearing in Fig. 16, and finding the row in which the page resides. Then, the row number is used to access the table in Fig. 14 and obtain the page numbers of the corresponding MSB and CSB pages residing in the same row. The pages themselves are located in the buffer appearing in Fig. 2. Mapping 2 comprises the following mapping scheme:
A sequence of logical pages is mapped into an erase block including an array of physical multi-level e.g. 3-level cells as follows:
Logical page 0 is stored in the MSBs of cells 0, 2, 4 etc. in row 0.
Logical page 1 is stored in the MSBs of cells 1, 3, 5 etc. in row 0. Logical page 2 is stored in the CSBs of cells 0, 2, 4, etc. in row 0.
Logical page 3 is stored in the CSBs of cells 1, 3, 5, etc. in row 0.
Logical page 4 is stored in the LSBs of cells 0, 2, 4, etc. in row 0.
Logical page 5 is stored in the LSBs of cells 1, 3, 5, etc. in row 0.
Logical page 6 is stored in the MSBs of cells 0, 2, 4, etc. in row 1. Logical page 7 is stored in the MSBs of cells 1, 3, 5, etc. in row 1.
Logical pages 0, 2, etc. are termed herein "even pages" whereas pages 1, 3, etc. are termed herein "odd pages". For the case of erase sectors comprising 192 logical pages mapped to 32 physical rows, the mapping of pages to cells is listed in its entirety in Fig. 13. Example implementation 2 is now described. As for tracking an MSB page, the implementation is not dependent on the mapping and is depicted in Fig. 6. As for tracking
a CSB page e.g. as shown in Fig. 7, step 705 comprises looking in the table appearing in
Fig. 15, and finding the row in which the page resides. Then, the row number is used to access the table in Fig. 13 and obtain the page number of the corresponding MSB page residing in the same row. The page itself is located in the buffer appearing in Fig. 2. As for tracking an LSB page e.g. as shown in Figs. 8A - 8B, step 810 comprises looking in the table appearing in Fig. 15. and finding the row in which the page resides. Then, the row number is used to access the table in Fig. 13 and obtain the page numbers of the corresponding MSB and CSB pages residing in the same row. The pages themselves are located in the buffer appearing in Fig. 2. Fig. 18 is a generalized flowchart illustration of a method of operation of the system of Figs. 1 - 2, the method being operative according to certain embodiments of the present invention.
The method of Fig. 18 typically comprises some or all of the following steps, suitably ordered e.g. as shown: Step 3010: predetermine at least one initial reading threshold.
Step 3020: perform steps 3030 and 3040 for each of at least one current logical pages.
Step 3030: generate bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page.
Step 3040: compute at least one row-specific reading threshold based on the bit error characterizing information and on a previous threshold initially comprising the initial threshold and subsequently comprising a row-specific reading threshold computed for a successfully reconstructed previous logical page. Step 3050: When steps 3030 and 3040 have been performed for a set of current logical pages, step 3050 is performed, involving reading at least a portion of the current logical page using the at least one row-specific reading threshold.
Fig. 19 is a simplified flowchart illustration of a method for using flash memory to store data, the method being operative in accordance with certain embodiments of the present invention. The method of Fig. 19 typically comprises some or all of the following steps, suitably ordered e.g. as shown:
Step 3110: Write at least one page of data to flash memory Step 3120: Read at least one page of data from flash memory using a set of reading thresholds, including generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page
Step 3130: Subsequently, use flash memory so as to take into account bit error characterizing information.
It is appreciated that software components of the present invention including programs and data may, if desired, be implemented in ROM (read only memory) form including CD-ROMs, EPROMs and EEPROMs, or may be stored in any other suitable computer-readable medium such as but not limited to disks of various kinds, cards of various kinds and RAMs. Components described herein as software may, alternatively, be implemented wholly or partly in hardware, if desired, using conventional techniques.
Included in the scope of the present invention, inter alia, are electromagnetic signals carrying computer-readable instructions for performing any or all of the steps of any of the methods shown and described herein, in any suitable order; machine-readable instructions for performing any or all of the steps of any of the methods shown and described herein, in any suitable order; program storage devices readable by machine, tangibly embodying a program of instructions executable by the machine to perform any or all of the steps of any of the methods shown and described herein, in any suitable order; a computer program product comprising a computer useable medium having computer readable program code having embodied therein, and/or including computer readable program code for performing, any or all of the steps of any of the methods shown and described herein, in any suitable order; any technical effects brought about by any or all of the steps of any of the methods shown and described herein, when performed in any suitable order; any suitable apparatus or device or combination of such, programmed to perform, alone or in combination, any or all of the steps of any of the methods shown and described herein, in any suitable order; information storage devices or physical records, such as disks or hard drives, causing a computer or other device to be configured so as to carry out any or all of the steps of any of the methods shown and described herein, in any suitable order; a program pre-stored e.g. in memory or on an
information network such as the Internet, before or after being downloaded, which embodies any or all of the steps of any of the methods shown and described herein, in any suitable order, and the method of uploading or downloading such, and a system including server/s and/or client/s for using such; and hardware which performs any or all of the steps of any of the methods shown and described herein, in any suitable order, either alone or in conjunction with software.
Certain operations are described herein as occurring in the microcontroller internal to a flash memory device. Such description is intended to include operations which may be performed by hardware which may be associated with the microcontroller such as peripheral hardware on a chip on which the microcontroller may reside. It is also appreciated that some or all of these operations, in any embodiment, may alternatively be performed by the external, host-flash memory device interface controller including operations which may be performed by hardware which may be associated with the interface controller such as peripheral hardware on a chip on which the interface controller may reside. Finally it is appreciated that the internal and external controllers may each physically reside on a single hardware device, or alternatively on several operatively associated hardware devices.
Any data described as being stored at a specific location in memory may alternatively be stored elsewhere, in conjunction with an indication of the location in memory with which the data is associated. For example, instead of storing page- or erase- sector-specific information within a specific page or erase sector, the same may be stored within the flash memory device's internal microcontroller or within a microcontroller interfacing between the flash memory device and the host, and an indication may be stored of the specific page or erase sector associated with the cells. It is appreciated that the teachings of the present invention can, for example, be implemented by suitably modifying, or interfacing externally with, flash controlling apparatus. The flash controlling apparatus controls a flash memory array and may comprise either a controller external to the flash array or a microcontroller on-board the flash array or otherwise incorporated therewithin. Examples of flash memory arrays include Samsung's K9XXG08UXM series, Hynix' HY27UK08BGFM Series, Micron's MT29F64G08TAAWP or other arrays such as but not limited to NOR or phase change
memory. Examples of controllers which are external to the flash array they control include STMicroelectrocincs's ST7265x microcontroller family, STMicroelectrocincs's ST72681 microcontroller, and SMSCs USB97C242, Traspan Technologies' TS-4811, Chipsbank CBM2090/CBM1 190. Example of commercial IP software for Flash file systems are: Denali's Spectra™ NAND Flash File System, Aarsan's NAND Flash Controller IP Core and Arasan's NAND Flash File System. It is appreciated that the flash controller apparatus need not be NAND-type and can alternatively, for example, be NOR-type or phase change memory-type.
Flash controlling apparatus, whether external or internal to the controlled flash array, typically includes the following components: a Memory Management/File system, a NAND interface (or other flash memory array interface), a Host Interface (USB, SD or other), error correction circuitry (ECC) typically comprising an Encoder and matching decoder, and a control system managing all of the above. The present invention may for example interface with or modify, as per any of the embodiments described herein, one, some or all of the above components.
Features of the present invention which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, features of the invention, including method steps, which are described for brevity in the context of a single embodiment or in a certain order may be provided separately or in any suitable subcombination or in a different order, "e.g." is used herein in the sense of a specific example which is not intended to be limiting.
Claims
1. A method for generating a set of at least one row-specific reading threshold for reading at least portions of pages of data within an erase sector of a flash memory device, the method comprising: predetermining at least one initial reading threshold; performing the following steps for at least one current logical page: generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and computing at least one row-specific reading threshold based on said bit error characterizing information and on a previous threshold initially comprising said initial threshold and subsequently comprising a row-specific reading threshold computed for a successfully reconstructed previous logical page; and reading at least a portion of said current logical page using said at least one row-specific reading threshold.
2. A method according to claim 1 wherein said bit error characterizing information comprises identification of a reading threshold associated with the bit error.
3. A method according to claim 1 wherein said bit error characterizing information comprises a direction of the bit error.
4. A method according to claim 1 wherein a first number of threshold errors whose direction, with respect to said reading threshold, is from left to right is compared to a second number of threshold errors whose direction, with respect to said reading threshold, is from right to left, wherein the row-specific reading threshold depends upon at least one of the sign and magnitude of the difference between said first and second numbers of threshold errors.
5. A method according to claim 1 and also comprising: selecting a subset of rows within said erase sector; and identifying a set of logical pages residing within said subset of rows; and performing said generating, computing and reading for said set of logical pages and for less than all pages in said erase sector.
6. A method according to claim 5 and wherein said generating, computing and reading are performed only for said set of logical pages.
7. A method according to claim 1 wherein said reading thresholds are corrected only if the number of bit errors per page is in a process of change of at least a predetermined magnitude.
8. A method according to claim 7 wherein said reading thresholds are corrected only if the difference between the number of bit errors encountered during reconstruction of said current page and the number of bit errors occurring during reconstruction of at least one previous page is larger than a predetermined number.
9. A method according to claim 1 wherein said generating is performed for at least one CSB page residing in a row corresponding to an MSB page also residing in said row, based at least partly on values read from said MSB page.
10. A method according to claim 1 wherein said generating is performed for an LSB page residing in a row corresponding to an MSB and at least one CSB page also residing in said row, based at least partly on values read from at least one of said
MSB and CSB pages.
11. A method according to claim 9 wherein said generating performed for said CSB page is based at least partly on values read on-the-fly from said MSB page.
12. A method according to claim 10 wherein said generating performed for said LSB page is based at least partly on values read on-the-fly from at least one of said MSB and CSB pages.
13. A method according to claim 9 wherein said generating performed for said CSB page is based at least partly on stored values previously read from said MSB page.
14. A method according to claim 10 wherein said generating performed for said LSB page is based at least partly on stored values previously read from at least one of said MSB and CSB pages.
15. A method for using flash memory to store data, the method comprising: writing at least one page of data to said flash memory; reading said at least one page of data from said flash memory using a set of reading thresholds, including generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and subsequently, using said flash memory so as to take into account said bit error characterizing information.
16. A method according to claim 15 wherein said bit error characterizing information comprises identification of a reading threshold which is associated with the bit error.
17. A method according to claim 15 wherein said bit error characterizing information comprises a direction of the bit error.
18. A method according to claim 15 wherein said using comprises reading at least one subsequent page of data so as to take into account said bit error characterizing information.
19. A method according to claim 15 wherein said using comprises detecting portions of said flash memory which suffer from read-disturb phenomenon based on said bit error characterizing information.
20. A method according to claim 19 wherein said detecting comprises detecting an overly large number of bit errors whose source is a reading threshold which is closest, within said set of reading thresholds, to zero voltage, and whose direction is from left to right.
21. A system for generating a set of at least one row-specific reading threshold for reading at least portions of pages of data within an erase sector of a flash memory device, the system comprising: apparatus for predetermining at least one initial reading threshold: a bit error analyzer operative, for at least one current logical page, to generate bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and a bit error-based threshold generator operative to compute at least one row-specific reading threshold based on said bit error characterizing information and on a previous threshold initially comprising said initial threshold and subsequently comprising a row-specific reading threshold computed for a successfully reconstructed previous logical page; and a flash memory cell reader operative to read at least a portion of said current logical page using said at least one row-specific reading threshold.
22. A system for using flash memory to store data, the system comprising: apparatus for writing in flash memory operative to write at least one page of data to the flash memory; a bit error characterizing reader operative to read said at least one page of data from said flash memory using a set of reading thresholds, including generating bit error characterizing information regarding at least one corresponding bit error within at least one cell representing at least a logical portion of at least one successfully reconstructed previous logical page; and a bit error-based controller operative to control said flash memory so as to take into account said bit error characterizing information.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/596,450 US8453022B2 (en) | 2007-12-05 | 2008-09-17 | Apparatus and methods for generating row-specific reading thresholds in flash memory |
Applications Claiming Priority (10)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US99678207P | 2007-12-05 | 2007-12-05 | |
US60/996,782 | 2007-12-05 | ||
US680508P | 2008-01-31 | 2008-01-31 | |
US61/006,805 | 2008-01-31 | ||
US6485308P | 2008-03-31 | 2008-03-31 | |
US61/064,853 | 2008-03-31 | ||
US7146508P | 2008-04-30 | 2008-04-30 | |
US61/071,465 | 2008-04-30 | ||
US12960808P | 2008-07-08 | 2008-07-08 | |
US61/129,608 | 2008-07-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2009072101A2 true WO2009072101A2 (en) | 2009-06-11 |
WO2009072101A3 WO2009072101A3 (en) | 2010-03-04 |
Family
ID=40718290
Family Applications (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IL2008/001232 WO2009072102A2 (en) | 2007-12-05 | 2008-09-17 | System and methods employing mock thresholds to generate actual reading thresholds in flash memory devices |
PCT/IL2008/001231 WO2009072101A2 (en) | 2007-12-05 | 2008-09-17 | Apparatus and methods for generating row-specific reading thresholds in flash memory |
PCT/IL2008/001230 WO2009072100A2 (en) | 2007-12-05 | 2008-09-17 | Systems and methods for temporarily retiring memory portions |
PCT/IL2008/001239 WO2009072104A2 (en) | 2007-12-05 | 2008-09-17 | Flash memory device with physical cell value deterioration accommodation and methods useful in conjunction therewith |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IL2008/001232 WO2009072102A2 (en) | 2007-12-05 | 2008-09-17 | System and methods employing mock thresholds to generate actual reading thresholds in flash memory devices |
Family Applications After (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IL2008/001230 WO2009072100A2 (en) | 2007-12-05 | 2008-09-17 | Systems and methods for temporarily retiring memory portions |
PCT/IL2008/001239 WO2009072104A2 (en) | 2007-12-05 | 2008-09-17 | Flash memory device with physical cell value deterioration accommodation and methods useful in conjunction therewith |
Country Status (2)
Country | Link |
---|---|
US (6) | US8453022B2 (en) |
WO (4) | WO2009072102A2 (en) |
Cited By (64)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7751240B2 (en) | 2007-01-24 | 2010-07-06 | Anobit Technologies Ltd. | Memory device with negative thresholds |
US7773413B2 (en) | 2007-10-08 | 2010-08-10 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells in the presence of temperature variations |
US7821826B2 (en) | 2006-10-30 | 2010-10-26 | Anobit Technologies, Ltd. | Memory cell readout using successive approximation |
US7864573B2 (en) | 2008-02-24 | 2011-01-04 | Anobit Technologies Ltd. | Programming analog memory cells for reduced variance after retention |
US7900102B2 (en) | 2006-12-17 | 2011-03-01 | Anobit Technologies Ltd. | High-speed programming of memory devices |
US7924648B2 (en) | 2006-11-28 | 2011-04-12 | Anobit Technologies Ltd. | Memory power and performance management |
US7924613B1 (en) | 2008-08-05 | 2011-04-12 | Anobit Technologies Ltd. | Data storage in analog memory cells with protection against programming interruption |
US7925936B1 (en) | 2007-07-13 | 2011-04-12 | Anobit Technologies Ltd. | Memory device with non-uniform programming levels |
US7924587B2 (en) | 2008-02-21 | 2011-04-12 | Anobit Technologies Ltd. | Programming of analog memory cells using a single programming pulse per state transition |
US7975192B2 (en) | 2006-10-30 | 2011-07-05 | Anobit Technologies Ltd. | Reading memory cells using multiple thresholds |
US7995388B1 (en) | 2008-08-05 | 2011-08-09 | Anobit Technologies Ltd. | Data storage using modified voltages |
US8000141B1 (en) | 2007-10-19 | 2011-08-16 | Anobit Technologies Ltd. | Compensation for voltage drifts in analog memory cells |
US8001320B2 (en) | 2007-04-22 | 2011-08-16 | Anobit Technologies Ltd. | Command interface for memory devices |
US8000135B1 (en) | 2008-09-14 | 2011-08-16 | Anobit Technologies Ltd. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
US8050086B2 (en) | 2006-05-12 | 2011-11-01 | Anobit Technologies Ltd. | Distortion estimation and cancellation in memory devices |
US8059457B2 (en) | 2008-03-18 | 2011-11-15 | Anobit Technologies Ltd. | Memory device with multiple-accuracy read commands |
US8060806B2 (en) | 2006-08-27 | 2011-11-15 | Anobit Technologies Ltd. | Estimation of non-linear distortion in memory devices |
US8068360B2 (en) | 2007-10-19 | 2011-11-29 | Anobit Technologies Ltd. | Reading analog memory cells using built-in multi-threshold commands |
US8085586B2 (en) | 2007-12-27 | 2011-12-27 | Anobit Technologies Ltd. | Wear level estimation in analog memory cells |
US8151163B2 (en) | 2006-12-03 | 2012-04-03 | Anobit Technologies Ltd. | Automatic defect management in memory devices |
US8151166B2 (en) | 2007-01-24 | 2012-04-03 | Anobit Technologies Ltd. | Reduction of back pattern dependency effects in memory devices |
US8156403B2 (en) | 2006-05-12 | 2012-04-10 | Anobit Technologies Ltd. | Combined distortion estimation and error correction coding for memory devices |
US8156398B2 (en) | 2008-02-05 | 2012-04-10 | Anobit Technologies Ltd. | Parameter estimation based on error correction code parity check equations |
US8169825B1 (en) | 2008-09-02 | 2012-05-01 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells subjected to long retention periods |
US8174857B1 (en) | 2008-12-31 | 2012-05-08 | Anobit Technologies Ltd. | Efficient readout schemes for analog memory cell devices using multiple read threshold sets |
US8174905B2 (en) | 2007-09-19 | 2012-05-08 | Anobit Technologies Ltd. | Programming orders for reducing distortion in arrays of multi-level analog memory cells |
US8209588B2 (en) | 2007-12-12 | 2012-06-26 | Anobit Technologies Ltd. | Efficient interference cancellation in analog memory cell arrays |
US8208304B2 (en) | 2008-11-16 | 2012-06-26 | Anobit Technologies Ltd. | Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N |
US8225181B2 (en) | 2007-11-30 | 2012-07-17 | Apple Inc. | Efficient re-read operations from memory devices |
US8230300B2 (en) | 2008-03-07 | 2012-07-24 | Apple Inc. | Efficient readout from analog memory cells using data compression |
US8228701B2 (en) | 2009-03-01 | 2012-07-24 | Apple Inc. | Selective activation of programming schemes in analog memory cell arrays |
US8234545B2 (en) | 2007-05-12 | 2012-07-31 | Apple Inc. | Data storage with incremental redundancy |
US8239734B1 (en) | 2008-10-15 | 2012-08-07 | Apple Inc. | Efficient data storage in storage device arrays |
US8239735B2 (en) | 2006-05-12 | 2012-08-07 | Apple Inc. | Memory Device with adaptive capacity |
US8238157B1 (en) | 2009-04-12 | 2012-08-07 | Apple Inc. | Selective re-programming of analog memory cells |
US8248831B2 (en) | 2008-12-31 | 2012-08-21 | Apple Inc. | Rejuvenation of analog memory cells |
US8259497B2 (en) | 2007-08-06 | 2012-09-04 | Apple Inc. | Programming schemes for multi-level analog memory cells |
US8259506B1 (en) | 2009-03-25 | 2012-09-04 | Apple Inc. | Database of memory read thresholds |
US8261159B1 (en) | 2008-10-30 | 2012-09-04 | Apple, Inc. | Data scrambling schemes for memory devices |
US8270246B2 (en) | 2007-11-13 | 2012-09-18 | Apple Inc. | Optimized selection of memory chips in multi-chips memory devices |
US8369141B2 (en) | 2007-03-12 | 2013-02-05 | Apple Inc. | Adaptive estimation of memory cell read thresholds |
US8400858B2 (en) | 2008-03-18 | 2013-03-19 | Apple Inc. | Memory device with reduced sense time readout |
US8429493B2 (en) | 2007-05-12 | 2013-04-23 | Apple Inc. | Memory device with internal signap processing unit |
US8479080B1 (en) | 2009-07-12 | 2013-07-02 | Apple Inc. | Adaptive over-provisioning in memory systems |
US8482978B1 (en) | 2008-09-14 | 2013-07-09 | Apple Inc. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
US8493781B1 (en) | 2010-08-12 | 2013-07-23 | Apple Inc. | Interference mitigation using individual word line erasure operations |
US8495465B1 (en) | 2009-10-15 | 2013-07-23 | Apple Inc. | Error correction coding over multiple memory pages |
US8527819B2 (en) | 2007-10-19 | 2013-09-03 | Apple Inc. | Data storage in analog memory cell arrays having erase failures |
US8572423B1 (en) | 2010-06-22 | 2013-10-29 | Apple Inc. | Reducing peak current in memory systems |
US8572311B1 (en) | 2010-01-11 | 2013-10-29 | Apple Inc. | Redundant data storage in multi-die memory systems |
US8595591B1 (en) | 2010-07-11 | 2013-11-26 | Apple Inc. | Interference-aware assignment of programming levels in analog memory cells |
US8645794B1 (en) | 2010-07-31 | 2014-02-04 | Apple Inc. | Data storage in analog memory cells using a non-integer number of bits per cell |
US8677054B1 (en) | 2009-12-16 | 2014-03-18 | Apple Inc. | Memory management schemes for non-volatile memory devices |
US8694853B1 (en) | 2010-05-04 | 2014-04-08 | Apple Inc. | Read commands for reading interfering memory cells |
US8694814B1 (en) | 2010-01-10 | 2014-04-08 | Apple Inc. | Reuse of host hibernation storage space by memory controller |
US8694854B1 (en) | 2010-08-17 | 2014-04-08 | Apple Inc. | Read threshold setting based on soft readout statistics |
US8832354B2 (en) | 2009-03-25 | 2014-09-09 | Apple Inc. | Use of host system resources by memory controller |
US8856475B1 (en) | 2010-08-01 | 2014-10-07 | Apple Inc. | Efficient selection of memory blocks for compaction |
US8924661B1 (en) | 2009-01-18 | 2014-12-30 | Apple Inc. | Memory system including a controller and processors associated with memory devices |
US8949684B1 (en) | 2008-09-02 | 2015-02-03 | Apple Inc. | Segmented data storage |
US9021181B1 (en) | 2010-09-27 | 2015-04-28 | Apple Inc. | Memory management for unifying memory cell conditions by using maximum time intervals |
US9104580B1 (en) | 2010-07-27 | 2015-08-11 | Apple Inc. | Cache memory for hybrid disk drives |
US11556416B2 (en) | 2021-05-05 | 2023-01-17 | Apple Inc. | Controlling memory readout reliability and throughput by adjusting distance between read thresholds |
US11847342B2 (en) | 2021-07-28 | 2023-12-19 | Apple Inc. | Efficient transfer of hard data and confidence levels in reading a nonvolatile memory |
Families Citing this family (297)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8645793B2 (en) * | 2008-06-03 | 2014-02-04 | Marvell International Ltd. | Statistical tracking for flash memory |
US7941590B2 (en) * | 2006-11-06 | 2011-05-10 | Marvell World Trade Ltd. | Adaptive read and write systems and methods for memory cells |
US7809900B2 (en) * | 2006-11-24 | 2010-10-05 | Sandforce, Inc. | System, method, and computer program product for delaying an operation that reduces a lifetime of memory |
US7904619B2 (en) | 2006-11-24 | 2011-03-08 | Sandforce, Inc. | System, method, and computer program product for reducing memory write operations using difference information |
US7747813B2 (en) * | 2006-11-24 | 2010-06-29 | Sandforce, Inc. | Multi-memory device system and method for managing a lifetime thereof |
US7710777B1 (en) * | 2006-12-20 | 2010-05-04 | Marvell International Ltd. | Semi-volatile NAND flash memory |
US8031526B1 (en) | 2007-08-23 | 2011-10-04 | Marvell International Ltd. | Write pre-compensation for nonvolatile memory |
US8189381B1 (en) | 2007-08-28 | 2012-05-29 | Marvell International Ltd. | System and method for reading flash memory cells |
US8085605B2 (en) | 2007-08-29 | 2011-12-27 | Marvell World Trade Ltd. | Sequence detection for flash memory with inter-cell interference |
WO2009095902A2 (en) | 2008-01-31 | 2009-08-06 | Densbits Technologies Ltd. | Systems and methods for handling immediate data errors in flash memory |
US8650352B2 (en) * | 2007-09-20 | 2014-02-11 | Densbits Technologies Ltd. | Systems and methods for determining logical values of coupled flash memory cells |
US8694715B2 (en) | 2007-10-22 | 2014-04-08 | Densbits Technologies Ltd. | Methods for adaptively programming flash memory devices and flash memory systems incorporating same |
WO2009053961A2 (en) | 2007-10-25 | 2009-04-30 | Densbits Technologies Ltd. | Systems and methods for multiple coding rates in flash devices |
US7903486B2 (en) | 2007-11-19 | 2011-03-08 | Sandforce, Inc. | System, method, and computer program product for increasing a lifetime of a plurality of blocks of memory |
US8607128B2 (en) * | 2007-12-05 | 2013-12-10 | Densbits Technologies Ltd. | Low power chien-search based BCH/RS decoding system for flash memory, mobile communications devices and other applications |
US8453022B2 (en) | 2007-12-05 | 2013-05-28 | Densbits Technologies Ltd. | Apparatus and methods for generating row-specific reading thresholds in flash memory |
WO2009072103A2 (en) | 2007-12-05 | 2009-06-11 | Densbits Technologies Ltd. | Flash memory apparatus and methods using a plurality of decoding stages including optional use of concatenated bch codes and/or designation of 'first below' cells |
US8359516B2 (en) | 2007-12-12 | 2013-01-22 | Densbits Technologies Ltd. | Systems and methods for error correction and decoding on multi-level physical media |
WO2009074979A2 (en) | 2007-12-12 | 2009-06-18 | Densbits Technologies Ltd. | Chien-search system employing a clock-gating scheme to save power for error correction decoder and other applications |
WO2009078006A2 (en) | 2007-12-18 | 2009-06-25 | Densbits Technologies Ltd. | Apparatus for coding at a plurality of rates in multi-level flash memory systems, and methods useful in conjunction therewith |
US8621137B2 (en) | 2007-12-27 | 2013-12-31 | Sandisk Enterprise Ip Llc | Metadata rebuild in a flash memory controller following a loss of power |
JP4461170B2 (en) | 2007-12-28 | 2010-05-12 | 株式会社東芝 | Memory system |
US8972472B2 (en) | 2008-03-25 | 2015-03-03 | Densbits Technologies Ltd. | Apparatus and methods for hardware-efficient unbiased rounding |
JP4439569B2 (en) * | 2008-04-24 | 2010-03-24 | 株式会社東芝 | Memory system |
JP2009266349A (en) * | 2008-04-28 | 2009-11-12 | Toshiba Corp | Nonvolatile semiconductor memory device |
US8332725B2 (en) | 2008-08-20 | 2012-12-11 | Densbits Technologies Ltd. | Reprogramming non volatile memory portions |
CN102272731A (en) * | 2008-11-10 | 2011-12-07 | 弗森-艾奥公司 | Apparatus, system, and method for predicting failures in solid-state storage |
US9063874B2 (en) | 2008-11-10 | 2015-06-23 | SanDisk Technologies, Inc. | Apparatus, system, and method for wear management |
TWI410976B (en) * | 2008-11-18 | 2013-10-01 | Lite On It Corp | Reliability test method for solid storage medium |
US8127185B2 (en) | 2009-01-23 | 2012-02-28 | Micron Technology, Inc. | Memory devices and methods for managing error regions |
US8276042B2 (en) | 2009-02-03 | 2012-09-25 | Micron Technology, Inc. | Determining sector status in a memory device |
US8266503B2 (en) | 2009-03-13 | 2012-09-11 | Fusion-Io | Apparatus, system, and method for using multi-level cell storage in a single-level cell mode |
US8819385B2 (en) | 2009-04-06 | 2014-08-26 | Densbits Technologies Ltd. | Device and method for managing a flash memory |
US8458574B2 (en) | 2009-04-06 | 2013-06-04 | Densbits Technologies Ltd. | Compact chien-search based decoding apparatus and method |
US8572443B2 (en) * | 2009-04-08 | 2013-10-29 | International Business Machines Corporation | System, method, and computer program product for determining a retention behavior for at least one block of a memory device having finite endurance and/or retention |
US20100262755A1 (en) * | 2009-04-10 | 2010-10-14 | Honeywell International Inc. | Memory systems for computing devices and systems |
US8566510B2 (en) | 2009-05-12 | 2013-10-22 | Densbits Technologies Ltd. | Systems and method for flash memory management |
US8281227B2 (en) * | 2009-05-18 | 2012-10-02 | Fusion-10, Inc. | Apparatus, system, and method to increase data integrity in a redundant storage system |
US8140712B2 (en) * | 2009-07-17 | 2012-03-20 | Sandforce, Inc. | System, method, and computer program product for inserting a gap in information sent from a drive to a host device |
US8516166B2 (en) * | 2009-07-20 | 2013-08-20 | Lsi Corporation | System, method, and computer program product for reducing a rate of data transfer to at least a portion of memory |
US20110035540A1 (en) * | 2009-08-10 | 2011-02-10 | Adtron, Inc. | Flash blade system architecture and method |
US9330767B1 (en) | 2009-08-26 | 2016-05-03 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Flash memory module and method for programming a page of flash memory cells |
US8868821B2 (en) | 2009-08-26 | 2014-10-21 | Densbits Technologies Ltd. | Systems and methods for pre-equalization and code design for a flash memory |
US8995197B1 (en) | 2009-08-26 | 2015-03-31 | Densbits Technologies Ltd. | System and methods for dynamic erase and program control for flash memory device memories |
US8305812B2 (en) * | 2009-08-26 | 2012-11-06 | Densbits Technologies Ltd. | Flash memory module and method for programming a page of flash memory cells |
CN102004701B (en) * | 2009-08-28 | 2013-01-09 | 炬才微电子(深圳)有限公司 | Method and device for distributing secondary memory |
US8730729B2 (en) | 2009-10-15 | 2014-05-20 | Densbits Technologies Ltd. | Systems and methods for averaging error rates in non-volatile devices and storage systems |
US8724387B2 (en) | 2009-10-22 | 2014-05-13 | Densbits Technologies Ltd. | Method, system, and computer readable medium for reading and programming flash memory cells using multiple bias voltages |
US8312349B2 (en) * | 2009-10-27 | 2012-11-13 | Micron Technology, Inc. | Error detection/correction based memory management |
US8634240B2 (en) | 2009-10-28 | 2014-01-21 | SanDisk Technologies, Inc. | Non-volatile memory and method with accelerated post-write read to manage errors |
US8214700B2 (en) * | 2009-10-28 | 2012-07-03 | Sandisk Technologies Inc. | Non-volatile memory and method with post-write read and adaptive re-write to manage errors |
US8423866B2 (en) * | 2009-10-28 | 2013-04-16 | SanDisk Technologies, Inc. | Non-volatile memory and method with post-write read and adaptive re-write to manage errors |
US8626988B2 (en) | 2009-11-19 | 2014-01-07 | Densbits Technologies Ltd. | System and method for uncoded bit error rate equalization via interleaving |
US9037777B2 (en) * | 2009-12-22 | 2015-05-19 | Densbits Technologies Ltd. | Device, system, and method for reducing program/read disturb in flash arrays |
US8607124B2 (en) | 2009-12-24 | 2013-12-10 | Densbits Technologies Ltd. | System and method for setting a flash memory cell read threshold |
WO2011094454A2 (en) | 2010-01-27 | 2011-08-04 | Fusion-Io, Inc. | Apparatus, system, and method for determining a read voltage threshold for solid-state storage media |
US8380915B2 (en) | 2010-01-27 | 2013-02-19 | Fusion-Io, Inc. | Apparatus, system, and method for managing solid-state storage media |
US8854882B2 (en) | 2010-01-27 | 2014-10-07 | Intelligent Intellectual Property Holdings 2 Llc | Configuring storage cells |
US8661184B2 (en) | 2010-01-27 | 2014-02-25 | Fusion-Io, Inc. | Managing non-volatile media |
US9785561B2 (en) * | 2010-02-17 | 2017-10-10 | International Business Machines Corporation | Integrating a flash cache into large storage systems |
US8341502B2 (en) * | 2010-02-28 | 2012-12-25 | Densbits Technologies Ltd. | System and method for multi-dimensional decoding |
WO2011113034A2 (en) | 2010-03-12 | 2011-09-15 | Sandforce, Inc. | Ldpc erasure decoding for flash memories |
US9245653B2 (en) | 2010-03-15 | 2016-01-26 | Intelligent Intellectual Property Holdings 2 Llc | Reduced level cell mode for non-volatile memory |
US8527840B2 (en) | 2010-04-06 | 2013-09-03 | Densbits Technologies Ltd. | System and method for restoring damaged data programmed on a flash device |
US8516274B2 (en) | 2010-04-06 | 2013-08-20 | Densbits Technologies Ltd. | Method, system and medium for analog encryption in a flash memory |
US8745317B2 (en) | 2010-04-07 | 2014-06-03 | Densbits Technologies Ltd. | System and method for storing information in a multi-level cell memory |
US9021177B2 (en) | 2010-04-29 | 2015-04-28 | Densbits Technologies Ltd. | System and method for allocating and using spare blocks in a flash memory |
US8861727B2 (en) * | 2010-05-19 | 2014-10-14 | Cleversafe, Inc. | Storage of sensitive data in a dispersed storage network |
US8621321B2 (en) | 2010-07-01 | 2013-12-31 | Densbits Technologies Ltd. | System and method for multi-dimensional encoding and decoding |
US8539311B2 (en) | 2010-07-01 | 2013-09-17 | Densbits Technologies Ltd. | System and method for data recovery in multi-level cell memories |
US8819503B2 (en) | 2010-07-02 | 2014-08-26 | Stec, Inc. | Apparatus and method for determining an operating condition of a memory cell based on cycle information |
US20120008414A1 (en) | 2010-07-06 | 2012-01-12 | Michael Katz | Systems and methods for storing, retrieving, and adjusting read thresholds in flash memory storage system |
US8737141B2 (en) | 2010-07-07 | 2014-05-27 | Stec, Inc. | Apparatus and method for determining an operating condition of a memory cell based on cycle information |
US8305807B2 (en) | 2010-07-09 | 2012-11-06 | Sandisk Technologies Inc. | Detection of broken word-lines in memory arrays |
US8432732B2 (en) | 2010-07-09 | 2013-04-30 | Sandisk Technologies Inc. | Detection of word-line leakage in memory arrays |
US8514630B2 (en) | 2010-07-09 | 2013-08-20 | Sandisk Technologies Inc. | Detection of word-line leakage in memory arrays: current based approach |
US8737136B2 (en) | 2010-07-09 | 2014-05-27 | Stec, Inc. | Apparatus and method for determining a read level of a memory cell based on cycle information |
US8964464B2 (en) | 2010-08-24 | 2015-02-24 | Densbits Technologies Ltd. | System and method for accelerated sampling |
CN102385902A (en) * | 2010-09-01 | 2012-03-21 | 建兴电子科技股份有限公司 | Solid state storage device and data control method thereof |
US8508995B2 (en) | 2010-09-15 | 2013-08-13 | Densbits Technologies Ltd. | System and method for adjusting read voltage thresholds in memories |
US9063878B2 (en) | 2010-11-03 | 2015-06-23 | Densbits Technologies Ltd. | Method, system and computer readable medium for copy back |
US8850100B2 (en) | 2010-12-07 | 2014-09-30 | Densbits Technologies Ltd. | Interleaving codeword portions between multiple planes and/or dies of a flash memory device |
US8719663B2 (en) | 2010-12-12 | 2014-05-06 | Lsi Corporation | Cross-decoding for non-volatile storage |
US10402268B2 (en) * | 2011-02-01 | 2019-09-03 | Pure Storage, Inc. | Utilizing a dispersed storage network access token module to acquire digital content from a digital content provider |
US8909851B2 (en) | 2011-02-08 | 2014-12-09 | SMART Storage Systems, Inc. | Storage control system with change logging mechanism and method of operation thereof |
US10079068B2 (en) | 2011-02-23 | 2018-09-18 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Devices and method for wear estimation based memory management |
US8693258B2 (en) | 2011-03-17 | 2014-04-08 | Densbits Technologies Ltd. | Obtaining soft information using a hard interface |
US8935466B2 (en) | 2011-03-28 | 2015-01-13 | SMART Storage Systems, Inc. | Data storage system with non-volatile memory and method of operation thereof |
US9047955B2 (en) | 2011-03-30 | 2015-06-02 | Stec, Inc. | Adjusting operating parameters for memory cells based on wordline address and cycle information |
US8990665B1 (en) | 2011-04-06 | 2015-03-24 | Densbits Technologies Ltd. | System, method and computer program product for joint search of a read threshold and soft decoding |
US20120272036A1 (en) * | 2011-04-22 | 2012-10-25 | Naveen Muralimanohar | Adaptive memory system |
US8638600B2 (en) | 2011-04-22 | 2014-01-28 | Hewlett-Packard Development Company, L.P. | Random-access memory with dynamically adjustable endurance and retention |
US8488387B2 (en) * | 2011-05-02 | 2013-07-16 | Macronix International Co., Ltd. | Thermally assisted dielectric charge trapping flash |
US9001590B2 (en) | 2011-05-02 | 2015-04-07 | Macronix International Co., Ltd. | Method for operating a semiconductor structure |
US8379454B2 (en) | 2011-05-05 | 2013-02-19 | Sandisk Technologies Inc. | Detection of broken word-lines in memory arrays |
US8958242B2 (en) * | 2011-05-05 | 2015-02-17 | Micron Technology, Inc. | Thermal treatment of flash memories |
US9195592B1 (en) | 2011-05-12 | 2015-11-24 | Densbits Technologies Ltd. | Advanced management of a non-volatile memory |
US9501392B1 (en) | 2011-05-12 | 2016-11-22 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Management of a non-volatile memory module |
US9110785B1 (en) | 2011-05-12 | 2015-08-18 | Densbits Technologies Ltd. | Ordered merge of data sectors that belong to memory space portions |
US9372792B1 (en) | 2011-05-12 | 2016-06-21 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Advanced management of a non-volatile memory |
US9396106B2 (en) | 2011-05-12 | 2016-07-19 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Advanced management of a non-volatile memory |
US8996790B1 (en) | 2011-05-12 | 2015-03-31 | Densbits Technologies Ltd. | System and method for flash memory management |
US9141528B2 (en) | 2011-05-17 | 2015-09-22 | Sandisk Technologies Inc. | Tracking and handling of super-hot data in non-volatile memory systems |
US9176864B2 (en) * | 2011-05-17 | 2015-11-03 | SanDisk Technologies, Inc. | Non-volatile memory and method having block management with hot/cold data sorting |
US8667211B2 (en) | 2011-06-01 | 2014-03-04 | Densbits Technologies Ltd. | System and method for managing a non-volatile memory |
US9021227B2 (en) * | 2011-06-22 | 2015-04-28 | Intel Corporation | Drift management in a phase change memory and switch (PCMS) memory device |
US8726104B2 (en) | 2011-07-28 | 2014-05-13 | Sandisk Technologies Inc. | Non-volatile memory and method with accelerated post-write read using combined verification of multiple pages |
US8750042B2 (en) | 2011-07-28 | 2014-06-10 | Sandisk Technologies Inc. | Combined simultaneous sensing of multiple wordlines in a post-write read (PWR) and detection of NAND failures |
US8775901B2 (en) | 2011-07-28 | 2014-07-08 | SanDisk Technologies, Inc. | Data recovery for defective word lines during programming of non-volatile memory arrays |
US8588003B1 (en) | 2011-08-01 | 2013-11-19 | Densbits Technologies Ltd. | System, method and computer program product for programming and for recovering from a power failure |
WO2013030866A1 (en) * | 2011-08-29 | 2013-03-07 | Hitachi, Ltd. | Semiconductor storage device comprising electrically rewritable nonvolatile semiconductor memory |
US9098399B2 (en) | 2011-08-31 | 2015-08-04 | SMART Storage Systems, Inc. | Electronic system with storage management mechanism and method of operation thereof |
US9021231B2 (en) | 2011-09-02 | 2015-04-28 | SMART Storage Systems, Inc. | Storage control system with write amplification control mechanism and method of operation thereof |
US9063844B2 (en) | 2011-09-02 | 2015-06-23 | SMART Storage Systems, Inc. | Non-volatile memory management system with time measure mechanism and method of operation thereof |
US9021319B2 (en) * | 2011-09-02 | 2015-04-28 | SMART Storage Systems, Inc. | Non-volatile memory management system with load leveling and method of operation thereof |
US8553468B2 (en) | 2011-09-21 | 2013-10-08 | Densbits Technologies Ltd. | System and method for managing erase operations in a non-volatile memory |
US8555130B2 (en) * | 2011-10-04 | 2013-10-08 | Cleversafe, Inc. | Storing encoded data slices in a dispersed storage unit |
US8949553B2 (en) | 2011-10-28 | 2015-02-03 | Dell Products L.P. | System and method for retention of historical data in storage resources |
US10359949B2 (en) * | 2011-10-31 | 2019-07-23 | Apple Inc. | Systems and methods for obtaining and using nonvolatile memory health information |
US8938658B2 (en) | 2011-11-07 | 2015-01-20 | Sandisk Enterprise Ip Llc | Statistical read comparison signal generation for memory systems |
US9166626B2 (en) | 2011-11-18 | 2015-10-20 | Korea Advanced Institute Of Science And Technology | Encoding, decoding, and multi-stage decoding circuits for concatenated BCH, and error correction circuit of flash memory device using the same |
US9286205B2 (en) * | 2011-12-20 | 2016-03-15 | Intel Corporation | Apparatus and method for phase change memory drift management |
US9269448B2 (en) | 2012-01-27 | 2016-02-23 | Sk Hynix Memory Solutions Inc. | Generating soft read values using multiple reads and/or bins |
US9239781B2 (en) | 2012-02-07 | 2016-01-19 | SMART Storage Systems, Inc. | Storage control system with erase block mechanism and method of operation thereof |
US8996788B2 (en) | 2012-02-09 | 2015-03-31 | Densbits Technologies Ltd. | Configurable flash interface |
US8947941B2 (en) | 2012-02-09 | 2015-02-03 | Densbits Technologies Ltd. | State responsive operations relating to flash memory cells |
US9195586B2 (en) | 2012-02-23 | 2015-11-24 | Hgst Technologies Santa Ana, Inc. | Determining bias information for offsetting operating variations in memory cells based on wordline address |
US8838881B2 (en) | 2012-03-01 | 2014-09-16 | Seagate Technology Llc | Transfer command with specified sense threshold vector component |
US8943384B2 (en) * | 2012-04-12 | 2015-01-27 | Seagate Technology Llc | Using a soft decoder with hard data |
US8996793B1 (en) | 2012-04-24 | 2015-03-31 | Densbits Technologies Ltd. | System, method and computer readable medium for generating soft information |
US9003224B2 (en) * | 2012-04-25 | 2015-04-07 | Western Digital Technologies, Inc. | Managing unreliable memory in data storage systems |
US8856611B2 (en) | 2012-08-04 | 2014-10-07 | Lsi Corporation | Soft-decision compensation for flash channel variation |
US8839073B2 (en) * | 2012-05-04 | 2014-09-16 | Lsi Corporation | Zero-one balance management in a solid-state disk controller |
US8838937B1 (en) | 2012-05-23 | 2014-09-16 | Densbits Technologies Ltd. | Methods, systems and computer readable medium for writing and reading data |
US9251019B2 (en) | 2012-05-29 | 2016-02-02 | SanDisk Technologies, Inc. | Apparatus, system and method for managing solid-state retirement |
US8879325B1 (en) | 2012-05-30 | 2014-11-04 | Densbits Technologies Ltd. | System, method and computer program product for processing read threshold information and for reading a flash memory module |
US8949689B2 (en) | 2012-06-11 | 2015-02-03 | SMART Storage Systems, Inc. | Storage control system with data management mechanism and method of operation thereof |
US8904093B1 (en) * | 2012-06-15 | 2014-12-02 | Juniper Networks, Inc. | Managing lifetime of limited usage storage devices in a caching system |
US8566671B1 (en) | 2012-06-29 | 2013-10-22 | Sandisk Technologies Inc. | Configurable accelerated post-write read to manage errors |
US8856431B2 (en) | 2012-08-02 | 2014-10-07 | Lsi Corporation | Mixed granularity higher-level redundancy for non-volatile memory |
US9239754B2 (en) | 2012-08-04 | 2016-01-19 | Seagate Technology Llc | Single read based soft-decision decoding of non-volatile memory |
US9699263B1 (en) | 2012-08-17 | 2017-07-04 | Sandisk Technologies Llc. | Automatic read and write acceleration of data accessed by virtual machines |
US8792281B2 (en) | 2012-08-21 | 2014-07-29 | Apple Inc. | Read threshold estimation in analog memory cells using simultaneous multi-voltage sense |
US9921954B1 (en) | 2012-08-27 | 2018-03-20 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Method and system for split flash memory management between host and storage controller |
US8914696B2 (en) | 2012-08-29 | 2014-12-16 | Seagate Technology Llc | Flash memory read scrub and channel tracking |
US8832530B2 (en) * | 2012-09-26 | 2014-09-09 | Intel Corporation | Techniques associated with a read and write window budget for a two level memory system |
US9847139B2 (en) | 2012-10-01 | 2017-12-19 | Seagate Technology Llp | Flash channel parameter management with read scrub |
KR101934892B1 (en) * | 2012-10-17 | 2019-01-04 | 삼성전자 주식회사 | Method for determining deterioration state of memory device and memory system using method thereof |
US9361167B2 (en) * | 2012-10-24 | 2016-06-07 | SanDisk Technologies, Inc. | Bit error rate estimation for wear leveling and for block selection based on data type |
US9368225B1 (en) | 2012-11-21 | 2016-06-14 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Determining read thresholds based upon read error direction statistics |
US9671962B2 (en) | 2012-11-30 | 2017-06-06 | Sandisk Technologies Llc | Storage control system with data management mechanism of parity and method of operation thereof |
US9501398B2 (en) | 2012-12-26 | 2016-11-22 | Sandisk Technologies Llc | Persistent storage device with NVRAM for staging writes |
US9239751B1 (en) | 2012-12-27 | 2016-01-19 | Sandisk Enterprise Ip Llc | Compressing data from multiple reads for error control management in memory systems |
US9430339B1 (en) | 2012-12-27 | 2016-08-30 | Marvell International Ltd. | Method and apparatus for using wear-out blocks in nonvolatile memory |
US9612948B2 (en) | 2012-12-27 | 2017-04-04 | Sandisk Technologies Llc | Reads and writes between a contiguous data block and noncontiguous sets of logical address blocks in a persistent storage device |
US9454420B1 (en) | 2012-12-31 | 2016-09-27 | Sandisk Technologies Llc | Method and system of reading threshold voltage equalization |
US9069659B1 (en) | 2013-01-03 | 2015-06-30 | Densbits Technologies Ltd. | Read threshold determination using reference read threshold |
US9123445B2 (en) | 2013-01-22 | 2015-09-01 | SMART Storage Systems, Inc. | Storage control system with data management mechanism and method of operation thereof |
US9329928B2 (en) | 2013-02-20 | 2016-05-03 | Sandisk Enterprise IP LLC. | Bandwidth optimization in a non-volatile memory system |
US9214965B2 (en) | 2013-02-20 | 2015-12-15 | Sandisk Enterprise Ip Llc | Method and system for improving data integrity in non-volatile storage |
US9349476B2 (en) * | 2013-02-21 | 2016-05-24 | Sandisk Technologies Inc. | Methods, systems, and computer readable media for early detection of potential flash failures using an adaptive system level algorithm based on flash program verify |
US9183137B2 (en) | 2013-02-27 | 2015-11-10 | SMART Storage Systems, Inc. | Storage control system with data management mechanism and method of operation thereof |
US10521339B2 (en) * | 2013-02-28 | 2019-12-31 | Technion Research And Development Foundation Ltd. | Retired page utilization (RPU) for improved write capacity of solid state drives |
US8972776B2 (en) | 2013-03-06 | 2015-03-03 | Seagate Technology, Llc | Partial R-block recycling |
US9470720B2 (en) | 2013-03-08 | 2016-10-18 | Sandisk Technologies Llc | Test system with localized heating and method of manufacture thereof |
US9870830B1 (en) * | 2013-03-14 | 2018-01-16 | Sandisk Technologies Llc | Optimal multilevel sensing for reading data from a storage medium |
US9092310B2 (en) | 2013-03-15 | 2015-07-28 | Seagate Technology Llc | Host command based read disturb methodology |
US9367246B2 (en) | 2013-03-15 | 2016-06-14 | Sandisk Technologies Inc. | Performance optimization of data transfer for soft information generation |
US9244763B1 (en) | 2013-03-15 | 2016-01-26 | Sandisk Enterprise Ip Llc | System and method for updating a reading threshold voltage based on symbol transition information |
US9092350B1 (en) | 2013-03-15 | 2015-07-28 | Sandisk Enterprise Ip Llc | Detection and handling of unbalanced errors in interleaved codewords |
US9236886B1 (en) | 2013-03-15 | 2016-01-12 | Sandisk Enterprise Ip Llc | Universal and reconfigurable QC-LDPC encoder |
US9136877B1 (en) | 2013-03-15 | 2015-09-15 | Sandisk Enterprise Ip Llc | Syndrome layered decoding for LDPC codes |
US9032264B2 (en) * | 2013-03-21 | 2015-05-12 | Kabushiki Kaisha Toshiba | Test method for nonvolatile memory |
US9043780B2 (en) | 2013-03-27 | 2015-05-26 | SMART Storage Systems, Inc. | Electronic system with system modification control mechanism and method of operation thereof |
US9170941B2 (en) | 2013-04-05 | 2015-10-27 | Sandisk Enterprises IP LLC | Data hardening in a storage system |
US10049037B2 (en) | 2013-04-05 | 2018-08-14 | Sandisk Enterprise Ip Llc | Data management in a storage system |
US9543025B2 (en) | 2013-04-11 | 2017-01-10 | Sandisk Technologies Llc | Storage control system with power-off time estimation mechanism and method of operation thereof |
US10546648B2 (en) | 2013-04-12 | 2020-01-28 | Sandisk Technologies Llc | Storage control system with data management mechanism and method of operation thereof |
US9159437B2 (en) | 2013-06-11 | 2015-10-13 | Sandisk Enterprise IP LLC. | Device and method for resolving an LM flag issue |
US9136876B1 (en) | 2013-06-13 | 2015-09-15 | Densbits Technologies Ltd. | Size limited multi-dimensional decoding |
JP2015001908A (en) * | 2013-06-17 | 2015-01-05 | 富士通株式会社 | Information processing device, control circuit, control program, and control method |
US9313874B2 (en) | 2013-06-19 | 2016-04-12 | SMART Storage Systems, Inc. | Electronic system with heat extraction and method of manufacture thereof |
US9898056B2 (en) | 2013-06-19 | 2018-02-20 | Sandisk Technologies Llc | Electronic assembly with thermal channel and method of manufacture thereof |
US9367353B1 (en) | 2013-06-25 | 2016-06-14 | Sandisk Technologies Inc. | Storage control system with power throttling mechanism and method of operation thereof |
US9244519B1 (en) | 2013-06-25 | 2016-01-26 | Smart Storage Systems. Inc. | Storage system with data transfer rate adjustment for power throttling |
US9183070B2 (en) | 2013-07-24 | 2015-11-10 | Micron Technology, Inc. | Resting blocks of memory cells in response to the blocks being deemed to fail |
US9384126B1 (en) | 2013-07-25 | 2016-07-05 | Sandisk Technologies Inc. | Methods and systems to avoid false negative results in bloom filters implemented in non-volatile data storage systems |
US9524235B1 (en) | 2013-07-25 | 2016-12-20 | Sandisk Technologies Llc | Local hash value generation in non-volatile data storage systems |
US9146850B2 (en) | 2013-08-01 | 2015-09-29 | SMART Storage Systems, Inc. | Data storage system with dynamic read threshold mechanism and method of operation thereof |
US9361222B2 (en) | 2013-08-07 | 2016-06-07 | SMART Storage Systems, Inc. | Electronic system with storage drive life estimation mechanism and method of operation thereof |
US9448946B2 (en) | 2013-08-07 | 2016-09-20 | Sandisk Technologies Llc | Data storage system with stale data mechanism and method of operation thereof |
US9431113B2 (en) | 2013-08-07 | 2016-08-30 | Sandisk Technologies Llc | Data storage system with dynamic erase block grouping mechanism and method of operation thereof |
KR102065664B1 (en) * | 2013-08-09 | 2020-01-13 | 삼성전자 주식회사 | Method for estimating degradation state of memory device and wear leveling method in memory system using the same |
US9880926B1 (en) | 2013-08-20 | 2018-01-30 | Seagate Technology Llc | Log structured reserved zone for a data storage device |
US9235509B1 (en) | 2013-08-26 | 2016-01-12 | Sandisk Enterprise Ip Llc | Write amplification reduction by delaying read access to data written during garbage collection |
US9639463B1 (en) | 2013-08-26 | 2017-05-02 | Sandisk Technologies Llc | Heuristic aware garbage collection scheme in storage systems |
JP5911834B2 (en) * | 2013-09-11 | 2016-04-27 | 株式会社東芝 | Nonvolatile semiconductor memory device |
US9413491B1 (en) | 2013-10-08 | 2016-08-09 | Avago Technologies General Ip (Singapore) Pte. Ltd. | System and method for multiple dimension decoding and encoding a message |
US9397706B1 (en) | 2013-10-09 | 2016-07-19 | Avago Technologies General Ip (Singapore) Pte. Ltd. | System and method for irregular multiple dimension decoding and encoding |
US9786388B1 (en) | 2013-10-09 | 2017-10-10 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Detecting and managing bad columns |
US9348694B1 (en) | 2013-10-09 | 2016-05-24 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Detecting and managing bad columns |
US9298608B2 (en) | 2013-10-18 | 2016-03-29 | Sandisk Enterprise Ip Llc | Biasing for wear leveling in storage systems |
US9442662B2 (en) | 2013-10-18 | 2016-09-13 | Sandisk Technologies Llc | Device and method for managing die groups |
US9436831B2 (en) | 2013-10-30 | 2016-09-06 | Sandisk Technologies Llc | Secure erase in a memory device |
KR102102175B1 (en) * | 2013-11-05 | 2020-04-21 | 삼성전자 주식회사 | Testing method of nonvolatile memory device using variable resistive element |
US9263156B2 (en) | 2013-11-07 | 2016-02-16 | Sandisk Enterprise Ip Llc | System and method for adjusting trip points within a storage device |
US9244785B2 (en) | 2013-11-13 | 2016-01-26 | Sandisk Enterprise Ip Llc | Simulated power failure and data hardening |
US9152555B2 (en) | 2013-11-15 | 2015-10-06 | Sandisk Enterprise IP LLC. | Data management with modular erase in a data storage system |
US9703816B2 (en) | 2013-11-19 | 2017-07-11 | Sandisk Technologies Llc | Method and system for forward reference logging in a persistent datastore |
US9520197B2 (en) | 2013-11-22 | 2016-12-13 | Sandisk Technologies Llc | Adaptive erase of a storage device |
US9520162B2 (en) | 2013-11-27 | 2016-12-13 | Sandisk Technologies Llc | DIMM device controller supervisor |
US9582058B2 (en) | 2013-11-29 | 2017-02-28 | Sandisk Technologies Llc | Power inrush management of storage devices |
US9213601B2 (en) | 2013-12-03 | 2015-12-15 | Sandisk Technologies Inc. | Adaptive data re-compaction after post-write read verification operations |
US9235245B2 (en) | 2013-12-04 | 2016-01-12 | Sandisk Enterprise Ip Llc | Startup performance and power isolation |
US9274882B2 (en) * | 2013-12-04 | 2016-03-01 | International Business Machines Corporation | Page retirement in a NAND flash memory system |
US10733069B2 (en) | 2013-12-04 | 2020-08-04 | International Business Machines Corporation | Page retirement in a NAND flash memory system |
US9262316B2 (en) | 2013-12-09 | 2016-02-16 | International Business Machines Corporation | Recording dwell time in a non-volatile memory system |
US9390003B2 (en) | 2013-12-09 | 2016-07-12 | International Business Machines Corporation | Retirement of physical memory based on dwell time |
GB201322075D0 (en) | 2013-12-13 | 2014-01-29 | Ibm | Device for selecting a level for at least one read voltage |
US9129665B2 (en) | 2013-12-17 | 2015-09-08 | Sandisk Enterprise Ip Llc | Dynamic brownout adjustment in a storage device |
US9645763B2 (en) | 2014-01-13 | 2017-05-09 | Seagate Technology Llc | Framework for balancing robustness and latency during collection of statistics from soft reads |
US9536612B1 (en) | 2014-01-23 | 2017-01-03 | Avago Technologies General Ip (Singapore) Pte. Ltd | Digital signaling processing for three dimensional flash memory arrays |
US10120792B1 (en) | 2014-01-29 | 2018-11-06 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Programming an embedded flash storage device |
US9508437B2 (en) * | 2014-01-30 | 2016-11-29 | Sandisk Technologies Llc | Pattern breaking in multi-die write management |
US9703636B2 (en) | 2014-03-01 | 2017-07-11 | Sandisk Technologies Llc | Firmware reversion trigger and control |
JP6102800B2 (en) * | 2014-03-04 | 2017-03-29 | ソニー株式会社 | Memory controller, storage device, information processing system, and control method therefor. |
US9390814B2 (en) | 2014-03-19 | 2016-07-12 | Sandisk Technologies Llc | Fault detection and prediction for data storage elements |
US9448876B2 (en) | 2014-03-19 | 2016-09-20 | Sandisk Technologies Llc | Fault detection and prediction in storage devices |
US9454448B2 (en) | 2014-03-19 | 2016-09-27 | Sandisk Technologies Llc | Fault testing in storage devices |
US9626400B2 (en) | 2014-03-31 | 2017-04-18 | Sandisk Technologies Llc | Compaction of information in tiered data structure |
US9626399B2 (en) | 2014-03-31 | 2017-04-18 | Sandisk Technologies Llc | Conditional updates for reducing frequency of data modification operations |
US9390021B2 (en) | 2014-03-31 | 2016-07-12 | Sandisk Technologies Llc | Efficient cache utilization in a tiered data structure |
US9697267B2 (en) | 2014-04-03 | 2017-07-04 | Sandisk Technologies Llc | Methods and systems for performing efficient snapshots in tiered data structures |
TWI492234B (en) * | 2014-04-21 | 2015-07-11 | Silicon Motion Inc | Method, memory controller, and memory system for reading data stored in flash memory |
US9542262B1 (en) | 2014-05-29 | 2017-01-10 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Error correction |
US10114557B2 (en) | 2014-05-30 | 2018-10-30 | Sandisk Technologies Llc | Identification of hot regions to enhance performance and endurance of a non-volatile storage device |
US10656840B2 (en) | 2014-05-30 | 2020-05-19 | Sandisk Technologies Llc | Real-time I/O pattern recognition to enhance performance and endurance of a storage device |
US10162748B2 (en) | 2014-05-30 | 2018-12-25 | Sandisk Technologies Llc | Prioritizing garbage collection and block allocation based on I/O history for logical address regions |
US10656842B2 (en) | 2014-05-30 | 2020-05-19 | Sandisk Technologies Llc | Using history of I/O sizes and I/O sequences to trigger coalesced writes in a non-volatile storage device |
US10146448B2 (en) | 2014-05-30 | 2018-12-04 | Sandisk Technologies Llc | Using history of I/O sequences to trigger cached read ahead in a non-volatile storage device |
US10372613B2 (en) | 2014-05-30 | 2019-08-06 | Sandisk Technologies Llc | Using sub-region I/O history to cache repeatedly accessed sub-regions in a non-volatile storage device |
US9703491B2 (en) | 2014-05-30 | 2017-07-11 | Sandisk Technologies Llc | Using history of unaligned writes to cache data and avoid read-modify-writes in a non-volatile storage device |
US9652381B2 (en) | 2014-06-19 | 2017-05-16 | Sandisk Technologies Llc | Sub-block garbage collection |
KR102215741B1 (en) | 2014-06-23 | 2021-02-17 | 삼성전자주식회사 | Storage device including nonvolatile memory and memory controller and operating method of storage device |
US9892033B1 (en) | 2014-06-24 | 2018-02-13 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Management of memory units |
US9972393B1 (en) | 2014-07-03 | 2018-05-15 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Accelerating programming of a flash memory module |
US9584159B1 (en) | 2014-07-03 | 2017-02-28 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Interleaved encoding |
US9449702B1 (en) | 2014-07-08 | 2016-09-20 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Power management |
KR102293082B1 (en) * | 2014-07-29 | 2021-08-26 | 삼성전자주식회사 | Storage device, operation method of storage device and accessing method for accessing storage device |
US9817751B2 (en) * | 2014-09-03 | 2017-11-14 | Apple Inc. | Multi-phase programming schemes for nonvolatile memories |
US9443601B2 (en) | 2014-09-08 | 2016-09-13 | Sandisk Technologies Llc | Holdup capacitor energy harvesting |
US9690655B2 (en) * | 2014-09-30 | 2017-06-27 | EMC IP Holding Company LLC | Method and system for improving flash storage utilization by predicting bad m-pages |
US10365859B2 (en) | 2014-10-21 | 2019-07-30 | International Business Machines Corporation | Storage array management employing a merged background management process |
US9563373B2 (en) | 2014-10-21 | 2017-02-07 | International Business Machines Corporation | Detecting error count deviations for non-volatile memory blocks for advanced non-volatile memory block management |
US9524211B1 (en) | 2014-11-18 | 2016-12-20 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Codeword management |
US9678864B2 (en) * | 2014-12-03 | 2017-06-13 | Seagate Technology Llc | Data reallocation upon detection of errors |
US9990279B2 (en) | 2014-12-23 | 2018-06-05 | International Business Machines Corporation | Page-level health equalization |
US10339048B2 (en) | 2014-12-23 | 2019-07-02 | International Business Machines Corporation | Endurance enhancement scheme using memory re-evaluation |
US10305515B1 (en) | 2015-02-02 | 2019-05-28 | Avago Technologies International Sales Pte. Limited | System and method for encoding using multiple linear feedback shift registers |
US9224492B1 (en) * | 2015-02-17 | 2015-12-29 | Phison Electronics Corp. | Memory management method, memory storage device and memory controlling circuit unit |
US9928925B1 (en) | 2015-02-17 | 2018-03-27 | Darryl G. Walker | Multi-chip non-volatile semiconductor memory package including heater and sensor elements |
US9773563B2 (en) | 2015-03-27 | 2017-09-26 | Toshiba Memory Corporation | Memory controller, memory control method, and coefficient decision method |
US10628255B1 (en) | 2015-06-11 | 2020-04-21 | Avago Technologies International Sales Pte. Limited | Multi-dimensional decoding |
US9496043B1 (en) | 2015-06-24 | 2016-11-15 | International Business Machines Corporation | Dynamically optimizing flash data retention or endurance based on data write frequency |
US9851921B1 (en) | 2015-07-05 | 2017-12-26 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Flash memory chip processing |
KR102393323B1 (en) | 2015-08-24 | 2022-05-03 | 삼성전자주식회사 | Method for operating storage device determining wordlines for writing user data depending on reuse period |
KR102456104B1 (en) | 2015-08-24 | 2022-10-19 | 삼성전자주식회사 | Method for operating storage device changing operation condition depending on data reliability |
KR102333746B1 (en) * | 2015-09-02 | 2021-12-01 | 삼성전자주식회사 | Method for operating storage device managing wear level depending on reuse period |
US10847235B2 (en) | 2015-09-30 | 2020-11-24 | Hewlett Packard Enterprise Development Lp | Remapping operations |
US10192614B2 (en) | 2015-10-30 | 2019-01-29 | Seagate Technology Llc | Adaptive read threshold voltage tracking with gap estimation between default read threshold voltages |
US10347343B2 (en) | 2015-10-30 | 2019-07-09 | Seagate Technology Llc | Adaptive read threshold voltage tracking with separate characterization on each side of voltage distribution about distribution mean |
US9954558B1 (en) | 2016-03-03 | 2018-04-24 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Fast decoding of data stored in a flash memory |
US10496289B2 (en) * | 2016-06-16 | 2019-12-03 | Nuvoton Technology Corporation | System and methods for increasing useful lifetime of a flash memory device |
DE102017112560B4 (en) * | 2016-07-29 | 2020-08-27 | Western Digital Technologies, Inc. | ADAPTIVE WEAR LEVELING |
US10467134B2 (en) | 2016-08-25 | 2019-11-05 | Sandisk Technologies Llc | Dynamic anneal characteristics for annealing non-volatile memory |
US9761290B1 (en) * | 2016-08-25 | 2017-09-12 | Sandisk Technologies Llc | Overheat prevention for annealing non-volatile memory |
US10490234B2 (en) | 2016-10-17 | 2019-11-26 | Seagate Technology Llc | Recovering from data access errors by controlling access to neighboring memory units |
CN106775587B (en) * | 2016-11-30 | 2020-04-14 | 上海兆芯集成电路有限公司 | Method for executing computer instructions and device using same |
US10254981B2 (en) | 2016-12-12 | 2019-04-09 | International Business Machines Corporation | Adaptive health grading for a non-volatile memory |
US10068657B1 (en) | 2017-02-10 | 2018-09-04 | Sandisk Technologies Llc | Detecting misalignment in memory array and adjusting read and verify timing parameters on sub-block and block levels |
US10387239B2 (en) * | 2017-04-10 | 2019-08-20 | Western Digital Technologies, Inc. | Detecting memory failures in the runtime environment |
US10453547B2 (en) | 2017-06-16 | 2019-10-22 | Seagate Technologies Llc | Monitoring a memory for retirement |
KR20190022987A (en) * | 2017-08-25 | 2019-03-07 | 에스케이하이닉스 주식회사 | Data storage device and operating method thereof |
US10354724B2 (en) | 2017-09-15 | 2019-07-16 | Sandisk Technologies Llc | Methods and apparatus for programming barrier modulated memory cells |
US10565051B2 (en) * | 2018-02-06 | 2020-02-18 | Alibaba Group Holding Limited | Accommodating variable page sizes in solid-state drives using customized error correction |
US10559370B2 (en) | 2018-03-22 | 2020-02-11 | Sandisk Technologies Llc | System and method for in-situ programming and read operation adjustments in a non-volatile memory |
US10699797B2 (en) | 2018-04-27 | 2020-06-30 | Seagate Technology Llc | Storage area retirement in a storage device |
US11132247B2 (en) * | 2018-07-30 | 2021-09-28 | Micron Technology, Inc. | Selective bad block untag and bad block reuse |
US10877880B2 (en) * | 2018-10-11 | 2020-12-29 | Micron Technology, Inc. | Unretiring memory device blocks |
JP2021044034A (en) | 2019-09-09 | 2021-03-18 | キオクシア株式会社 | Memory system |
CN113448489A (en) * | 2020-03-25 | 2021-09-28 | 慧荣科技股份有限公司 | Computer readable storage medium, method and apparatus for controlling access of flash memory card |
US11294819B2 (en) | 2020-03-31 | 2022-04-05 | Western Digital Technologies, Inc. | Command optimization through intelligent threshold detection |
US11776629B2 (en) | 2020-08-17 | 2023-10-03 | Micron Technology, Inc. | Threshold voltage based on program/erase cycles |
US11189355B1 (en) | 2020-08-25 | 2021-11-30 | Micron Technology, Inc. | Read window based on program/erase cycles |
US11392312B2 (en) | 2020-08-25 | 2022-07-19 | Micron Technology, Inc. | Read calibration based on ranges of program/erase cycles |
US11430528B2 (en) | 2020-08-25 | 2022-08-30 | Micron Technology, Inc. | Determining a read voltage based on a change in a read window |
US20230367497A1 (en) * | 2022-05-10 | 2023-11-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Memory system, operating method and controller |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7177977B2 (en) * | 2004-03-19 | 2007-02-13 | Sandisk Corporation | Operating non-volatile memory without read disturb limitations |
US20070104004A1 (en) * | 1997-09-08 | 2007-05-10 | So Hock C | Multi-Bit-Per-Cell Flash EEprom Memory with Refresh |
US7290203B2 (en) * | 2004-10-29 | 2007-10-30 | International Business Machines Corporation | Dynamic memory architecture employing passive expiration of data |
US20070253249A1 (en) * | 2006-04-26 | 2007-11-01 | Sang-Gu Kang | Multi-bit nonvolatile memory device and related programming method |
Family Cites Families (295)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4430701A (en) | 1981-08-03 | 1984-02-07 | International Business Machines Corporation | Method and apparatus for a hierarchical paging storage system |
US4463375A (en) * | 1982-09-07 | 1984-07-31 | The Board Of Trustees Of The Leland Standford Junior University | Multiple-measurement noise-reducing system |
US4589084A (en) * | 1983-05-16 | 1986-05-13 | Rca Corporation | Apparatus for symmetrically truncating two's complement binary signals as for use with interleaved quadrature signals |
US4584686A (en) | 1983-12-22 | 1986-04-22 | Optical Storage International | Reed-Solomon error correction apparatus |
US4777589A (en) | 1985-06-28 | 1988-10-11 | Hewlett-Packard Company | Direct input/output in a virtual memory system |
US4866716A (en) | 1987-05-15 | 1989-09-12 | Digital Equipment Corporation | Real-time BCH error correction code decoding mechanism |
US5077737A (en) | 1989-08-18 | 1991-12-31 | Micron Technology, Inc. | Method and apparatus for storing digital data in off-specification dynamic random access memory devices |
DE68920142T2 (en) | 1989-08-24 | 1995-07-13 | Philips Electronics Nv | Method and device for decoding word-protected code words by means of a non-binary BCH code against at least one symbol error. |
US5003597A (en) | 1989-12-21 | 1991-03-26 | Xerox Corporation | Method and apparatus for data encryption |
US5663901A (en) | 1991-04-11 | 1997-09-02 | Sandisk Corporation | Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems |
IT1248564B (en) * | 1991-06-27 | 1995-01-19 | Permelec Spa Nora | ELECTROCHEMICAL DECOMPOSITION OF NEUTRAL SALTS WITHOUT HALOGEN OR ACID CO-PRODUCTION AND ELECTROLYSIS CELL SUITABLE FOR ITS REALIZATION. |
JP3229345B2 (en) | 1991-09-11 | 2001-11-19 | ローム株式会社 | Non-volatile IC memory |
US5657332A (en) | 1992-05-20 | 1997-08-12 | Sandisk Corporation | Soft errors handling in EEPROM devices |
US5740395A (en) | 1992-10-30 | 1998-04-14 | Intel Corporation | Method and apparatus for cleaning up a solid state memory disk storing floating sector data |
DE4410060B4 (en) | 1993-04-08 | 2006-02-09 | Hewlett-Packard Development Co., L.P., Houston | Translating device for converting a virtual memory address into a physical memory address |
US5592641A (en) | 1993-06-30 | 1997-01-07 | Intel Corporation | Method and device for selectively locking write access to blocks in a memory array using write protect inputs and block enabled status |
US5623620A (en) | 1993-06-30 | 1997-04-22 | Intel Corporation | Special test modes for a page buffer shared resource in a memory device |
US5640529A (en) | 1993-07-29 | 1997-06-17 | Intel Corporation | Method and system for performing clean-up of a solid state disk during host command execution |
JPH08137763A (en) | 1994-11-04 | 1996-05-31 | Fujitsu Ltd | Flash memory controller |
US5579356A (en) | 1995-07-28 | 1996-11-26 | Micron Quantum Devices, Inc. | Timer circuit with programmable decode circuitry |
US6728851B1 (en) | 1995-07-31 | 2004-04-27 | Lexar Media, Inc. | Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices |
EP0757355B1 (en) | 1995-07-31 | 2000-04-19 | STMicroelectronics S.r.l. | Mixed parallel-dichotomic serial sensing method for sensing multiple-levels non-volatile memory cells, and sensing circuit actuating such method |
US6081878A (en) | 1997-03-31 | 2000-06-27 | Lexar Media, Inc. | Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices |
US5778430A (en) | 1996-04-19 | 1998-07-07 | Eccs, Inc. | Method and apparatus for computer disk cache management |
US5968198A (en) | 1996-08-16 | 1999-10-19 | Ericsson, Inc. | Decoder utilizing soft information output to minimize error rates |
US5771346A (en) | 1996-10-24 | 1998-06-23 | Micron Quantum Devices, Inc. | Apparatus and method for detecting over-programming condition in multistate memory device |
US5745418A (en) | 1996-11-25 | 1998-04-28 | Macronix International Co., Ltd. | Flash memory mass storage system |
US5956473A (en) | 1996-11-25 | 1999-09-21 | Macronix International Co., Ltd. | Method and system for managing a flash memory mass storage system |
US5982659A (en) * | 1996-12-23 | 1999-11-09 | Lsi Logic Corporation | Memory cell capable of storing more than two logic states by using different via resistances |
DE19880311B3 (en) | 1997-02-12 | 2017-06-22 | Hyundai Electronics America Inc. | Non-volatile memory structure |
US6094465A (en) | 1997-03-21 | 2000-07-25 | Qualcomm Incorporated | Method and apparatus for performing decoding of CRC outer concatenated codes |
US5920578A (en) | 1997-04-23 | 1999-07-06 | Cirrus Logic, Inc. | Method and apparatus for efficiently processing a multi-dimensional code |
JP3565687B2 (en) | 1997-08-06 | 2004-09-15 | 沖電気工業株式会社 | Semiconductor memory device and control method thereof |
US5926409A (en) | 1997-09-05 | 1999-07-20 | Information Storage Devices, Inc. | Method and apparatus for an adaptive ramp amplitude controller in nonvolatile memory application |
US6199188B1 (en) | 1997-10-07 | 2001-03-06 | Quantum Corporation | System for finding roots of degree three and degree four error locator polynomials over GF(2M) |
US6279133B1 (en) | 1997-12-31 | 2001-08-21 | Kawasaki Steel Corporation | Method and apparatus for significantly improving the reliability of multilevel memory architecture |
US6038634A (en) | 1998-02-02 | 2000-03-14 | International Business Machines Corporation | Intra-unit block addressing system for memory |
JP3165099B2 (en) | 1998-02-05 | 2001-05-14 | インターナショナル・ビジネス・マシーンズ・コーポレ−ション | Error correction method and system |
KR100297986B1 (en) | 1998-03-13 | 2001-10-25 | 김영환 | Wear levelling system of flash memory cell array and wear levelling method thereof |
US6209114B1 (en) * | 1998-05-29 | 2001-03-27 | Texas Instruments Incorporated | Efficient hardware implementation of chien search polynomial reduction in reed-solomon decoding |
JP2000067574A (en) | 1998-08-21 | 2000-03-03 | Mitsubishi Electric Corp | Semiconductor memory |
US6192497B1 (en) | 1998-08-27 | 2001-02-20 | Adaptec, Inc. | Parallel Chien search circuit |
US6704902B1 (en) | 1998-09-07 | 2004-03-09 | Sony Corporation | Decoding system for error correction code |
US6637002B1 (en) | 1998-10-21 | 2003-10-21 | Maxtor Corporation | Decoder for error correcting block codes |
US6292918B1 (en) | 1998-11-05 | 2001-09-18 | Qualcomm Incorporated | Efficient iterative decoding |
JP3410036B2 (en) | 1999-02-03 | 2003-05-26 | シャープ株式会社 | Method of writing information to nonvolatile semiconductor memory device |
US6374383B1 (en) | 1999-06-07 | 2002-04-16 | Maxtor Corporation | Determining error locations using error correction codes |
JP4074029B2 (en) | 1999-06-28 | 2008-04-09 | 株式会社東芝 | Flash memory |
US20080209114A1 (en) | 1999-08-04 | 2008-08-28 | Super Talent Electronics, Inc. | Reliability High Endurance Non-Volatile Memory Device with Zone-Based Non-Volatile Memory File System |
US6278633B1 (en) | 1999-11-05 | 2001-08-21 | Multi Level Memory Technology | High bandwidth flash memory that selects programming parameters according to measurements of previous programming operations |
US6560747B1 (en) * | 1999-11-10 | 2003-05-06 | Maxtor Corporation | Error counting mechanism |
US7035892B2 (en) | 1999-12-10 | 2006-04-25 | Broadcom Corporation | Apparatus and method for reducing precision of data |
US8108590B2 (en) | 2000-01-06 | 2012-01-31 | Super Talent Electronics, Inc. | Multi-operation write aggregator using a page buffer and a scratch flash block in each of multiple channels of a large array of flash memory to reduce block wear |
US6259627B1 (en) | 2000-01-27 | 2001-07-10 | Multi Level Memory Technology | Read and write operations using constant row line voltage and variable column line load |
US6532556B1 (en) | 2000-01-27 | 2003-03-11 | Multi Level Memory Technology | Data management for multi-bit-per-cell memories |
US6564306B2 (en) | 2000-04-25 | 2003-05-13 | Hewlett-Packard Development Company, L.P. | Apparatus and method for performing speculative cache directory tag updates |
US6301151B1 (en) | 2000-08-09 | 2001-10-09 | Information Storage Devices, Inc. | Adaptive programming method and apparatus for flash memory analog storage |
US6772274B1 (en) | 2000-09-13 | 2004-08-03 | Lexar Media, Inc. | Flash memory system and method implementing LBA to PBA correlation within flash memory array |
KR100370239B1 (en) | 2000-10-25 | 2003-01-29 | 삼성전자 주식회사 | Memory device for applying to high speed block pipelined reed-solomon decoder and method of memory access and reed-solomon decoder having the memory device |
US6507357B2 (en) | 2000-11-29 | 2003-01-14 | Applied Minds, Inc. | Method and apparatus for maintaining eye contact in teleconferencing using reflected images |
US7170997B2 (en) | 2000-12-07 | 2007-01-30 | Cryptico A/S | Method of generating pseudo-random numbers in an electronic device, and a method of encrypting and decrypting electronic data |
US6349056B1 (en) | 2000-12-28 | 2002-02-19 | Sandisk Corporation | Method and structure for efficient data verification operation for non-volatile memories |
TW539950B (en) | 2000-12-28 | 2003-07-01 | Sony Corp | Data recording device and data write method for flash memory |
KR100381957B1 (en) | 2001-01-04 | 2003-04-26 | 삼성전자주식회사 | Nonvolatile semiconductor memory device and data input/output control method thereof |
US6763424B2 (en) | 2001-01-19 | 2004-07-13 | Sandisk Corporation | Partial block data programming and reading operations in a non-volatile memory |
US20030105620A1 (en) | 2001-01-29 | 2003-06-05 | Matt Bowen | System, method and article of manufacture for interface constructs in a programming language capable of programming hardware architetures |
US6938144B2 (en) | 2001-03-22 | 2005-08-30 | Matsushita Electric Industrial Co., Ltd. | Address conversion unit for memory device |
US6898614B2 (en) | 2001-03-29 | 2005-05-24 | Koninklijke Philips Electronics N.V. | Round-off algorithm without bias for 2's complement data |
US20030192007A1 (en) | 2001-04-19 | 2003-10-09 | Miller David H. | Code-programmable field-programmable architecturally-systolic Reed-Solomon BCH error correction decoder integrated circuit and error correction decoding method |
US6792569B2 (en) | 2001-04-24 | 2004-09-14 | International Business Machines Corporation | Root solver and associated method for solving finite field polynomial equations |
US6370061B1 (en) | 2001-06-19 | 2002-04-09 | Advanced Micro Devices, Inc. | Ceiling test mode to characterize the threshold voltage distribution of over programmed memory cells |
US6532169B1 (en) | 2001-06-26 | 2003-03-11 | Cypress Semiconductor Corp. | SONOS latch and application |
US6961890B2 (en) | 2001-08-16 | 2005-11-01 | Hewlett-Packard Development Company, L.P. | Dynamic variable-length error correction code |
US6678785B2 (en) * | 2001-09-28 | 2004-01-13 | M-Systems Flash Disk Pioneers Ltd. | Flash management system using only sequential write |
US6925007B2 (en) | 2001-10-31 | 2005-08-02 | Sandisk Corporation | Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements |
US6839007B2 (en) * | 2001-11-01 | 2005-01-04 | Qualcomm Incorporated | Inner coding of higher priority data within a digital message |
US6915477B2 (en) * | 2001-12-28 | 2005-07-05 | Lucent Technologies Inc. | Delay sensitive adaptive quality control loop for rate adaptation |
US6621739B2 (en) | 2002-01-18 | 2003-09-16 | Sandisk Corporation | Reducing the effects of noise in non-volatile memories through multiple reads |
US6542407B1 (en) | 2002-01-18 | 2003-04-01 | Sandisk Corporation | Techniques of recovering data from memory cells affected by field coupling with adjacent memory cells |
US6675281B1 (en) | 2002-01-22 | 2004-01-06 | Icreate Technologies Corporation | Distributed mapping scheme for mass storage system |
KR100439507B1 (en) | 2002-03-18 | 2004-07-09 | 삼성전기주식회사 | Data operating method in flash memory card system of high-capacity |
KR20030078453A (en) | 2002-03-29 | 2003-10-08 | 주식회사 엘지이아이 | Method and apparatus for encrypting and decrypting data in wireless lan |
US7010739B1 (en) | 2002-04-11 | 2006-03-07 | Marvell International Ltd. | Error evaluator for inversionless Berlekamp-Massey algorithm in Reed-Solomon decoders |
US6781910B2 (en) | 2002-05-17 | 2004-08-24 | Hewlett-Packard Development Company, L.P. | Small area magnetic memory devices |
US6751766B2 (en) | 2002-05-20 | 2004-06-15 | Sandisk Corporation | Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data |
JP2003346484A (en) | 2002-05-23 | 2003-12-05 | Mitsubishi Electric Corp | Nonvolatile semiconductor storage device |
WO2004001802A2 (en) | 2002-06-21 | 2003-12-31 | Micron Technology, Inc. | Nrom memory cell, memory array, related devices and methods |
US20040015771A1 (en) | 2002-07-16 | 2004-01-22 | Menahem Lasser | Error correction for non-volatile memory |
KR100484147B1 (en) | 2002-07-26 | 2005-04-18 | 삼성전자주식회사 | Flash memory management method |
US6781877B2 (en) * | 2002-09-06 | 2004-08-24 | Sandisk Corporation | Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells |
US6831865B2 (en) | 2002-10-28 | 2004-12-14 | Sandisk Corporation | Maintaining erase counts in non-volatile storage systems |
US6891768B2 (en) | 2002-11-13 | 2005-05-10 | Hewlett-Packard Development Company, L.P. | Power-saving reading of magnetic memory devices |
US7028247B2 (en) | 2002-12-25 | 2006-04-11 | Faraday Technology Corp. | Error correction code circuit with reduced hardware complexity |
US7292365B2 (en) | 2003-01-15 | 2007-11-06 | Xerox Corporation | Methods and systems for determining distribution mean level without histogram measurement |
US7206992B2 (en) | 2003-03-04 | 2007-04-17 | Broadcom Corporation | Decoding a received BCH encoded signal |
JP4256198B2 (en) | 2003-04-22 | 2009-04-22 | 株式会社東芝 | Data storage system |
US7203874B2 (en) | 2003-05-08 | 2007-04-10 | Micron Technology, Inc. | Error detection, documentation, and correction in a flash memory device |
US6873543B2 (en) | 2003-05-30 | 2005-03-29 | Hewlett-Packard Development Company, L.P. | Memory device |
US7372731B2 (en) | 2003-06-17 | 2008-05-13 | Sandisk Il Ltd. | Flash memories with adaptive reference voltages |
US6914809B2 (en) | 2003-07-07 | 2005-07-05 | Hewlett-Packard Development Company, L.P. | Memory cell strings |
US7191379B2 (en) | 2003-09-10 | 2007-03-13 | Hewlett-Packard Development Company, L.P. | Magnetic memory with error correction coding |
US7149950B2 (en) | 2003-09-12 | 2006-12-12 | Hewlett-Packard Development Company, L.P. | Assisted memory device for reading and writing single and multiple units of data |
FR2860360B1 (en) | 2003-09-29 | 2005-12-09 | Canon Kk | ENCODING / DECODING DEVICE USING REED-SOLOMON ENCODER / DECODER |
US7079436B2 (en) | 2003-09-30 | 2006-07-18 | Hewlett-Packard Development Company, L.P. | Resistive cross point memory |
US7188228B1 (en) | 2003-10-01 | 2007-03-06 | Sandisk Corporation | Hybrid mapping implementation within a non-volatile memory system |
US7012835B2 (en) * | 2003-10-03 | 2006-03-14 | Sandisk Corporation | Flash memory data correction and scrub techniques |
US6990012B2 (en) | 2003-10-07 | 2006-01-24 | Hewlett-Packard Development Company, L.P. | Magnetic memory device |
US7177199B2 (en) | 2003-10-20 | 2007-02-13 | Sandisk Corporation | Behavior based programming of non-volatile memory |
US6996004B1 (en) | 2003-11-04 | 2006-02-07 | Advanced Micro Devices, Inc. | Minimization of FG-FG coupling in flash memory |
US20050120265A1 (en) | 2003-12-02 | 2005-06-02 | Pline Steven L. | Data storage system with error correction code and replaceable defective memory |
US7467177B2 (en) | 2003-12-29 | 2008-12-16 | Xilinx, Inc. | Mathematical circuit with dynamic rounding |
KR100526188B1 (en) | 2003-12-30 | 2005-11-04 | 삼성전자주식회사 | Method for address mapping and managing mapping information, and flash memory thereof |
KR100528482B1 (en) | 2003-12-31 | 2005-11-15 | 삼성전자주식회사 | Flash memory system capable of inputting/outputting sector dara at random |
KR100608592B1 (en) | 2004-01-27 | 2006-08-03 | 삼성전자주식회사 | Data managing device and method thereof |
US7068539B2 (en) | 2004-01-27 | 2006-06-27 | Sandisk Corporation | Charge packet metering for coarse/fine programming of non-volatile memory |
US7210077B2 (en) | 2004-01-29 | 2007-04-24 | Hewlett-Packard Development Company, L.P. | System and method for configuring a solid-state storage device with error correction coding |
JP4170952B2 (en) | 2004-01-30 | 2008-10-22 | 株式会社東芝 | Semiconductor memory device |
EP1711896B1 (en) | 2004-02-05 | 2015-11-18 | BlackBerry Limited | Memory controller interface |
US7254692B1 (en) * | 2004-03-02 | 2007-08-07 | Advanced Micro Devices, Inc. | Testing for operating life of a memory device with address cycling using a gray code sequence |
US20050213393A1 (en) | 2004-03-14 | 2005-09-29 | M-Systems Flash Disk Pioneers, Ltd. | States encoding in multi-bit flash cells for optimizing error rate |
US7325090B2 (en) * | 2004-04-29 | 2008-01-29 | Sandisk Il Ltd. | Refreshing data stored in a flash memory |
US20060294312A1 (en) | 2004-05-27 | 2006-12-28 | Silverbrook Research Pty Ltd | Generation sequences |
US6999854B2 (en) * | 2004-05-28 | 2006-02-14 | International Business Machines Corporation | Medical infusion pump capable of learning bolus time patterns and providing bolus alerts |
JP3967338B2 (en) | 2004-06-09 | 2007-08-29 | 株式会社日立国際電気 | Wireless packet transfer device |
WO2006013529A1 (en) | 2004-08-02 | 2006-02-09 | Koninklijke Philips Electronics N.V. | Data storage and replay apparatus |
EP1635261B1 (en) | 2004-09-10 | 2008-06-11 | STMicroelectronics S.r.l. | Memory with embedded error correction code circuit |
US20060059409A1 (en) | 2004-09-10 | 2006-03-16 | Hanho Lee | Reed-solomon decoder systems for high speed communication and data storage applications |
JP4406339B2 (en) | 2004-09-21 | 2010-01-27 | 株式会社東芝 | Controller, memory card and control method thereof |
US7038950B1 (en) | 2004-11-05 | 2006-05-02 | Spansion Llc | Multi bit program algorithm |
US7493457B2 (en) * | 2004-11-08 | 2009-02-17 | Sandisk Il. Ltd | States encoding in multi-bit flash cells for optimizing error rate |
US7441067B2 (en) | 2004-11-15 | 2008-10-21 | Sandisk Corporation | Cyclic flash memory wear leveling |
US7395404B2 (en) | 2004-12-16 | 2008-07-01 | Sandisk Corporation | Cluster auto-alignment for storing addressable data packets in a non-volatile memory array |
US7315916B2 (en) | 2004-12-16 | 2008-01-01 | Sandisk Corporation | Scratch pad block |
US7313023B2 (en) | 2005-03-11 | 2007-12-25 | Sandisk Corporation | Partition of non-volatile memory array to reduce bit line capacitance |
US7206230B2 (en) | 2005-04-01 | 2007-04-17 | Sandisk Corporation | Use of data latches in cache operations of non-volatile memories |
US7196928B2 (en) | 2005-04-05 | 2007-03-27 | Sandisk Corporation | Compensating for coupling during read operations of non-volatile memory |
US7196946B2 (en) | 2005-04-05 | 2007-03-27 | Sandisk Corporation | Compensating for coupling in non-volatile storage |
US8452929B2 (en) | 2005-04-21 | 2013-05-28 | Violin Memory Inc. | Method and system for storage of data in non-volatile media |
US20070098069A1 (en) | 2005-04-27 | 2007-05-03 | Stephen Gordon | Inverse scan, coefficient, inverse quantization and inverse transform system and method |
US7444579B2 (en) | 2005-04-28 | 2008-10-28 | Micron Technology, Inc. | Non-systematic coded error correction |
US7519582B2 (en) | 2005-06-13 | 2009-04-14 | International Business Machines Corporation | System and method for performing a high-level multi-dimensional query on a multi-structural database |
US7602009B2 (en) | 2005-06-16 | 2009-10-13 | Micron Technology, Inc. | Erasable non-volatile memory device using hole trapping in high-K dielectrics |
US7230854B2 (en) | 2005-08-01 | 2007-06-12 | Sandisk Corporation | Method for programming non-volatile memory with self-adjusting maximum program loop |
JP2007073779A (en) * | 2005-09-07 | 2007-03-22 | Elpida Memory Inc | Nonvolatile memory element and its manufacturing method |
KR100719697B1 (en) | 2005-10-10 | 2007-05-17 | 주식회사 하이닉스반도체 | Method for programming a flash memory device |
JP2007133683A (en) * | 2005-11-10 | 2007-05-31 | Sony Corp | Memory system |
US7844877B2 (en) | 2005-11-15 | 2010-11-30 | Ramot At Tel Aviv University Ltd. | Method and device for multi phase error-correction |
US20070143561A1 (en) | 2005-12-21 | 2007-06-21 | Gorobets Sergey A | Methods for adaptive file data handling in non-volatile memories with a directly mapped file storage system |
US8020060B2 (en) | 2006-01-18 | 2011-09-13 | Sandisk Il Ltd | Method of arranging data in a multi-level cell memory device |
US7793059B2 (en) | 2006-01-18 | 2010-09-07 | Apple Inc. | Interleaving policies for flash memory |
US7844879B2 (en) | 2006-01-20 | 2010-11-30 | Marvell World Trade Ltd. | Method and system for error correction in flash memory |
US8055979B2 (en) | 2006-01-20 | 2011-11-08 | Marvell World Trade Ltd. | Flash memory with coding and signal processing |
US7388781B2 (en) | 2006-03-06 | 2008-06-17 | Sandisk Il Ltd. | Multi-bit-per-cell flash memory device with non-bijective mapping |
US7962827B2 (en) | 2006-03-08 | 2011-06-14 | Marvell World Trade Ltd. | Systems and methods for achieving higher coding rate using parity interleaving |
US7810017B2 (en) | 2006-03-20 | 2010-10-05 | Micron Technology, Inc. | Variable sector-count ECC |
US7786526B2 (en) * | 2006-03-31 | 2010-08-31 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile semiconductor memory device |
US8050086B2 (en) | 2006-05-12 | 2011-11-01 | Anobit Technologies Ltd. | Distortion estimation and cancellation in memory devices |
WO2007132458A2 (en) | 2006-05-12 | 2007-11-22 | Anobit Technologies Ltd. | Memory device programming using combined shaping and linear spreading |
KR101202537B1 (en) | 2006-05-12 | 2012-11-19 | 애플 인크. | Combined distortion estimation and error correction coding for memory devices |
US7697326B2 (en) | 2006-05-12 | 2010-04-13 | Anobit Technologies Ltd. | Reducing programming error in memory devices |
US7639531B2 (en) | 2006-05-15 | 2009-12-29 | Apple Inc. | Dynamic cell bit resolution |
US7613043B2 (en) | 2006-05-15 | 2009-11-03 | Apple Inc. | Shifting reference values to account for voltage sag |
JP2007305267A (en) | 2006-05-15 | 2007-11-22 | Toshiba Corp | Semiconductor storage device |
US7809994B2 (en) | 2006-05-17 | 2010-10-05 | Sandisk Corporation | Error correction coding for multiple-sector pages in flash memory devices |
US7486561B2 (en) | 2006-06-22 | 2009-02-03 | Sandisk Corporation | Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages |
EP2038892A2 (en) | 2006-06-30 | 2009-03-25 | Nxp B.V. | Flash memory device having a flash cache portion and a method for using the same |
US7533328B2 (en) | 2006-07-04 | 2009-05-12 | Sandisk Il, Ltd. | Method of error correction in a multi-bit-per-cell flash memory |
US7443729B2 (en) | 2006-07-20 | 2008-10-28 | Sandisk Corporation | System that compensates for coupling based on sensing a neighbor using coupling |
US20080028014A1 (en) | 2006-07-26 | 2008-01-31 | Hilt Jason W | N-BIT 2's COMPLEMENT SYMMETRIC ROUNDING METHOD AND LOGIC FOR IMPLEMENTING THE SAME |
US7471565B2 (en) | 2006-08-22 | 2008-12-30 | Micron Technology, Inc. | Reducing effects of program disturb in a memory device |
KR100919156B1 (en) | 2006-08-24 | 2009-09-28 | 삼성전자주식회사 | Multi-bit flash memory device and program method thereof |
WO2008026203A2 (en) | 2006-08-27 | 2008-03-06 | Anobit Technologies | Estimation of non-linear distortion in memory devices |
US7450425B2 (en) | 2006-08-30 | 2008-11-11 | Micron Technology, Inc. | Non-volatile memory cell read failure reduction |
US7739576B2 (en) | 2006-08-31 | 2010-06-15 | Micron Technology, Inc. | Variable strength ECC |
KR100802059B1 (en) * | 2006-09-06 | 2008-02-12 | 삼성전자주식회사 | Memory system capable of suppressing generation of bad blocks due to read disturbance and operating method thereof |
JP2008077810A (en) | 2006-09-25 | 2008-04-03 | Toshiba Corp | Nonvolatile semiconductor storage device |
US7716538B2 (en) | 2006-09-27 | 2010-05-11 | Sandisk Corporation | Memory with cell population distribution assisted read margining |
US7904783B2 (en) | 2006-09-28 | 2011-03-08 | Sandisk Corporation | Soft-input soft-output decoder for nonvolatile memory |
US7818653B2 (en) * | 2006-09-28 | 2010-10-19 | Sandisk Corporation | Methods of soft-input soft-output decoding for nonvolatile memory |
US7805663B2 (en) | 2006-09-28 | 2010-09-28 | Sandisk Corporation | Methods of adapting operation of nonvolatile memory |
US7356442B1 (en) | 2006-10-05 | 2008-04-08 | International Business Machines Corporation | End of life prediction of flash memory |
US7805664B1 (en) | 2006-10-05 | 2010-09-28 | Marvell International Ltd | Likelihood metric generation for trellis-based detection and/or decoding |
US7961797B1 (en) | 2006-10-10 | 2011-06-14 | Marvell International Ltd. | Nonlinear viterbi complexity reduction |
KR100858241B1 (en) | 2006-10-25 | 2008-09-12 | 삼성전자주식회사 | Hybrid-flash memory device and method for assigning reserved blocks therof |
WO2008053472A2 (en) | 2006-10-30 | 2008-05-08 | Anobit Technologies Ltd. | Reading memory cells using multiple thresholds |
WO2008053473A2 (en) * | 2006-10-30 | 2008-05-08 | Anobit Technologies Ltd. | Memory cell readout using successive approximation |
KR100771521B1 (en) | 2006-10-30 | 2007-10-30 | 삼성전자주식회사 | Flash memory device having a multi-leveled cell and programming method thereof |
US7558109B2 (en) | 2006-11-03 | 2009-07-07 | Sandisk Corporation | Nonvolatile memory with variable read threshold |
US7440319B2 (en) | 2006-11-27 | 2008-10-21 | Sandisk Corporation | Apparatus with segmented bitscan for verification of programming |
US7924648B2 (en) * | 2006-11-28 | 2011-04-12 | Anobit Technologies Ltd. | Memory power and performance management |
US8190961B1 (en) | 2006-11-28 | 2012-05-29 | Marvell International Ltd. | System and method for using pilot signals in non-volatile memory devices |
JP2010511266A (en) * | 2006-11-29 | 2010-04-08 | ラムバス・インコーポレーテッド | Integrated circuit with built-in heating circuit to reverse operational degeneration |
KR100776139B1 (en) | 2006-11-30 | 2007-11-15 | 동부일렉트로닉스 주식회사 | Flash memory device |
US7706182B2 (en) | 2006-12-03 | 2010-04-27 | Anobit Technologies Ltd. | Adaptive programming of analog memory cells using statistical characteristics |
US8151163B2 (en) * | 2006-12-03 | 2012-04-03 | Anobit Technologies Ltd. | Automatic defect management in memory devices |
EP2115563A2 (en) | 2006-12-06 | 2009-11-11 | Fusion Multisystems, Inc. | Apparatus, system, and method for managing data in a storage device with an empty data token directive |
US8074011B2 (en) | 2006-12-06 | 2011-12-06 | Fusion-Io, Inc. | Apparatus, system, and method for storage space recovery after reaching a read count limit |
KR100766042B1 (en) | 2006-12-06 | 2007-10-12 | 삼성전자주식회사 | Multi-level cell memory device using concatenated coding |
KR100785925B1 (en) | 2006-12-06 | 2007-12-17 | 삼성전자주식회사 | Multi-level cell memory device using tcm |
US7593263B2 (en) | 2006-12-17 | 2009-09-22 | Anobit Technologies Ltd. | Memory device with reduced reading latency |
US7900102B2 (en) | 2006-12-17 | 2011-03-01 | Anobit Technologies Ltd. | High-speed programming of memory devices |
US8725975B2 (en) | 2007-01-03 | 2014-05-13 | Freescale Semiconductor, Inc. | Progressive memory initialization with waitpoints |
WO2008086237A2 (en) | 2007-01-05 | 2008-07-17 | California Institute Of Technology | Codes for limited magnitude asymmetric errors in flash memories |
KR100874441B1 (en) | 2007-01-09 | 2008-12-17 | 삼성전자주식회사 | Flash memory device capable of storing multi-bit data, memory controller controlling it, and memory system including the same |
US7751240B2 (en) | 2007-01-24 | 2010-07-06 | Anobit Technologies Ltd. | Memory device with negative thresholds |
US8151166B2 (en) | 2007-01-24 | 2012-04-03 | Anobit Technologies Ltd. | Reduction of back pattern dependency effects in memory devices |
US7900100B2 (en) | 2007-02-21 | 2011-03-01 | International Business Machines Corporation | Uncorrectable error detection utilizing complementary test patterns |
US7804718B2 (en) | 2007-03-07 | 2010-09-28 | Mosaid Technologies Incorporated | Partial block erase architecture for flash memory |
US8369141B2 (en) | 2007-03-12 | 2013-02-05 | Apple Inc. | Adaptive estimation of memory cell read thresholds |
KR100874920B1 (en) | 2007-03-15 | 2008-12-19 | 삼성전자주식회사 | Flash memory device with reduced coupling effect between cells and driving method thereof |
KR100891332B1 (en) | 2007-03-30 | 2009-03-31 | 삼성전자주식회사 | Bose-Chaudhuri-Hocquenghem error correction method and circuit for checking error using error correction encoder |
US8001320B2 (en) | 2007-04-22 | 2011-08-16 | Anobit Technologies Ltd. | Command interface for memory devices |
WO2008139441A2 (en) | 2007-05-12 | 2008-11-20 | Anobit Technologies Ltd. | Memory device with internal signal processing unit |
US8234545B2 (en) | 2007-05-12 | 2012-07-31 | Apple Inc. | Data storage with incremental redundancy |
US8073648B2 (en) | 2007-05-14 | 2011-12-06 | Sandisk Il Ltd. | Measuring threshold voltage distribution in memory using an aggregate characteristic |
KR20090011249A (en) | 2007-07-25 | 2009-02-02 | 삼성전자주식회사 | Non-volatile memory cell programming method |
US8259497B2 (en) | 2007-08-06 | 2012-09-04 | Apple Inc. | Programming schemes for multi-level analog memory cells |
WO2009095902A2 (en) | 2008-01-31 | 2009-08-06 | Densbits Technologies Ltd. | Systems and methods for handling immediate data errors in flash memory |
US8650352B2 (en) | 2007-09-20 | 2014-02-11 | Densbits Technologies Ltd. | Systems and methods for determining logical values of coupled flash memory cells |
US7773413B2 (en) | 2007-10-08 | 2010-08-10 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells in the presence of temperature variations |
US8068360B2 (en) | 2007-10-19 | 2011-11-29 | Anobit Technologies Ltd. | Reading analog memory cells using built-in multi-threshold commands |
US8427867B2 (en) | 2007-10-22 | 2013-04-23 | Densbits Technologies Ltd. | Systems and methods for averaging error rates in non-volatile devices and storage systems |
WO2009053963A2 (en) | 2007-10-22 | 2009-04-30 | Densbits Technologies Ltd. | Methods for adaptively programming flash memory devices and flash memory systems incorporating same |
US8694715B2 (en) | 2007-10-22 | 2014-04-08 | Densbits Technologies Ltd. | Methods for adaptively programming flash memory devices and flash memory systems incorporating same |
WO2009053961A2 (en) * | 2007-10-25 | 2009-04-30 | Densbits Technologies Ltd. | Systems and methods for multiple coding rates in flash devices |
US20090113275A1 (en) | 2007-10-29 | 2009-04-30 | Legend Silicon Corp. | Bch code with 256 information bytes and up to 8 bytes of parity check elements |
US8046542B2 (en) | 2007-11-21 | 2011-10-25 | Micron Technology, Inc. | Fault-tolerant non-volatile integrated circuit memory |
US8429492B2 (en) | 2007-11-30 | 2013-04-23 | Marvell World Trade Ltd. | Error correcting code predication system and method |
US8225181B2 (en) | 2007-11-30 | 2012-07-17 | Apple Inc. | Efficient re-read operations from memory devices |
US8453022B2 (en) | 2007-12-05 | 2013-05-28 | Densbits Technologies Ltd. | Apparatus and methods for generating row-specific reading thresholds in flash memory |
WO2009072103A2 (en) | 2007-12-05 | 2009-06-11 | Densbits Technologies Ltd. | Flash memory apparatus and methods using a plurality of decoding stages including optional use of concatenated bch codes and/or designation of 'first below' cells |
US8607128B2 (en) | 2007-12-05 | 2013-12-10 | Densbits Technologies Ltd. | Low power chien-search based BCH/RS decoding system for flash memory, mobile communications devices and other applications |
US8209588B2 (en) | 2007-12-12 | 2012-06-26 | Anobit Technologies Ltd. | Efficient interference cancellation in analog memory cell arrays |
US8359516B2 (en) | 2007-12-12 | 2013-01-22 | Densbits Technologies Ltd. | Systems and methods for error correction and decoding on multi-level physical media |
WO2009074979A2 (en) | 2007-12-12 | 2009-06-18 | Densbits Technologies Ltd. | Chien-search system employing a clock-gating scheme to save power for error correction decoder and other applications |
US8456905B2 (en) | 2007-12-16 | 2013-06-04 | Apple Inc. | Efficient data storage in multi-plane memory devices |
WO2009078006A2 (en) * | 2007-12-18 | 2009-06-25 | Densbits Technologies Ltd. | Apparatus for coding at a plurality of rates in multi-level flash memory systems, and methods useful in conjunction therewith |
US8085586B2 (en) | 2007-12-27 | 2011-12-27 | Anobit Technologies Ltd. | Wear level estimation in analog memory cells |
US8255758B2 (en) | 2008-01-21 | 2012-08-28 | Apple Inc. | Decoding of error correction code using partial bit inversion |
US8300823B2 (en) | 2008-01-28 | 2012-10-30 | Netapp, Inc. | Encryption and compression of data for storage |
US8417893B2 (en) | 2008-02-04 | 2013-04-09 | Apple Inc. | Memory mapping techniques |
US8156398B2 (en) | 2008-02-05 | 2012-04-10 | Anobit Technologies Ltd. | Parameter estimation based on error correction code parity check equations |
US7924587B2 (en) | 2008-02-21 | 2011-04-12 | Anobit Technologies Ltd. | Programming of analog memory cells using a single programming pulse per state transition |
US7864573B2 (en) | 2008-02-24 | 2011-01-04 | Anobit Technologies Ltd. | Programming analog memory cells for reduced variance after retention |
CN101251788A (en) | 2008-03-07 | 2008-08-27 | 威盛电子股份有限公司 | Storage unit management method and system |
US8230300B2 (en) | 2008-03-07 | 2012-07-24 | Apple Inc. | Efficient readout from analog memory cells using data compression |
US8059457B2 (en) | 2008-03-18 | 2011-11-15 | Anobit Technologies Ltd. | Memory device with multiple-accuracy read commands |
US8972472B2 (en) * | 2008-03-25 | 2015-03-03 | Densbits Technologies Ltd. | Apparatus and methods for hardware-efficient unbiased rounding |
US20090271564A1 (en) | 2008-04-25 | 2009-10-29 | Hitachi, Ltd. | Storage system |
US7957187B2 (en) | 2008-05-09 | 2011-06-07 | Sandisk Corporation | Dynamic and adaptive optimization of read compare levels based on memory cell threshold voltage distribution |
US8625785B2 (en) | 2008-05-15 | 2014-01-07 | Qualcomm Incorporated | Identity based symmetric cryptosystem using secure biometric model |
US8060719B2 (en) | 2008-05-28 | 2011-11-15 | Micron Technology, Inc. | Hybrid memory management |
US8154918B2 (en) | 2008-06-30 | 2012-04-10 | Sandisk Il Ltd. | Method for page- and block based scrambling in non-volatile memory |
US8904083B2 (en) | 2008-07-30 | 2014-12-02 | Infineon Technologies Ag | Method and apparatus for storing data in solid state memory |
KR101528167B1 (en) | 2008-08-01 | 2015-06-12 | 삼성전자주식회사 | Memory device and method of data decision of memory device |
US8332725B2 (en) | 2008-08-20 | 2012-12-11 | Densbits Technologies Ltd. | Reprogramming non volatile memory portions |
US8208304B2 (en) * | 2008-11-16 | 2012-06-26 | Anobit Technologies Ltd. | Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N |
US7839690B2 (en) | 2008-12-11 | 2010-11-23 | Sandisk Corporation | Adaptive erase and soft programming for memory |
US8248831B2 (en) * | 2008-12-31 | 2012-08-21 | Apple Inc. | Rejuvenation of analog memory cells |
US8040744B2 (en) | 2009-01-05 | 2011-10-18 | Sandisk Technologies Inc. | Spare block management of non-volatile memories |
KR20100082185A (en) | 2009-01-08 | 2010-07-16 | 삼성전자주식회사 | User device including flash memory, cache memory and controller |
US8036035B2 (en) | 2009-03-25 | 2011-10-11 | Micron Technology, Inc. | Erase cycle counter usage in a memory device |
US8819385B2 (en) | 2009-04-06 | 2014-08-26 | Densbits Technologies Ltd. | Device and method for managing a flash memory |
US8458574B2 (en) | 2009-04-06 | 2013-06-04 | Densbits Technologies Ltd. | Compact chien-search based decoding apparatus and method |
US10447474B2 (en) | 2009-04-20 | 2019-10-15 | Pure Storage, Inc. | Dispersed data storage system data decoding and decryption |
US8566510B2 (en) | 2009-05-12 | 2013-10-22 | Densbits Technologies Ltd. | Systems and method for flash memory management |
US8159881B2 (en) | 2009-06-03 | 2012-04-17 | Marvell World Trade Ltd. | Reference voltage optimization for flash memory |
TWI425512B (en) | 2009-06-16 | 2014-02-01 | Phison Electronics Corp | Flash memory controller circuit and storage system and data transfer method thereof |
US8868821B2 (en) | 2009-08-26 | 2014-10-21 | Densbits Technologies Ltd. | Systems and methods for pre-equalization and code design for a flash memory |
US8305812B2 (en) | 2009-08-26 | 2012-11-06 | Densbits Technologies Ltd. | Flash memory module and method for programming a page of flash memory cells |
US8730729B2 (en) * | 2009-10-15 | 2014-05-20 | Densbits Technologies Ltd. | Systems and methods for averaging error rates in non-volatile devices and storage systems |
KR101602939B1 (en) | 2009-10-16 | 2016-03-15 | 삼성전자주식회사 | Nonvolatile memory system and method for managing data thereof |
US8724387B2 (en) | 2009-10-22 | 2014-05-13 | Densbits Technologies Ltd. | Method, system, and computer readable medium for reading and programming flash memory cells using multiple bias voltages |
US8423866B2 (en) | 2009-10-28 | 2013-04-16 | SanDisk Technologies, Inc. | Non-volatile memory and method with post-write read and adaptive re-write to manage errors |
US8626988B2 (en) | 2009-11-19 | 2014-01-07 | Densbits Technologies Ltd. | System and method for uncoded bit error rate equalization via interleaving |
US8250324B2 (en) | 2009-11-30 | 2012-08-21 | International Business Machines Corporation | Method to efficiently locate meta-data structures on a flash-based storage device |
US9037777B2 (en) | 2009-12-22 | 2015-05-19 | Densbits Technologies Ltd. | Device, system, and method for reducing program/read disturb in flash arrays |
US8607124B2 (en) | 2009-12-24 | 2013-12-10 | Densbits Technologies Ltd. | System and method for setting a flash memory cell read threshold |
KR101662309B1 (en) | 2010-02-08 | 2016-10-04 | 삼성전자주식회사 | Method of programming memory cells for a non-volatile memory device |
US8589766B2 (en) | 2010-02-24 | 2013-11-19 | Apple Inc. | Codeword remapping schemes for non-volatile memories |
US8341502B2 (en) | 2010-02-28 | 2012-12-25 | Densbits Technologies Ltd. | System and method for multi-dimensional decoding |
US8516274B2 (en) | 2010-04-06 | 2013-08-20 | Densbits Technologies Ltd. | Method, system and medium for analog encryption in a flash memory |
US8527840B2 (en) | 2010-04-06 | 2013-09-03 | Densbits Technologies Ltd. | System and method for restoring damaged data programmed on a flash device |
US20110252187A1 (en) | 2010-04-07 | 2011-10-13 | Avigdor Segal | System and method for operating a non-volatile memory including a portion operating as a single-level cell memory and a portion operating as a multi-level cell memory |
US8745317B2 (en) | 2010-04-07 | 2014-06-03 | Densbits Technologies Ltd. | System and method for storing information in a multi-level cell memory |
US9021177B2 (en) | 2010-04-29 | 2015-04-28 | Densbits Technologies Ltd. | System and method for allocating and using spare blocks in a flash memory |
US8539311B2 (en) | 2010-07-01 | 2013-09-17 | Densbits Technologies Ltd. | System and method for data recovery in multi-level cell memories |
US8621321B2 (en) * | 2010-07-01 | 2013-12-31 | Densbits Technologies Ltd. | System and method for multi-dimensional encoding and decoding |
US20120008414A1 (en) | 2010-07-06 | 2012-01-12 | Michael Katz | Systems and methods for storing, retrieving, and adjusting read thresholds in flash memory storage system |
US8407560B2 (en) | 2010-07-14 | 2013-03-26 | Hewlett-Packard Development Company, L.P. | Systems and methods for encoding information for storage in an electronic memory and for decoding encoded information retrieved from an electronic memory |
US8964464B2 (en) * | 2010-08-24 | 2015-02-24 | Densbits Technologies Ltd. | System and method for accelerated sampling |
US8508995B2 (en) | 2010-09-15 | 2013-08-13 | Densbits Technologies Ltd. | System and method for adjusting read voltage thresholds in memories |
US9063878B2 (en) | 2010-11-03 | 2015-06-23 | Densbits Technologies Ltd. | Method, system and computer readable medium for copy back |
US8806106B2 (en) | 2010-11-12 | 2014-08-12 | Seagate Technology Llc | Estimating wear of non-volatile, solid state memory |
US8886990B2 (en) | 2011-01-27 | 2014-11-11 | Apple Inc. | Block management schemes in hybrid SLC/MLC memory |
-
2008
- 2008-09-17 US US12/596,450 patent/US8453022B2/en active Active
- 2008-09-17 US US12/596,438 patent/US8751726B2/en active Active
- 2008-09-17 US US12/596,446 patent/US8341335B2/en active Active
- 2008-09-17 US US12/667,042 patent/US8321625B2/en active Active
- 2008-09-17 WO PCT/IL2008/001232 patent/WO2009072102A2/en active Application Filing
- 2008-09-17 WO PCT/IL2008/001231 patent/WO2009072101A2/en active Application Filing
- 2008-09-17 WO PCT/IL2008/001230 patent/WO2009072100A2/en active Application Filing
- 2008-09-17 WO PCT/IL2008/001239 patent/WO2009072104A2/en active Application Filing
-
2012
- 2012-10-11 US US13/649,292 patent/US8843698B2/en active Active
- 2012-11-19 US US13/681,246 patent/US9104550B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070104004A1 (en) * | 1997-09-08 | 2007-05-10 | So Hock C | Multi-Bit-Per-Cell Flash EEprom Memory with Refresh |
US7177977B2 (en) * | 2004-03-19 | 2007-02-13 | Sandisk Corporation | Operating non-volatile memory without read disturb limitations |
US7290203B2 (en) * | 2004-10-29 | 2007-10-30 | International Business Machines Corporation | Dynamic memory architecture employing passive expiration of data |
US20070253249A1 (en) * | 2006-04-26 | 2007-11-01 | Sang-Gu Kang | Multi-bit nonvolatile memory device and related programming method |
Cited By (74)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8239735B2 (en) | 2006-05-12 | 2012-08-07 | Apple Inc. | Memory Device with adaptive capacity |
US8050086B2 (en) | 2006-05-12 | 2011-11-01 | Anobit Technologies Ltd. | Distortion estimation and cancellation in memory devices |
US8599611B2 (en) | 2006-05-12 | 2013-12-03 | Apple Inc. | Distortion estimation and cancellation in memory devices |
US8570804B2 (en) | 2006-05-12 | 2013-10-29 | Apple Inc. | Distortion estimation and cancellation in memory devices |
US8156403B2 (en) | 2006-05-12 | 2012-04-10 | Anobit Technologies Ltd. | Combined distortion estimation and error correction coding for memory devices |
US8060806B2 (en) | 2006-08-27 | 2011-11-15 | Anobit Technologies Ltd. | Estimation of non-linear distortion in memory devices |
USRE46346E1 (en) | 2006-10-30 | 2017-03-21 | Apple Inc. | Reading memory cells using multiple thresholds |
US8145984B2 (en) | 2006-10-30 | 2012-03-27 | Anobit Technologies Ltd. | Reading memory cells using multiple thresholds |
US7975192B2 (en) | 2006-10-30 | 2011-07-05 | Anobit Technologies Ltd. | Reading memory cells using multiple thresholds |
US7821826B2 (en) | 2006-10-30 | 2010-10-26 | Anobit Technologies, Ltd. | Memory cell readout using successive approximation |
US7924648B2 (en) | 2006-11-28 | 2011-04-12 | Anobit Technologies Ltd. | Memory power and performance management |
US8151163B2 (en) | 2006-12-03 | 2012-04-03 | Anobit Technologies Ltd. | Automatic defect management in memory devices |
US7900102B2 (en) | 2006-12-17 | 2011-03-01 | Anobit Technologies Ltd. | High-speed programming of memory devices |
US7881107B2 (en) | 2007-01-24 | 2011-02-01 | Anobit Technologies Ltd. | Memory device with negative thresholds |
US8151166B2 (en) | 2007-01-24 | 2012-04-03 | Anobit Technologies Ltd. | Reduction of back pattern dependency effects in memory devices |
US7751240B2 (en) | 2007-01-24 | 2010-07-06 | Anobit Technologies Ltd. | Memory device with negative thresholds |
US8369141B2 (en) | 2007-03-12 | 2013-02-05 | Apple Inc. | Adaptive estimation of memory cell read thresholds |
US8001320B2 (en) | 2007-04-22 | 2011-08-16 | Anobit Technologies Ltd. | Command interface for memory devices |
US8429493B2 (en) | 2007-05-12 | 2013-04-23 | Apple Inc. | Memory device with internal signap processing unit |
US8234545B2 (en) | 2007-05-12 | 2012-07-31 | Apple Inc. | Data storage with incremental redundancy |
US7925936B1 (en) | 2007-07-13 | 2011-04-12 | Anobit Technologies Ltd. | Memory device with non-uniform programming levels |
US8259497B2 (en) | 2007-08-06 | 2012-09-04 | Apple Inc. | Programming schemes for multi-level analog memory cells |
US8174905B2 (en) | 2007-09-19 | 2012-05-08 | Anobit Technologies Ltd. | Programming orders for reducing distortion in arrays of multi-level analog memory cells |
US7773413B2 (en) | 2007-10-08 | 2010-08-10 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells in the presence of temperature variations |
US8068360B2 (en) | 2007-10-19 | 2011-11-29 | Anobit Technologies Ltd. | Reading analog memory cells using built-in multi-threshold commands |
US8000141B1 (en) | 2007-10-19 | 2011-08-16 | Anobit Technologies Ltd. | Compensation for voltage drifts in analog memory cells |
US8527819B2 (en) | 2007-10-19 | 2013-09-03 | Apple Inc. | Data storage in analog memory cell arrays having erase failures |
US8270246B2 (en) | 2007-11-13 | 2012-09-18 | Apple Inc. | Optimized selection of memory chips in multi-chips memory devices |
US8225181B2 (en) | 2007-11-30 | 2012-07-17 | Apple Inc. | Efficient re-read operations from memory devices |
US8209588B2 (en) | 2007-12-12 | 2012-06-26 | Anobit Technologies Ltd. | Efficient interference cancellation in analog memory cell arrays |
US8085586B2 (en) | 2007-12-27 | 2011-12-27 | Anobit Technologies Ltd. | Wear level estimation in analog memory cells |
US8156398B2 (en) | 2008-02-05 | 2012-04-10 | Anobit Technologies Ltd. | Parameter estimation based on error correction code parity check equations |
US7924587B2 (en) | 2008-02-21 | 2011-04-12 | Anobit Technologies Ltd. | Programming of analog memory cells using a single programming pulse per state transition |
US7864573B2 (en) | 2008-02-24 | 2011-01-04 | Anobit Technologies Ltd. | Programming analog memory cells for reduced variance after retention |
US8230300B2 (en) | 2008-03-07 | 2012-07-24 | Apple Inc. | Efficient readout from analog memory cells using data compression |
US8400858B2 (en) | 2008-03-18 | 2013-03-19 | Apple Inc. | Memory device with reduced sense time readout |
US8059457B2 (en) | 2008-03-18 | 2011-11-15 | Anobit Technologies Ltd. | Memory device with multiple-accuracy read commands |
US7995388B1 (en) | 2008-08-05 | 2011-08-09 | Anobit Technologies Ltd. | Data storage using modified voltages |
US7924613B1 (en) | 2008-08-05 | 2011-04-12 | Anobit Technologies Ltd. | Data storage in analog memory cells with protection against programming interruption |
US8498151B1 (en) | 2008-08-05 | 2013-07-30 | Apple Inc. | Data storage in analog memory cells using modified pass voltages |
US8949684B1 (en) | 2008-09-02 | 2015-02-03 | Apple Inc. | Segmented data storage |
US8169825B1 (en) | 2008-09-02 | 2012-05-01 | Anobit Technologies Ltd. | Reliable data storage in analog memory cells subjected to long retention periods |
US8482978B1 (en) | 2008-09-14 | 2013-07-09 | Apple Inc. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
US8000135B1 (en) | 2008-09-14 | 2011-08-16 | Anobit Technologies Ltd. | Estimation of memory cell read thresholds by sampling inside programming level distribution intervals |
US8239734B1 (en) | 2008-10-15 | 2012-08-07 | Apple Inc. | Efficient data storage in storage device arrays |
US8713330B1 (en) | 2008-10-30 | 2014-04-29 | Apple Inc. | Data scrambling in memory devices |
US8261159B1 (en) | 2008-10-30 | 2012-09-04 | Apple, Inc. | Data scrambling schemes for memory devices |
US8208304B2 (en) | 2008-11-16 | 2012-06-26 | Anobit Technologies Ltd. | Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N |
US8248831B2 (en) | 2008-12-31 | 2012-08-21 | Apple Inc. | Rejuvenation of analog memory cells |
US8174857B1 (en) | 2008-12-31 | 2012-05-08 | Anobit Technologies Ltd. | Efficient readout schemes for analog memory cell devices using multiple read threshold sets |
US8397131B1 (en) | 2008-12-31 | 2013-03-12 | Apple Inc. | Efficient readout schemes for analog memory cell devices |
US8924661B1 (en) | 2009-01-18 | 2014-12-30 | Apple Inc. | Memory system including a controller and processors associated with memory devices |
US8228701B2 (en) | 2009-03-01 | 2012-07-24 | Apple Inc. | Selective activation of programming schemes in analog memory cell arrays |
US8832354B2 (en) | 2009-03-25 | 2014-09-09 | Apple Inc. | Use of host system resources by memory controller |
US8259506B1 (en) | 2009-03-25 | 2012-09-04 | Apple Inc. | Database of memory read thresholds |
US8238157B1 (en) | 2009-04-12 | 2012-08-07 | Apple Inc. | Selective re-programming of analog memory cells |
US8479080B1 (en) | 2009-07-12 | 2013-07-02 | Apple Inc. | Adaptive over-provisioning in memory systems |
US8495465B1 (en) | 2009-10-15 | 2013-07-23 | Apple Inc. | Error correction coding over multiple memory pages |
US8677054B1 (en) | 2009-12-16 | 2014-03-18 | Apple Inc. | Memory management schemes for non-volatile memory devices |
US8694814B1 (en) | 2010-01-10 | 2014-04-08 | Apple Inc. | Reuse of host hibernation storage space by memory controller |
US8677203B1 (en) | 2010-01-11 | 2014-03-18 | Apple Inc. | Redundant data storage schemes for multi-die memory systems |
US8572311B1 (en) | 2010-01-11 | 2013-10-29 | Apple Inc. | Redundant data storage in multi-die memory systems |
US8694853B1 (en) | 2010-05-04 | 2014-04-08 | Apple Inc. | Read commands for reading interfering memory cells |
US8572423B1 (en) | 2010-06-22 | 2013-10-29 | Apple Inc. | Reducing peak current in memory systems |
US8595591B1 (en) | 2010-07-11 | 2013-11-26 | Apple Inc. | Interference-aware assignment of programming levels in analog memory cells |
US9104580B1 (en) | 2010-07-27 | 2015-08-11 | Apple Inc. | Cache memory for hybrid disk drives |
US8645794B1 (en) | 2010-07-31 | 2014-02-04 | Apple Inc. | Data storage in analog memory cells using a non-integer number of bits per cell |
US8767459B1 (en) | 2010-07-31 | 2014-07-01 | Apple Inc. | Data storage in analog memory cells across word lines using a non-integer number of bits per cell |
US8856475B1 (en) | 2010-08-01 | 2014-10-07 | Apple Inc. | Efficient selection of memory blocks for compaction |
US8493781B1 (en) | 2010-08-12 | 2013-07-23 | Apple Inc. | Interference mitigation using individual word line erasure operations |
US8694854B1 (en) | 2010-08-17 | 2014-04-08 | Apple Inc. | Read threshold setting based on soft readout statistics |
US9021181B1 (en) | 2010-09-27 | 2015-04-28 | Apple Inc. | Memory management for unifying memory cell conditions by using maximum time intervals |
US11556416B2 (en) | 2021-05-05 | 2023-01-17 | Apple Inc. | Controlling memory readout reliability and throughput by adjusting distance between read thresholds |
US11847342B2 (en) | 2021-07-28 | 2023-12-19 | Apple Inc. | Efficient transfer of hard data and confidence levels in reading a nonvolatile memory |
Also Published As
Publication number | Publication date |
---|---|
US20130238839A1 (en) | 2013-09-12 |
WO2009072104A2 (en) | 2009-06-11 |
WO2009072100A3 (en) | 2010-03-04 |
WO2009072102A3 (en) | 2010-03-04 |
US20130080691A1 (en) | 2013-03-28 |
US9104550B2 (en) | 2015-08-11 |
US8843698B2 (en) | 2014-09-23 |
US20100064096A1 (en) | 2010-03-11 |
US8453022B2 (en) | 2013-05-28 |
WO2009072102A2 (en) | 2009-06-11 |
US8341335B2 (en) | 2012-12-25 |
US20100146191A1 (en) | 2010-06-10 |
US20100180073A1 (en) | 2010-07-15 |
WO2009072104A3 (en) | 2010-03-04 |
WO2009072104A8 (en) | 2009-09-03 |
US8321625B2 (en) | 2012-11-27 |
WO2009072101A3 (en) | 2010-03-04 |
WO2009072100A2 (en) | 2009-06-11 |
US20100131809A1 (en) | 2010-05-27 |
US8751726B2 (en) | 2014-06-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8453022B2 (en) | Apparatus and methods for generating row-specific reading thresholds in flash memory | |
US8694715B2 (en) | Methods for adaptively programming flash memory devices and flash memory systems incorporating same | |
US8762800B1 (en) | Systems and methods for handling immediate data errors in flash memory | |
US9257204B2 (en) | Read voltage setting method, and control circuit, and memory storage apparatus using the same | |
US9019770B2 (en) | Data reading method, and control circuit, memory module and memory storage apparatus and memory module using the same | |
US9703698B2 (en) | Data writing method, memory controller and memory storage apparatus | |
WO2009053963A2 (en) | Methods for adaptively programming flash memory devices and flash memory systems incorporating same | |
CN107731258B (en) | Memory system with read threshold estimation and method of operating the same | |
US9286986B2 (en) | Data writing method, and memory control circuit unit and memory storage apparatus using the same | |
CN106257594B (en) | Read disturb reclaim policy | |
US9563508B2 (en) | Memory management method, memory control circuit unit and memory storage apparatus | |
US8972653B2 (en) | Memory management method, and memory controller and memory storage apparatus using the same | |
US20140047160A1 (en) | Data writing method, and memory controller and memory storage apparatus using the same | |
CN112394880B (en) | Method and apparatus for access control with machine learning for quality of service optimization | |
US8830750B1 (en) | Data reading method, and control circuit, memory module and memory storage apparatus using the same | |
US10656847B2 (en) | Mitigating asymmetric transient errors in non-volatile memory by proactive data relocation | |
US20190391752A1 (en) | Block health estimation for wear leveling in non-volatile memories | |
US10832784B2 (en) | Pre-program read to counter wordline failures | |
US10790031B1 (en) | System handling for first read read disturb | |
CN110908825B (en) | Data reading method and device, storage equipment and storage medium | |
CN114724596A (en) | Read voltage setting method, memory storage device and memory controller |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 08808032 Country of ref document: EP Kind code of ref document: A2 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 12596450 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 08808032 Country of ref document: EP Kind code of ref document: A2 |