WO2009114392A3 - Semiconductor die package including embedded flip chip - Google Patents

Semiconductor die package including embedded flip chip Download PDF

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Publication number
WO2009114392A3
WO2009114392A3 PCT/US2009/036226 US2009036226W WO2009114392A3 WO 2009114392 A3 WO2009114392 A3 WO 2009114392A3 US 2009036226 W US2009036226 W US 2009036226W WO 2009114392 A3 WO2009114392 A3 WO 2009114392A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor die
die package
flip chip
package including
including embedded
Prior art date
Application number
PCT/US2009/036226
Other languages
French (fr)
Other versions
WO2009114392A2 (en
Inventor
Yong Liu
Jeff Ju
Zhongfa Yuan
Roger Luo
Original Assignee
Fairchild Semiconductor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Semiconductor Corporation filed Critical Fairchild Semiconductor Corporation
Priority to KR1020107021836A priority Critical patent/KR101483204B1/en
Priority to CN200980108883.5A priority patent/CN101971332B/en
Publication of WO2009114392A2 publication Critical patent/WO2009114392A2/en
Publication of WO2009114392A3 publication Critical patent/WO2009114392A3/en

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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L2924/0781Adhesive characteristics other than chemical being an ohmic electrical conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161Exposing the passive side of the semiconductor or solid-state body of a flip chip

Abstract

A semiconductor die package. The semiconductor die package includes a leadframe structure, a first semiconductor die comprising a first surface attached to a first side of the leadframe structure, and a second semiconductor die attached to a second side of the leadframe structure. The second semiconductor die comprises an integrated circuit die. A housing material is formed over at least a portion of the leadframe structure, the first semiconductor die, and the second semiconductor die. An exterior surface of the molding material is substantially coplanar with the first surface of the semiconductor die.
PCT/US2009/036226 2008-03-12 2009-03-05 Semiconductor die package including embedded flip chip WO2009114392A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020107021836A KR101483204B1 (en) 2008-03-12 2009-03-05 Semiconductor die package including embedded flip chip
CN200980108883.5A CN101971332B (en) 2008-03-12 2009-03-05 Semiconductor die package including embedded flip chip

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/047,028 US7768108B2 (en) 2008-03-12 2008-03-12 Semiconductor die package including embedded flip chip
US12/047,028 2008-03-12

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WO2009114392A2 WO2009114392A2 (en) 2009-09-17
WO2009114392A3 true WO2009114392A3 (en) 2009-11-26

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Country Link
US (1) US7768108B2 (en)
KR (1) KR101483204B1 (en)
CN (1) CN101971332B (en)
MY (1) MY149770A (en)
TW (1) TWI464851B (en)
WO (1) WO2009114392A2 (en)

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WO2009114392A2 (en) 2009-09-17
US20090230537A1 (en) 2009-09-17
KR20100130611A (en) 2010-12-13
TW200943517A (en) 2009-10-16
US7768108B2 (en) 2010-08-03
TWI464851B (en) 2014-12-11
MY149770A (en) 2013-10-14
CN101971332B (en) 2015-04-29
KR101483204B1 (en) 2015-01-15
CN101971332A (en) 2011-02-09

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