WO2009123808A2 - A solder bump bondig method, stencil. and system - Google Patents

A solder bump bondig method, stencil. and system Download PDF

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Publication number
WO2009123808A2
WO2009123808A2 PCT/US2009/035373 US2009035373W WO2009123808A2 WO 2009123808 A2 WO2009123808 A2 WO 2009123808A2 US 2009035373 W US2009035373 W US 2009035373W WO 2009123808 A2 WO2009123808 A2 WO 2009123808A2
Authority
WO
WIPO (PCT)
Prior art keywords
openings
substrate
solder balls
solder
photoresist
Prior art date
Application number
PCT/US2009/035373
Other languages
French (fr)
Other versions
WO2009123808A3 (en
Inventor
Charles Alan Huffman
Original Assignee
Research Triangle Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Research Triangle Institute filed Critical Research Triangle Institute
Publication of WO2009123808A2 publication Critical patent/WO2009123808A2/en
Publication of WO2009123808A3 publication Critical patent/WO2009123808A3/en

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3478—Applying solder preforms; Transferring prefabricated solder patterns
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • B23K1/0016—Brazing of electronic components
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/008—Soldering within a furnace
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/012—Soldering with the use of hot gas
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/20—Preliminary treatment of work or areas to be soldered, e.g. in respect of a galvanic coating
    • B23K1/203—Fluxing, i.e. applying flux onto surfaces
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K3/00—Tools, devices, or special appurtenances for soldering, e.g. brazing, or unsoldering, not specially adapted for particular methods
    • B23K3/06—Solder feeding devices; Solder melting pans
    • B23K3/0607—Solder feeding devices
    • B23K3/0623—Solder feeding devices for shaped solder piece feeding, e.g. preforms, bumps, balls, pellets, droplets
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    • H01L2924/01—Chemical elements
    • H01L2924/01051—Antimony [Sb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/041—Solder preforms in the shape of solder balls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3452—Solder masks

Definitions

  • This application is directed to structures and methods for bonding multiple chip wafers for advanced integrated circuit fabrication.
  • One method is through wafer bumping in which solder bumps are placed on the terminal metal pads of a first IC wafer prior to connecting the first IC wafer to a substrate (i.e. a printed circuit board, laminate substrate, or another IC).
  • a substrate i.e. a printed circuit board, laminate substrate, or another IC.
  • a metal stencil is provided over the IC wafer for depositing solder balls or paste onto electrical pads connected to the IC wafer which have been prepared with an under bump metallurgy (UBM) compatible with the solder.
  • UBM under bump metallurgy
  • the solder balls (or paste) are then subjected to a reflow process which melts the solder material and bonds it to the UBM on the electrical pads, so as to form individual solder bumps over each of the prepared electrical pads.
  • UBM under bump metallurgy
  • an electroplating-based bumping process is used to form solder bumps on an IC wafer.
  • This process involves an under bump metal (UBM) deposition, thick photoresist processing, electroplating of solder (possibly preceded by electroplating of a barrier metal such as nickel or copper), and a reflow process.
  • UBM under bump metal
  • the electroplated metal deposited in patterned regions is heated to melt the solder material into solder bumps available thereafter to connect the electrical pads on the substrate.
  • U.S. Patent Nos. 5,384,283, 6,939,790, and 6,908,842 the entire contents of which are incorporated herein by reference, describe typical photoresists, metallizations, and connecting steps used in this approach.
  • a method for forming solder bumps on a substrate having electrical pads formed thereon including forming a photoresist layer on the substrate, patterning the photoresist layer to form photoresist openings aligned with the electrical pads on the substrate, supplying a plurality of solder balls into the photoresist openings, and connecting electrically the electrical pads to the solder balls by heating the solder balls to form the solder bumps.
  • a stencil for solder ball bonding including a photoresist layer having a plurality of patterned openings aligned with electrical pads on the substrate.
  • the patterned openings are dimensioned to accommodate the solder balls in the patterned openings.
  • a system for forming solder bumps on a substrate having electrical pads formed thereon includes a photoresist unit configured to form a photoresist layer on the substrate and to pattern the photoresist layer to form openings aligned with the electrical pads on the substrate.
  • the openings are dimensioned to accommodate solder balls therein.
  • the system includes a solder ball distribution unit configured to supply the solder balls into the openings, and a heating unit configured to heat the solder balls to form the solder bumps on the substrate.
  • FIG. IA is a schematic depicting metal pads on an IC wafer
  • FIG. IB is a schematic showing the formation of a photoresist about the metal pads
  • FIG. 1C is a schematic depicting the disposition of solder balls in contact with the metal pads
  • FIG. ID is a schematic depicting a reflow process of reflowing the solder ball to the metal pads
  • FIG. IE is a schematic depicting the resist of a subsequent reflow current after removal of the photoresist
  • FIG. 2 A is a schematic depicting alignment of another IC wafer to the reflow solder balls
  • FIG. 2B is a schematic depicting the joining of the two IC wafers together by solder ball attachment
  • FIG. 3 A is a schematic of a photoresist stencil according to the present invention.
  • FIG. 3B is a schematic of a solder-ball disposed in the photoresist stencil of the present invention and bonded to metal pads;
  • FIG. 4 is a schematic of a bonding system according to one embodiment of the present invention.
  • FIG. 5 A is another schematic of a photoresist stencil according to the present invention.
  • FIG. 5B is a schematic of a photoresist stencil of FIG. 5 A being processed
  • FIG. 5C is a schematic of the photoresist stencil of FIG. 5 A being further processed
  • FIG. 5D is a schematic diagram of the photoresist stencil of FIG. 5C after a reflow process.
  • FIG. 6 is a flowchart of a method according to the present invention.
  • Wafer bumping methodologies are designed to form arrays of metal interconnections, or bumps (usually a solder alloy), used to connect one electronic device to another mechanically and electrically.
  • the means of depositing these bumps include electroplating, solder paste stenciling, solid state bump placement, and others.
  • the invention detailed within has a number of advantages to common solder bump formation processes.
  • Electroplating for example, is a time intensive process when large bump structures are being formed, due to the length of time required to deposit the required amount of metal to form the bump. Therefore, other processes are used more often when forming larger bump sizes (i.e. larger than 250 microns). These processes often require the alignment of a metal stencil to a wafer with pre-prepared metal pads. Solder paste or solid state solder balls are deposited through the holes in the stencil and then subjected to a reflow process to join them to the substrate. When solder paste is used for this process, careful control of the paste parameters is required in order to achieve successful results, and the stencil must be cleaned often in order for the process to remain consistent. Alternative processes utilizing dry film photoresists as solder paste stencils are known in the industry, but are still require careful control of the paste parameters.
  • Solid state solder balls When solid state solder balls are deposited through a metal stencil, a fluxing process must take place first in order to keep the solder balls in place before reflow.
  • Solid state solder balls may also be placed on the flux-prepared substrate surface by using a specialized system designed to place the balls one at a time according to a predescribed pattern. This process grows longer and more costly the greater the numbers of bumps are needed on the substrate.
  • the invention in its various embodiments described below avoids many of these issues and is also expected to be a lower cost process, requiring fewer process variables to be controlled and a shorter cycle time. This process does not require expensive, specialized equipment for the deposition of the solder balls on the surface and uses commercially available materials.
  • FIGS. IA - IE show one possible method of forming a multiplicity of solder bump contacts to I/O pads on a device integrated circuit (IC) wafer according to the present invention.
  • FIG. IA shows an IC wafer 100 which may be for example a device chip or in this embodiment, the IC wafer 100 has a substrate 110 and electrical pads 120.
  • the substrate 110 may be made of silicon or other device substrate materials such as GaAs, SiC, Ge, silicon-on-insulator, ceramics, glasses, sapphire, InP, or laminate substrate panels.
  • the electrical pads 120 may be made of a thin metal layer or stack of metal layers (e.g., a layer of Au formed on a layer of Ni). Methods of forming metal pads, such as Ni/Au or other metals, on a substrate that are compatible with solder metallurgies are known in the art and will not be described here in detail.
  • FIG. IB shows a layer 130 of dry film photoresist applied to the wafer 100 and patterned to form openings 135 aligned with the electrical pads 120.
  • the dry film photoresist 130 may be from the WB3000TM family of dry film photoresists from DuPont. In this family of photoresists, thick photoresist layers in discrete thicknesses can be applied by hot roll lamination, patterned using standard photolithography techniques, and developed with a carbonate solution to form the patterned photoresist layers of the present invention.
  • a characteristic of the WB3000 photoresist is that it can withstand the temperatures required for the reflow of most common solder alloys and still be removed by chemical means. In one example, the photoresist has a temperature rating of at least 200 0 C. Such a photoresist is compatible with common metallic contact materials including for example Cu, Al, Ag, Sn, Ni, Pb, and Au, and alloys thereof.
  • the openings 135 in the photoresist 130 in one embodiment are formed and patterned to have a diameter smaller than the diameter of electrical pads 120 such that the electrical pads 120 and the openings 135 form concentric circles. Other shapes that are not specifically circular and other major openings exposing the electrical pads 120 can be used.
  • the openings in the photoresist are formed and patterned to be larger than the electrical pads as shown in Fig. 5.
  • the openings in the photoresist are formed and patterned to be the same size as the electrical pads 120.
  • FIG. 1C shows solder balls 140 in the openings 135 of the IC wafer 100.
  • the solder balls are typically flux-coated, although the flux could be deposited on the electrical pads prior to placement of the solder balls.
  • the electrical pads can be prepared using no flux, and an alternate surface oxide reduction technique can be used either prior to or during the reflow of the solder balls to allow adequate wetting of the solder balls to the pads. This may include the use of oxide reducing atmospheres in the reflow process or the use of plasma-based or other pretreatments of the solder balls prior to loading in the openings.
  • the solder balls 140 are generally spherical in shape.
  • the solder balls 140 are made of an electroconductive metal alloy that has a melting point in one embodiment of under 300°C to be compatible with the photoresist mask. A higher temperature photoresist mask would permit solder balls of higher melting temperatures to be used.
  • solder balls consisting of alloys of Sn, Pb, Cu, Ag, Au, In, Bi, Cd, Zn, Sb and other alloying elements common to solder alloys are suitable.
  • the size of the solder balls 140 may vary, but the size is chosen so that the solder balls 140 fit in the photoresist openings 135 and do not fall out if the wafer is slightly tilted or agitated. Conversely, the size of the photoresist openings is formed and patterned to be commensurate with the solder ball diameter so that the solder balls do no fall out if the wafer is slightly tilted of agitated. Additionally, the thickness of the photoresist is selected to ensure that the solder balls do not fall out, which heavily depends on the method used to remove excess solder balls from the surface of the wafer. In one embodiment, the depth of the photoresist opening 135 is at least one third of the diameter of a solder ball. In another embodiment, the photoresist opening has a depth of at least one half of the diameter of a solder ball. In yet another embodiment, the photoresist opening has a depth of at least three-fourths of the diameter of a solder ball.
  • agitation is applied to the IC wafer 100 to cause the solder balls 140 to settle into the photoresist openings.
  • a table supporting the IC wafer is mounted to a vibrator that can agitate the wafer. The table is capable of tilting so that excess solder balls that do not settle into the openings are allowed to fall off the edge of the wafer.
  • a solder ball collector 480 shown in Fig. 4 and described later, is used to collect the excess solder balls 140 for later use.
  • the IC wafer 100 is inspected to determine if there was a complete distribution of the solder balls 140 in the photoresist openings 135.
  • One method of inspection involves optical inspection testing the wafer to determine if there is a solder ball in each opening. Optical inspecting can be done either by a human operator inspecting the wafer visually or by microscope. Automatic testing may be done by the use of automated optical inspection systems (AOI), which are commercially available and well known in the industry for inspecting solder ball arrays for defects.
  • IC wafer 100 and solder balls 140 are reflowed at a solder ball reflow temperature designed to melt the solder alloy.
  • An oven or other heating device can be used to achieve the reflow temperatures.
  • the alloy wets and reacts with the metal pad 120 to bond with the pad.
  • This reflow step may also include some alternative or additional means for reducing the surface oxides of the solder ball and/or pads besides flux, including specific pretreatments of the solder balls or reflow environments with gas mixtures for this purpose.
  • the IC wafer following this step is shown in Fig. ID with the melted solder alloy portions as 140'.
  • dry film photoresist 130 is chemically removed from the IC wafer 100, and the wafer 100 is then subject to a second reflowing as shown in FIG. IE.
  • the second reflowing is performed, if necessary, to form the solder bumps into uniform spheres 140" over the entire substrate 100 as shown in FIG. IE.
  • FIG. 2 A shows second IC wafer 200 with a substrate 210 and a set of electrical pads 220 which are metallurgically compatible with solder alloys.
  • the IC wafer 200 may be a device chip similar to IC wafer 100 as was described in FIG. IA.
  • the substrate 210 may be made of silicon or other suitable device substrates such as for example the substrates noted above.
  • FIG. 2B shows the substrate 210 disposed onto the solder balls 140" which are connected to the first substrate 110. A second reflowing of the solder balls 140" then connects the solder balls to the second set of electrical pads 220 on the second substrate 210. In this example, an electrical connection is formed between electrical pads 120 and 220.
  • the substrate 210 can also be disposed on the solder balls before they are bonded to the electrical pads 120. In this method, a single reflowing can be performed to bond the solder balls to the electrical pads 120 and 220 simultaneously.
  • the present invention provides a variety of processes which form a photoresist layer on a first substrate, pattern the photoresist layer to form openings over a first set of electrical pads on the first substrate, place solder balls in the openings, connect the solder balls to the first set of electrical pads, dispose a second substrate on the solder balls, and connect the solder balls (attached previously to the first substrate) to the second substrate.
  • a photoresist stencil is produced as an intermediary product.
  • FIG. 3 A is a schematic depiction of a photoresist stencil 300 of the present invention.
  • Stencil 300 includes a photoresist layer 330 having openings 335 aligned with electrical pads 320 on a substrate 310.
  • the dry film photoresist 330 can be from the WB3000TM family of dry film photoresists from DuPont as discussed above or other suitable photoresist whose properties permit the depths and diameter of openings to accommodate solder balls and whose properties permit photoresist exposure to temperatures compatible with the solder ball reflow process used.
  • the openings 335 in the photoresist 330 are shown having a dimension (e.g., diameter) smaller than a dimension (e.g., diameter) of electrical pads 320 such that the electrical pads 320 and the openings 335 form concentric circles as discussed above, however, other shapes for the openings can be used in the present invention.
  • FIG. 3B shows the stencil 300 of FIG. 3 A having solder balls 340 disposed in the openings 335 and bonded to electrical pads 320.
  • the stencil 300 of Fig. 3B may be formed according to the process described above and shown in FIGS. IA - 1C.
  • the solder balls may be comprised of, for example, either Sn, Pb, Cu, Ag, Au, In, Bi, Cd, Zn, Sb or other alloying elements common to solder alloys.
  • the depth of the pattern openings may vary to accommodate the solder balls. In one example, the depth of each opening is 1/3 the diameter of one of the solder balls. In another example, the depth of each opening is Vi the diameter of one of the solder balls. In yet another example, the depth is at least 3 A of the diameter of one of the solder balls. In still another example, the depth is at least the diameter of one of the solder balls. In a further example, the depth is greater than the diameter of one of the solder balls.
  • the diameter of the patterned openings may also vary in relation to the size of each electrical pad. In one example, the diameter 135 of the each opening is smaller than the diameter of one of the electrical pads as shown in FIG. IB, and the diameters of 120 and 135 may also be designed to be equal.
  • the diameter 135 of the each opening is greater than the diameter of one of the electrical pads, as shown in FIGs. 5 A and 5B.
  • FIG. 5C is a schematic of the photoresist stencil of FIG. 5B being processed (along the same process flow as discussed above with regard to FIG. 1C).
  • FIG. 5D is a schematic of a photoresist stencil of FIG. 5B being further processed (along the same process flow as discussed above with regard to FIG. ID).
  • FIG. 4 is a schematic of a bonding system according to one embodiment of the present invention.
  • FIG. 4 shows a system 400 having sub-systems 400a and 400b.
  • Sub-system 400a includes photoresist unit 410.
  • the photoresist processes carried out by sub-system 400a are generally carried out in a more highly controlled environment and may further include lamination system 420 to apply the photoresist, aligner/exposure tool 430 to perform the patterned exposure of the photoresist, and developing system 440.
  • Photoresist unit 410 is configured to form a photoresist layer on the first substrate, and pattern the photoresist layer to form openings aligned with the first set of electrical pads on the first substrate.
  • Photoresist unit 410 preferably includes at least 3 separate systems: a resist lamination system, an alignment/exposure system, and a development system. Ovens that can be used to thermally treat batches of wafers are also needed.
  • Sub-system 400b includes the "back-end” process and in the embodiment shown in Fig. 4 includes wafer handler 450, solder ball distribution unit 460, agitator 470, solder ball collector 480, inspection tool 490, and heating unit 495.
  • Wafer handler 450 is configured to place the second substrate on the first substrate at a predetermined position. Wafer handler 450 performs alignment of the second substrate with the first substrate. Wafer handler 450 is preferably one that accommodates a cassette of wafers and then feeds them into the process at proscribed intervals. These systems are well known, have many different embodiments for removing and replacing wafers in a cassette, and are available commercially from several different vendors.
  • Wafer handler 450 is also configured to align the second substrate properly with the first substrate. While usually performed in a separate step later on and performed with individual chips bonded together or chips bonded to a wafer or other substrate rather than wafer-to-wafer, wafer-to-wafer alignment is possible.
  • Solder ball distribution unit 460 is configured to supply solder balls into the openings in the photoresist layer.
  • Solder ball distribution unit may be realized as a simple hopper that pours a quantity of solder balls over the wafer, and the quantity need not be controlled with any precision.
  • Solder ball distribution unit 460 may also include a table or chuck which allows the solder balls to be poured out over the surface of the wafer, followed by an agitation to distribute the balls into the photoresist openings. Next, the table is tilted, and possibly still agitated, to remove excess solder balls from the surface. Finally, a wafer inspection may be carried out by either human or automated means to ensure there are no empty photoresist openings on the substrate.
  • Agitator 470 is configured to agitate the solder balls so as to distribute the plurality of solder balls into the openings.
  • Agitator 470 may be a simple shaker table. Additionally, Agitator 470 may include a customized wafer holder or chuck.
  • Solder ball collector 480 is configured to collect excess solder balls that are not distributed to the openings.
  • Solder ball 480 may be a tray located proximally to the first substrate.
  • Solder ball collector 480 may be a simple bin which funnels the excess balls from the shaker table. This collection bin may or may not have a mechanism to transfer the unused balls back to the ball dispenser unit.
  • Inspection tool 490 is configured to inspect the first substrate following the placing of the plurality of solder balls in the openings to determine a distribution of the solder balls in the openings. Inspection tool 490 may use optical detection to determine the distribution of the solder balls. Inspection tool 490 may be a microscope or it may include the use of automated optical inspection systems (AOI), which are commercially available and well known in the industry for inspecting solder ball arrays for defects.
  • AOI automated optical inspection systems
  • Heating unit 495 is configured to heat the first substrate to mechanically and metallurgically join the balls onto the prepared electrical pads on the wafer.
  • This system would be a belt furnace or similar system that has multiple heating zones that can be set at different temperatures to create a heating profile that is determined by the materials in the substrate and the solder alloy.
  • FIG. 6 shows a process 600 showing the general steps for forming the solder bumps on a substrate.
  • a photoresist layer is formed on a substrate.
  • the photoresist layer is patterned to form photoresist openings aligned with the set of electrical pads on the substrate.
  • a plurality of solder balls into the photoresist openings.
  • the electrical pads are electrically connected to the solder balls by reflowing the solder balls, thus forming the solder bumps.
  • the photoresist layer can be formed on a device chip.
  • the layer is patterned such that the electrical pads of the device chip are exposed permitting the solder balls to make contact upon being supplied to the openings.
  • the photoresist layer can either be returned or removed in the solder-connected product.
  • the photoresist layer can be removed after heating the solder balls to connect the solder balls to the electrical pads.
  • a solvent for the photoresist material can be used to dissolve the photoresist, and the solder-connected product is then dried of the solvent.
  • the photoresist is a high temperature photoresist which can have a temperature rating of at least 200 0 C.
  • the above-noted WB3000TM family of photoresist can be used, but the invention is not limited to just this type of photoresist. Photoresists of similar properties are usable in the invention, and the invention is not limited to only the WB3000TM family of photoresist.
  • the photoresist openings are patterned and formed to have a depth that can vary from at least one-third of the solder ball diameter, to greater than the diameter of the solder ball to be used.
  • the present invention is not particularly limited to any of these sizes. Rather, these sizes are chosen for the convenience of solder ball retention in the photoresist openings to facilitate the placement and holding of the solder balls in the openings.
  • the photoresist openings have a diameter either smaller than, equal to, or greater than a diameter of one of the electrical pads. Smaller diameter openings or greater diameter openings can be used. For example, it may be desirable to form a metal pad with diameter X then form photoresist openings of diameter Y where Y>X. There are two factors that determine the size of a solder bump formed on a substrate: the diameter of the pad the ball is joined to and the volume of the solder in the ball. Bumps with larger heights can be formed on a given pad by using a larger solder ball, which would require a larger diameter opening in the photoresist.
  • solder balls and consequently smaller photoresist openings, might be used if the final bump size was to be smaller.
  • the size of the photoresist opening used is a function of the size of the solder balls being deposited (which is determined by the final desired bump height) and the size of the pad the balls are joined to (which is typically a design factor determined by the pitch of the interconnects and mechanical strength considerations).
  • the solder balls can be distributed by agitating the solder balls to distribute the solder balls into the photoresist openings. Additionally, the substrate can be tilted during this or other stages of the ball distribution to permit not only dispersion of the balls but also the collection of excess solder balls not disposed in the photoresist openings, which may be collected in a tray proximate the substrate.

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

A method, stencil, and system for forming solder bumps on a substrate having electrical pads formed thereon. The method and system form a photoresist layer on the substrate, pattern the photoresist layer to form photoresist openings aligned with the electrical pads on the first substrate, supply solder balls into the photoresist openings, and connect electrically the electrical pads by heating the solder balls to form the solder bumps. The stencil includes a photoresist layer having a plurality of patterned openings aligned with the electrical pads on the substrate. The openings are dimensioned to accommodate the solder balls.

Description

TITLE OF THE INVENTION
A SOLDER BUMP BONDING METHOD, STENCIL, AND SYSTEM
BACKGROUND OF THE INVENTION Field of the Invention
This application is directed to structures and methods for bonding multiple chip wafers for advanced integrated circuit fabrication.
Description of the Related Art hi the microchip industry there is a need to provide a method to electrically interconnect integrated circuits (IC) to each other. One method is through wafer bumping in which solder bumps are placed on the terminal metal pads of a first IC wafer prior to connecting the first IC wafer to a substrate (i.e. a printed circuit board, laminate substrate, or another IC). When individual chips from the first IC wafer are assembled to the substrate, the solder bumps on the first IC wafer are heated and melted to bond to mating terminal metal pads on the substrate, thus forming an electrical interconnection between them. hi a conventional method for providing solder bumps on an IC wafer, a metal stencil is provided over the IC wafer for depositing solder balls or paste onto electrical pads connected to the IC wafer which have been prepared with an under bump metallurgy (UBM) compatible with the solder. The solder balls (or paste) are then subjected to a reflow process which melts the solder material and bonds it to the UBM on the electrical pads, so as to form individual solder bumps over each of the prepared electrical pads. One problem with this wafer-bumping method is that there is a need to align the metal stencil to each IC wafer prior to the deposition of the solder balls or paste. Also the metal stencil is reused and therefore it must be cleaned frequently to maintain consistent performance. In another conventional method, an electroplating-based bumping process is used to form solder bumps on an IC wafer. This process involves an under bump metal (UBM) deposition, thick photoresist processing, electroplating of solder (possibly preceded by electroplating of a barrier metal such as nickel or copper), and a reflow process. In this process, the electroplated metal deposited in patterned regions is heated to melt the solder material into solder bumps available thereafter to connect the electrical pads on the substrate. This method is not a low-cost process because of the complexities of the steps involved. U.S. Patent Nos. 5,384,283, 6,939,790, and 6,908,842, the entire contents of which are incorporated herein by reference, describe typical photoresists, metallizations, and connecting steps used in this approach.
SUMMARY OF THE INVENTION
In one embodiment of the present invention, there is provided a method for forming solder bumps on a substrate having electrical pads formed thereon, including forming a photoresist layer on the substrate, patterning the photoresist layer to form photoresist openings aligned with the electrical pads on the substrate, supplying a plurality of solder balls into the photoresist openings, and connecting electrically the electrical pads to the solder balls by heating the solder balls to form the solder bumps.
In another embodiment of the present invention, there is provided a stencil for solder ball bonding, including a photoresist layer having a plurality of patterned openings aligned with electrical pads on the substrate. The patterned openings are dimensioned to accommodate the solder balls in the patterned openings. In another embodiment of the present invention, there is provided a system for forming solder bumps on a substrate having electrical pads formed thereon. The system includes a photoresist unit configured to form a photoresist layer on the substrate and to pattern the photoresist layer to form openings aligned with the electrical pads on the substrate. The openings are dimensioned to accommodate solder balls therein. The system includes a solder ball distribution unit configured to supply the solder balls into the openings, and a heating unit configured to heat the solder balls to form the solder bumps on the substrate.
It is to be understood that both the foregoing general description of the invention and the following detailed description are exemplary, but are not restrictive of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
FIG. IA is a schematic depicting metal pads on an IC wafer;
FIG. IB is a schematic showing the formation of a photoresist about the metal pads;
FIG. 1C is a schematic depicting the disposition of solder balls in contact with the metal pads;
FIG. ID is a schematic depicting a reflow process of reflowing the solder ball to the metal pads; FIG. IE is a schematic depicting the resist of a subsequent reflow current after removal of the photoresist;
FIG. 2 A is a schematic depicting alignment of another IC wafer to the reflow solder balls;
FIG. 2B is a schematic depicting the joining of the two IC wafers together by solder ball attachment;
FIG. 3 A is a schematic of a photoresist stencil according to the present invention;
FIG. 3B is a schematic of a solder-ball disposed in the photoresist stencil of the present invention and bonded to metal pads;
FIG. 4 is a schematic of a bonding system according to one embodiment of the present invention;
FIG. 5 A is another schematic of a photoresist stencil according to the present invention;
FIG. 5B is a schematic of a photoresist stencil of FIG. 5 A being processed;
FIG. 5C is a schematic of the photoresist stencil of FIG. 5 A being further processed;
FIG. 5D is a schematic diagram of the photoresist stencil of FIG. 5C after a reflow process; and
FIG. 6 is a flowchart of a method according to the present invention.
DETAILED DESCRIPTION OF THE INVENTION
Wafer bumping methodologies are designed to form arrays of metal interconnections, or bumps (usually a solder alloy), used to connect one electronic device to another mechanically and electrically. The means of depositing these bumps include electroplating, solder paste stenciling, solid state bump placement, and others. The invention detailed within has a number of advantages to common solder bump formation processes.
Electroplating, for example, is a time intensive process when large bump structures are being formed, due to the length of time required to deposit the required amount of metal to form the bump. Therefore, other processes are used more often when forming larger bump sizes (i.e. larger than 250 microns). These processes often require the alignment of a metal stencil to a wafer with pre-prepared metal pads. Solder paste or solid state solder balls are deposited through the holes in the stencil and then subjected to a reflow process to join them to the substrate. When solder paste is used for this process, careful control of the paste parameters is required in order to achieve successful results, and the stencil must be cleaned often in order for the process to remain consistent. Alternative processes utilizing dry film photoresists as solder paste stencils are known in the industry, but are still require careful control of the paste parameters.
When solid state solder balls are deposited through a metal stencil, a fluxing process must take place first in order to keep the solder balls in place before reflow. Solid state solder balls may also be placed on the flux-prepared substrate surface by using a specialized system designed to place the balls one at a time according to a predescribed pattern. This process grows longer and more costly the greater the numbers of bumps are needed on the substrate. The invention in its various embodiments described below avoids many of these issues and is also expected to be a lower cost process, requiring fewer process variables to be controlled and a shorter cycle time. This process does not require expensive, specialized equipment for the deposition of the solder balls on the surface and uses commercially available materials.
Referring now to the drawings, wherein like reference numerals designate like or corresponding parts throughout the several views, and more particularly to Figs. 1 A-IE, FIGS. IA - IE show one possible method of forming a multiplicity of solder bump contacts to I/O pads on a device integrated circuit (IC) wafer according to the present invention.
FIG. IA shows an IC wafer 100 which may be for example a device chip or in this embodiment, the IC wafer 100 has a substrate 110 and electrical pads 120. The substrate 110 may be made of silicon or other device substrate materials such as GaAs, SiC, Ge, silicon-on-insulator, ceramics, glasses, sapphire, InP, or laminate substrate panels. The electrical pads 120 may be made of a thin metal layer or stack of metal layers (e.g., a layer of Au formed on a layer of Ni). Methods of forming metal pads, such as Ni/Au or other metals, on a substrate that are compatible with solder metallurgies are known in the art and will not be described here in detail.
FIG. IB shows a layer 130 of dry film photoresist applied to the wafer 100 and patterned to form openings 135 aligned with the electrical pads 120. The dry film photoresist 130 may be from the WB3000™ family of dry film photoresists from DuPont. In this family of photoresists, thick photoresist layers in discrete thicknesses can be applied by hot roll lamination, patterned using standard photolithography techniques, and developed with a carbonate solution to form the patterned photoresist layers of the present invention. A characteristic of the WB3000 photoresist is that it can withstand the temperatures required for the reflow of most common solder alloys and still be removed by chemical means. In one example, the photoresist has a temperature rating of at least 2000C. Such a photoresist is compatible with common metallic contact materials including for example Cu, Al, Ag, Sn, Ni, Pb, and Au, and alloys thereof.
The openings 135 in the photoresist 130 in one embodiment are formed and patterned to have a diameter smaller than the diameter of electrical pads 120 such that the electrical pads 120 and the openings 135 form concentric circles. Other shapes that are not specifically circular and other major openings exposing the electrical pads 120 can be used. In another embodiment, the openings in the photoresist are formed and patterned to be larger than the electrical pads as shown in Fig. 5. hi yet another embodiment, the openings in the photoresist are formed and patterned to be the same size as the electrical pads 120.
FIG. 1C shows solder balls 140 in the openings 135 of the IC wafer 100. The solder balls are typically flux-coated, although the flux could be deposited on the electrical pads prior to placement of the solder balls. Alternatively, the electrical pads can be prepared using no flux, and an alternate surface oxide reduction technique can be used either prior to or during the reflow of the solder balls to allow adequate wetting of the solder balls to the pads. This may include the use of oxide reducing atmospheres in the reflow process or the use of plasma-based or other pretreatments of the solder balls prior to loading in the openings. The solder balls 140 are generally spherical in shape. The solder balls 140 are made of an electroconductive metal alloy that has a melting point in one embodiment of under 300°C to be compatible with the photoresist mask. A higher temperature photoresist mask would permit solder balls of higher melting temperatures to be used. For the WB3000™ photoresist, solder balls consisting of alloys of Sn, Pb, Cu, Ag, Au, In, Bi, Cd, Zn, Sb and other alloying elements common to solder alloys are suitable.
The size of the solder balls 140 may vary, but the size is chosen so that the solder balls 140 fit in the photoresist openings 135 and do not fall out if the wafer is slightly tilted or agitated. Conversely, the size of the photoresist openings is formed and patterned to be commensurate with the solder ball diameter so that the solder balls do no fall out if the wafer is slightly tilted of agitated. Additionally, the thickness of the photoresist is selected to ensure that the solder balls do not fall out, which heavily depends on the method used to remove excess solder balls from the surface of the wafer. In one embodiment, the depth of the photoresist opening 135 is at least one third of the diameter of a solder ball. In another embodiment, the photoresist opening has a depth of at least one half of the diameter of a solder ball. In yet another embodiment, the photoresist opening has a depth of at least three-fourths of the diameter of a solder ball.
In one embodiment, agitation is applied to the IC wafer 100 to cause the solder balls 140 to settle into the photoresist openings. A table supporting the IC wafer is mounted to a vibrator that can agitate the wafer. The table is capable of tilting so that excess solder balls that do not settle into the openings are allowed to fall off the edge of the wafer. A solder ball collector 480, shown in Fig. 4 and described later, is used to collect the excess solder balls 140 for later use. hi one embodiment, the IC wafer 100 is inspected to determine if there was a complete distribution of the solder balls 140 in the photoresist openings 135. One method of inspection involves optical inspection testing the wafer to determine if there is a solder ball in each opening. Optical inspecting can be done either by a human operator inspecting the wafer visually or by microscope. Automatic testing may be done by the use of automated optical inspection systems (AOI), which are commercially available and well known in the industry for inspecting solder ball arrays for defects.
Next, IC wafer 100 and solder balls 140 are reflowed at a solder ball reflow temperature designed to melt the solder alloy. An oven or other heating device can be used to achieve the reflow temperatures. As the solder alloy melts, the alloy wets and reacts with the metal pad 120 to bond with the pad. This reflow step may also include some alternative or additional means for reducing the surface oxides of the solder ball and/or pads besides flux, including specific pretreatments of the solder balls or reflow environments with gas mixtures for this purpose. The IC wafer following this step is shown in Fig. ID with the melted solder alloy portions as 140'.
To complete this part of the process, dry film photoresist 130 is chemically removed from the IC wafer 100, and the wafer 100 is then subject to a second reflowing as shown in FIG. IE. The second reflowing is performed, if necessary, to form the solder bumps into uniform spheres 140" over the entire substrate 100 as shown in FIG. IE.
Next, the first IC wafer 100 is electrically connected to a second IC wafer. FIG. 2 A shows second IC wafer 200 with a substrate 210 and a set of electrical pads 220 which are metallurgically compatible with solder alloys. The IC wafer 200 may be a device chip similar to IC wafer 100 as was described in FIG. IA. The substrate 210 may be made of silicon or other suitable device substrates such as for example the substrates noted above.
FIG. 2B shows the substrate 210 disposed onto the solder balls 140" which are connected to the first substrate 110. A second reflowing of the solder balls 140" then connects the solder balls to the second set of electrical pads 220 on the second substrate 210. In this example, an electrical connection is formed between electrical pads 120 and 220.
The substrate 210 can also be disposed on the solder balls before they are bonded to the electrical pads 120. In this method, a single reflowing can be performed to bond the solder balls to the electrical pads 120 and 220 simultaneously.
Thus, the present invention provides a variety of processes which form a photoresist layer on a first substrate, pattern the photoresist layer to form openings over a first set of electrical pads on the first substrate, place solder balls in the openings, connect the solder balls to the first set of electrical pads, dispose a second substrate on the solder balls, and connect the solder balls (attached previously to the first substrate) to the second substrate. During this process, a photoresist stencil is produced as an intermediary product.
FIG. 3 A is a schematic depiction of a photoresist stencil 300 of the present invention. Stencil 300 includes a photoresist layer 330 having openings 335 aligned with electrical pads 320 on a substrate 310. The dry film photoresist 330 can be from the WB3000™ family of dry film photoresists from DuPont as discussed above or other suitable photoresist whose properties permit the depths and diameter of openings to accommodate solder balls and whose properties permit photoresist exposure to temperatures compatible with the solder ball reflow process used. The openings 335 in the photoresist 330 are shown having a dimension (e.g., diameter) smaller than a dimension (e.g., diameter) of electrical pads 320 such that the electrical pads 320 and the openings 335 form concentric circles as discussed above, however, other shapes for the openings can be used in the present invention.
FIG. 3B shows the stencil 300 of FIG. 3 A having solder balls 340 disposed in the openings 335 and bonded to electrical pads 320. The stencil 300 of Fig. 3B may be formed according to the process described above and shown in FIGS. IA - 1C. The solder balls may be comprised of, for example, either Sn, Pb, Cu, Ag, Au, In, Bi, Cd, Zn, Sb or other alloying elements common to solder alloys.
The depth of the pattern openings may vary to accommodate the solder balls. In one example, the depth of each opening is 1/3 the diameter of one of the solder balls. In another example, the depth of each opening is Vi the diameter of one of the solder balls. In yet another example, the depth is at least 3A of the diameter of one of the solder balls. In still another example, the depth is at least the diameter of one of the solder balls. In a further example, the depth is greater than the diameter of one of the solder balls. The diameter of the patterned openings may also vary in relation to the size of each electrical pad. In one example, the diameter 135 of the each opening is smaller than the diameter of one of the electrical pads as shown in FIG. IB, and the diameters of 120 and 135 may also be designed to be equal. In another example, the diameter 135 of the each opening is greater than the diameter of one of the electrical pads, as shown in FIGs. 5 A and 5B. FIG. 5C is a schematic of the photoresist stencil of FIG. 5B being processed (along the same process flow as discussed above with regard to FIG. 1C). FIG. 5D is a schematic of a photoresist stencil of FIG. 5B being further processed (along the same process flow as discussed above with regard to FIG. ID).
The process and device structures described above can be implemented by way of the system shown in FIG. 4. FIG. 4 is a schematic of a bonding system according to one embodiment of the present invention.
FIG. 4 shows a system 400 having sub-systems 400a and 400b. Sub-system 400a includes photoresist unit 410. The photoresist processes carried out by sub-system 400a are generally carried out in a more highly controlled environment and may further include lamination system 420 to apply the photoresist, aligner/exposure tool 430 to perform the patterned exposure of the photoresist, and developing system 440.
Photoresist unit 410 is configured to form a photoresist layer on the first substrate, and pattern the photoresist layer to form openings aligned with the first set of electrical pads on the first substrate. Photoresist unit 410 preferably includes at least 3 separate systems: a resist lamination system, an alignment/exposure system, and a development system. Ovens that can be used to thermally treat batches of wafers are also needed.
Sub-system 400b includes the "back-end" process and in the embodiment shown in Fig. 4 includes wafer handler 450, solder ball distribution unit 460, agitator 470, solder ball collector 480, inspection tool 490, and heating unit 495. Wafer handler 450 is configured to place the second substrate on the first substrate at a predetermined position. Wafer handler 450 performs alignment of the second substrate with the first substrate. Wafer handler 450 is preferably one that accommodates a cassette of wafers and then feeds them into the process at proscribed intervals. These systems are well known, have many different embodiments for removing and replacing wafers in a cassette, and are available commercially from several different vendors.
Wafer handler 450 is also configured to align the second substrate properly with the first substrate. While usually performed in a separate step later on and performed with individual chips bonded together or chips bonded to a wafer or other substrate rather than wafer-to-wafer, wafer-to-wafer alignment is possible.
Solder ball distribution unit 460 is configured to supply solder balls into the openings in the photoresist layer. Solder ball distribution unit may be realized as a simple hopper that pours a quantity of solder balls over the wafer, and the quantity need not be controlled with any precision. Solder ball distribution unit 460 may also include a table or chuck which allows the solder balls to be poured out over the surface of the wafer, followed by an agitation to distribute the balls into the photoresist openings. Next, the table is tilted, and possibly still agitated, to remove excess solder balls from the surface. Finally, a wafer inspection may be carried out by either human or automated means to ensure there are no empty photoresist openings on the substrate.
Agitator 470 is configured to agitate the solder balls so as to distribute the plurality of solder balls into the openings. Agitator 470 may be a simple shaker table. Additionally, Agitator 470 may include a customized wafer holder or chuck.
Solder ball collector 480 is configured to collect excess solder balls that are not distributed to the openings. Solder ball 480 may be a tray located proximally to the first substrate. Solder ball collector 480 may be a simple bin which funnels the excess balls from the shaker table. This collection bin may or may not have a mechanism to transfer the unused balls back to the ball dispenser unit.
Inspection tool 490 is configured to inspect the first substrate following the placing of the plurality of solder balls in the openings to determine a distribution of the solder balls in the openings. Inspection tool 490 may use optical detection to determine the distribution of the solder balls. Inspection tool 490 may be a microscope or it may include the use of automated optical inspection systems (AOI), which are commercially available and well known in the industry for inspecting solder ball arrays for defects.
Heating unit 495 is configured to heat the first substrate to mechanically and metallurgically join the balls onto the prepared electrical pads on the wafer. This system would be a belt furnace or similar system that has multiple heating zones that can be set at different temperatures to create a heating profile that is determined by the materials in the substrate and the solder alloy.
FIG. 6 shows a process 600 showing the general steps for forming the solder bumps on a substrate. At step 610, a photoresist layer is formed on a substrate. At step 620, the photoresist layer is patterned to form photoresist openings aligned with the set of electrical pads on the substrate. At step 630, a plurality of solder balls into the photoresist openings. At step 640, the electrical pads are electrically connected to the solder balls by reflowing the solder balls, thus forming the solder bumps.
At 610, the photoresist layer can be formed on a device chip. The layer is patterned such that the electrical pads of the device chip are exposed permitting the solder balls to make contact upon being supplied to the openings. The photoresist layer can either be returned or removed in the solder-connected product. For example, the photoresist layer can be removed after heating the solder balls to connect the solder balls to the electrical pads. In that situation, a solvent for the photoresist material can be used to dissolve the photoresist, and the solder-connected product is then dried of the solvent.
At 610, the photoresist is a high temperature photoresist which can have a temperature rating of at least 2000C. The above-noted WB3000™ family of photoresist can be used, but the invention is not limited to just this type of photoresist. Photoresists of similar properties are usable in the invention, and the invention is not limited to only the WB3000™ family of photoresist.
At 610 and 620, the photoresist openings are patterned and formed to have a depth that can vary from at least one-third of the solder ball diameter, to greater than the diameter of the solder ball to be used. The present invention is not particularly limited to any of these sizes. Rather, these sizes are chosen for the convenience of solder ball retention in the photoresist openings to facilitate the placement and holding of the solder balls in the openings.
At 610 and 620, the photoresist openings have a diameter either smaller than, equal to, or greater than a diameter of one of the electrical pads. Smaller diameter openings or greater diameter openings can be used. For example, it may be desirable to form a metal pad with diameter X then form photoresist openings of diameter Y where Y>X. There are two factors that determine the size of a solder bump formed on a substrate: the diameter of the pad the ball is joined to and the volume of the solder in the ball. Bumps with larger heights can be formed on a given pad by using a larger solder ball, which would require a larger diameter opening in the photoresist. Alternatively, smaller solder balls, and consequently smaller photoresist openings, might be used if the final bump size was to be smaller. The size of the photoresist opening used is a function of the size of the solder balls being deposited (which is determined by the final desired bump height) and the size of the pad the balls are joined to (which is typically a design factor determined by the pitch of the interconnects and mechanical strength considerations).
At 630, the solder balls can be distributed by agitating the solder balls to distribute the solder balls into the photoresist openings. Additionally, the substrate can be tilted during this or other stages of the ball distribution to permit not only dispersion of the balls but also the collection of excess solder balls not disposed in the photoresist openings, which may be collected in a tray proximate the substrate.
Numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.

Claims

CLAIMS:
1. A method for forming solder bumps on a substrate having electrical pads formed thereon, the method comprising: forming a photoresist layer on the substrate; patterning the photoresist layer to form photoresist openings aligned with the electrical pads on the substrate; supplying a plurality of solder balls into the photoresist openings; and connecting electrically the electrical pads to the solder balls by heating the solder balls to form said solder bumps.
2. The method of Claim 1, wherein forming comprises forming the photoresist layer on a device chip.
3. The method of Claim 1, further comprising removing the photoresist layer after heating the solder balls to form said solder bumps.
4. The method of Claim 1, wherein forming comprises depositing a photoresist material having a temperature rating of at least 2000C.
5. The method of Claim 1, wherein forming and patterning comprise: producing said photoresist openings having a depth at least one half a diameter of one of the solder balls.
6. The method of Claim 1, wherein forming and patterning comprises: producing said photoresist openings having a depth at least three-fourths a diameter of one of the solder balls.
7. The method of Claim 1, wherein forming and patterning comprises: producing said photoresist openings having a dimension smaller than or equal to a lateral dimension of one of the electrical pads.
8. The method of Claim 1, wherein forming and patterning comprises: producing said photoresist openings having a dimension greater than a lateral dimension of one of the electrical pads.
9. The method of Claim 1, wherein supplying comprises agitating the solder balls to distribute said plurality of solder balls into the photoresist openings.
10. The method of Claim 1, further comprising: tilting the first substrate after the supplying; and collecting excess solder balls that are not in the photoresist openings.
11. The method of Claim 11 , further comprising: collecting the excess solder balls in a tray located proximate to the substrate.
12. The method of Claim 1, further comprising: inspecting the substrate following the supplying of the plurality of solder balls into the photoresist openings to determine a distribution of the solder balls in the photoresist openings.
13. The method of Claim 12, wherein inspecting further comprises: optically inspecting the substrate after said supplying.
14. The method of Claim 12, further comprising: removing said photoresist layer; and reheating said solder bumps to form convex solder bumps.
15. The method of Claim 14, further comprising: aligning a second substrate with the first substrate; and bonding said second substrate to the solder bumps on the first substrate.
16. A stencil for solder ball bonding to a substrate having electrical pads formed thereon, comprising: a photoresist layer having a plurality of patterned openings aligned with the electrical pads on the substrate; and said patterned openings dimensioned to accommodate solder balls in the patterned openings.
17. The stencil of Claim 16, further comprising: at least one solder ball disposed in at least one of the plurality of patterned openings.
18. The stencil of Claim 16, further comprising: at least one solder ball bonded with one of the respective electrical pads.
19. The stencil of Claim 16, wherein the solder balls comprise at least one of Pb, Sn,
Cu, Ag, Au, In, Bi, Cd, Zn, and Sb.
20. The stencil of Claim 16, wherein said openings have depths that are at least one half of a diameter of one of the solder balls.
21. The stencil of Claim 16, wherein said openings have depths that are at least three- fourths of a diameter of one of the solder balls.
22. The stencil of Claim 16, wherein the patterned openings having a dimension smaller than or equal to a lateral dimension of one of the electrical pads.
23. The stencil of Claim 16, wherein the patterned openings having a dimension greater than a lateral dimension of one of the electrical pads.
24. The stencil of Claim 16, wherein the photoresist layer comprises a photoresist material having a temperature rating of at least 200°C.
25. A system for forming solder bumps on a substrate having electrical pads formed thereon, comprising: a photoresist unit configured to form a photoresist layer on the substrate and to pattern the photoresist layer to form openings aligned with the electrical pads on the substrate, said openings dimensioned to accommodate solder balls therein; a solder ball distribution unit configured to supply the solder balls into the openings; and a heating unit configured to heat the solder balls to form said solder bumps on the substrate.
26. The system of Claim 25, further comprising: an agitator configured to agitate the solder balls so as to distribute the solder balls into the openings.
27. The system of Claim 25, wherein the solder ball distribution unit comprises: a solder ball collector configured to collect excess solder balls that are not in the openings.
28. The system of Claim 25, further comprising: an inspection tool configured to inspect the substrate following placement of the solder balls in the openings to determine a distribution of the solder balls in the openings.
29. The system of Claim 25, wherein the inspection tool comprises an optical inspection unit.
30. The system of Claim 25, further comprising a wafer handler configured to place the substrate at a predetermined location.
31. A system for forming solder bumps on a substrate having electrical pads formed thereon, comprising: means for forming a photoresist layer on the substrate and means for patterning the photoresist layer to form openings aligned with the electrical pads on the substrate, said openings dimensioned to accommodate solder balls therein; a solder ball distribution unit configured to supply the solder balls into the openings; and a heating unit configured to heat the solder balls to form said solder bumps on the substrate.
PCT/US2009/035373 2008-04-04 2009-02-27 A solder bump bondig method, stencil. and system WO2009123808A2 (en)

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