WO2009128047A1

WO2009128047A1 - High density inductor, having a high quality factor

Info

Publication number: WO2009128047A1
Application number: PCT/IB2009/051603
Authority: WO
Inventors: Olivier Tesson
Original assignee: Nxp B.V.
Priority date: 2008-04-18
Filing date: 2009-04-17
Publication date: 2009-10-22

Abstract

The invention relates to high density inductors, having a high quality factor combined with a reduction of parasitic coupling with other parts. The present invention relates to an inductor for use in an electronic circuit and a method for producing the same. More specifically, the present invention relates to a high density inductor that is reduced in size to allow high density and a method of producing such a high density inductor. An inductor as an electronic part has the property of storing current energy. Inductors, such as solenoids, are used in DC-DC converters, switching power sources and other devices and equipped in various electronic apparatuses. In recent years, with downsizing and thickness reduction of electronic apparatuses such as cellular phones and personal digital assistants (PDAs), downsizing and thickness reduction of inductors have been demanded. Solenoids have been realized in IC's (such as on Silicon or glass substrate). However, the integration density as well as the reliability of the device is not regarded high enough. Recently the development of through wafer vias (TWI) has led to building of a single solenoid within silicon. It is noted that for recent applications in medical systems high value inductors are required for such applications (L>20nH).

Description

High density inductor, having a high quality factor

FIELD OF THE INVENTION

The invention relates to high density inductors, having a high quality factor combined with a parasitic coupling reduction. The present invention relates to an inductor for use in an electronic circuit and a method for producing the same. More specifically, the present invention relates to a high density inductor that is reduced in size to allow high density and a method of producing such high density inductor.

An inductor as an electronic part has the property of storing current energy. Inductors, such as solenoids, are used in DC-DC converters, switching power sources and other devices and equipped in various electronic apparatuses.

In recent years, with downsizing and thickness reduction of electronic apparatuses such as cellular phones and personal digital assistants (PDAs), downsizing and thickness reduction of inductors have been demanded. Solenoids have been realized in ICs (such as on Silicon or glass substrate). However, the integration density as well as the reliability of the device is not regarded high enough. Recently the development of through wafer vias (TWI) has led to building of a single solenoid within silicon. It is noted that for recent applications in medical systems high value inductors are required for such applications (L > 2OnH).

In the following, the structure and production method of conventional inductors will be described.

BACKGROUND OF THE INVENTION

US6218925 Bl discloses an electronic component, wherein the winding center line (Y) of a coil buried in a rectangular-parallelepiped-shaped chip is set on a straight line joining the central points of a pair of square opposed end surfaces of the chip where terminal electrodes and are formed, wherein the coil is arranged so that the winding locus of the coil as seen in the direction of the winding center line is located line-symmetrically around each of any two crossing straight lines crossing the winding center line (Y) of the coil perpendicularly, and wherein leadout conductors and each joining the end of the coil and the terminal electrode and are located at the respective ends of the chip on the winding center line of the coil. Thus, this electronic component includes the coil that prevents the inductance from being changed by the mounting orientation.

This document teaches a way to achieve a 3D solenoϊd within a laminate substrate. It describes a method to achieve this using a classical process. However, the 3rd direction used therein is orthogonal to wire tracks used. As a consequence one metal level is required per spiral, leading to lots of material to be used, that can have an impact on the cost. Furthermore, it is not so interesting in case of a SiP (System in Package) module, where substrate thickness is a key parameter. The configuration used is not a symmetrical configuration. Further, such a configuration will add a negative serial mutual inductive coupling within the substrate, leading to a decrease of the self- inductance value (density integration) as well as of the quality factor. Further, the geometry is not symmetrical, and thus not suitable for various applications. The twisted nature of the layout topology of the spirals does not allow to address in a single straightforward way EMC related issues. Placement of layers is not really optimized to really improve the quality factor. Furthermore, this case lacks an option of a better integration, e.g. with other components and within existing processes of manufacturing.

US2003/034867 Al discloses a coil and coil system for integration in a micro elecronic circuit. The coil is placed inside an oxide layer of a chip, and the oxide layer is placed on the substrate surface of a substrate. The coil comprises one or more windings, whereby the winding(s) is/are formed by at least segments of two conductor tracks, which are each provided in spatially spaced-apart metallization levels, and by via-contacts which connect these conductor track(s) and/or conductor track segments. In order to be able to produce high-quality coils, a coil is produced with the largest possible coil cross-section, whereby a standard metallization, especially a standard metallization using copper, can, however, be used for producing the oil. To this end, the via contacts are formed from a stack of two ore more via elements arranged one above the other. Parts of the metallization levels can be located between the via elements.

To summarize, the above disclosure is related to a way of producing a classical embedded solenoϊd and toroϊd shape within a substrate (ceramic or laminate). The main problem encountered by the different geometries presented here is correlated to the density of integration. Devices disclosed are not really area efficient, especially the toroϊd one. Further, it does not fully profit of the positive mutual coupling at the centre of the device (step 2 in the picture) leading to a reduced overall size of the device. US2005/150106 Al discloses a dielectric substrate having an embedded inductor wherein each turn of the inductor traverses several layers such that the top and bottom of each turn of the inductor are parallel to each other but are in different layers and the sides of each turn of the inductor traverse at least one layer to connect the top and bottom of the inductor. The above disclosure relates to a way to design a 3D solenoϊd within multilayer (metal/dielectric/metal/dielectric/...) structures. In terms of process, such a method to make metal tracks and via holes is well known for both laminate and Ceramic (LTCC ) processes. Laminate herein refers to a multi-layer structure incorporating layers made of a mix of e.g. PTFE (Teflon) and quartz fibers, with metallization between them. However, there is nothing related to integration density optimisation. In fact the pitch between tracks is via holes limited, and as a consequence design rules are much more aggressive (restrictive) in such a case. A solenoϊd generated in such a case will generate a magnetic field that has a unique reduction. So there is no improvement regarding EMC (Electro Magnetic Compatibility) related issue.

None of the coils disclosed in the above documents are 8 shaped 3-D coils.

Furthermore, prior art inductors typically do not achieve a high density per unit area. Another problem is that it is difficult to achieve inductors with a high quality factor, for instance at a frequency of 2 GHZ. Such a frequency is nowadays typically used in several applications, such as in mobile phones. Another problem is that prior art inductors suffer from parasitic coupling with other components that may be present, such as other parts of a circuit, other components in a SiP, etc.

Thus, there still is a need for an improved high density inductor, having a high quality factor.

The goal of the present invention is to solve one or more of the above mentioned problems and overcome one or more of the above mentioned disadvantages.

SUMMARY OF THE INVENTION

Surprisingly, the present invention provides inductors by using three dimensions within PCB, ceramic (LTCC) or organic laminate substrates. Thereby, a density of 40 nH per square millimeter is achieved, using a technique, with a quality factor of up to 60, at a frequency of 2 GHz. An eight-shaped inductor is used to increase the density, and also to reduce the parasitic coupling with other components that may be present, such as other parts of a circuit, other components in a SiP, etc.

The goal of the present invention is to use a SIP comprising a laminate, such as LTCC, Laminate or PCB as a carrier and to put an inductor inside the carrier. Compared to silicon where only two metalisation layers are available (namely on back-side and front side), 3 metal layers can be used in case of PCB, LTCC or Laminate. Using more metal layers, i.e. 3 or more, allows forming a specific shape (such as 8-shaped) solenoid. 8-shapes have two major advantages: the first one is that it increases the density due to a positive mutual coupling occurring at the center of the device and due to a length of metallization being greater than in a prior art single solenoid within a same bounding box. As the current goes in the clockwise direction for one loop and into the anti clockwise direction for another loop, coupling with any part of the outside world, such as a circuit, is drastically reduced compared to single solenoid. An other advantage of using this type of devices is that the time to market is reduced as a LTCC/PCB/Laminate process is much easier to process than e.g. a silicon process; though both processes are known, the few extra processing steps of a laminate process form only a minute part of a process compared to a silicon process. Thus, by the present invention a breakthrough is realized in terms of inductor integration and quality factor for SIP (see below). The present invention involves also very simple processes, the time to market and time to volume is drastically reduced compared to single solenoid based on silicon processes e.g. due to reduced complexity of the process. The reducing of the coupling phenomenon is also addressed, resulting in an improvement therein as well.

Various other advantages of the present invention are that an 8-shaped solenoid is essential to guarantee a high level of integration and a lower level of parasitic coupling. Further, use is made of the three dimensions of the carrier substrate. Furthermore, a low cost device completely embedded in the system is provided, with a further advantage that less time needs to be spent to build overall applications, compared to SMD 's.

DETAILED DESCRIPTION OF THE INVENTION

In a first aspect the present invention relates to a semiconductor device comprising one or more 3-dimensional spiralized 8-shaped solenoids, preferably being highly symmetrical, which one or more solenoids comprise a laminate and an inductor, which inductor is substantially inside the laminate, which inductor is formed out of at least three metal layers, which metal layers form electrically conducting tracks, wherein vias are present in between metal layers, which vias are in electrically connection between a first metal layer track and a second metal layer track, which one or more solenoids further comprise a first and second contact, wherein the first and second contact are in electrically connection, which solenoid preferably has from 1- 1000 8-shaped spirals, more preferably from 2-500 spirals, even more preferably from 4-250 spirals, most preferably from 5-100 spirals, such as 20 spirals.

Preferably the via has a length in the range from 0.25-1 times the width of a spiral, wherein the width of a spiral, in a perpendicular top view is defined is the distance from one via to a second via having one and the same metal track in between (see Fig. 1). Preferably the via has a length from 0.35-0.8 times the width of a spiral, more preferably from 0.4-0.6 times the width of a spiral, such as approximately 0.5 time the width. The more symmetrical the 8 shaped spiralized solenoid is, the better the quality factor of the solenoid is. Further, all vias preferably have substantially the same length, e.g. approximately 0.5 time the width.

The device may comprise one or more solenoids, such as two, three or even ten or fifty solenoids. Examples of various configurations of more than one solenoid are given in figures 13-15.

The laminate protects the solenoid from environmental and other influences. Preferably the laminate is chosen from the group consisting of laminate substrates such as PCB, LTCC, organic laminates and equivalents. The laminate may be present in the form of a multilayer laminate. Preferably the metal layers comprise an element chosen from the group of copper, aluminum, tungsten, or combinations thereof. Also the vias may be formed of such a metal, or combinations thereof. Alternatively, any conducting material may be chosen. It is important that such a material is compatible with the manufacturing process used, and that such a material has a good electrical conductivity, preferably also having a good thermal conductivity. Therefore copper is preferred. The material of the various metal layers and that of the vias need not be the same, e.g. the vias may be formed of tungsten, whereas the metal layers may be formed of aluminum, or copper, or a first metal layer may be formed of aluminum and a second metal layer may be formed of copper. In between metal layers an insulation layer, typically a dielectric, such as silicon oxide, low k-dielectric, and high-k dielectric, is present. Also a stack of insulation layers may be present. Preferably the dielectric layer is silicon oxide, such as TEOS, or oxidized silicon, or a combination of silicon oxide with on or more other oxides (see e.g. Figure 2). Metal layers, vias and first and second contact of the solenoid form one conducting 3 dimensional path (see Fig. 3). Through the path an electrical current runs (see Figs. 4 and 5). In a top part of a first 8 shape spiral the current runs in a first direction, whereas in a bottom part the current runs in an opposite directions, i.e. clockwise and counterclockwise, or, vice-versa. The same holds for adjacent loops in a configuration comprising more than one solenoid. As such the magnetic field generated by a current running in such an 8-shaped spiral is largely cancelled. The current always flows in the same way within the intermediate metal that as a consequence will induce a positive mutual coupling inductance. This mutual inductance will be accounted for in a final value of the device self- inductance (see below). So, surprisingly it is found that the inductance value is increased due to the length of metallization and due to the positive mutual coupling that occurs in the core of the device. This is a tremendous advantage of the present solenoid over a circular solenoid.

For a good quality factor and a good inductance the 3 -dimensional spiralized 8-shaped solenoid according to the invention preferably comprises more than 1 spiral, such as 10 spirals. On the other hand, typically one is limited in space, and therefore the present solenoid preferably comprises less than 1000 spirals. An example of a present solenoid has the following characteristics:

L = 19 nH; Q-factor = 70 @ 2GHz; length = 1000 μm, and width = 450 μm.

In a further embodiment the present solenoid profits from an enlargement of the horizontal tracks, in order to minimize the serial electrical resistance. However, by doing this, the solenoid will tend to decrease the intrinsic self-inductance value developed by the tracks. In fact the self-inductance value per unit length value of a metal trace is decreasing when track thickness and track width are increasing. So, as the quality factor in a low frequency domain can be expressed as follows:

L ω

Q =

R

A smaller value of L will lead to a smaller value of Q. But on the other side there is a way to increase the mutual coupling between tracks so to increase the device self-inductance value only by enlarging the tracks. According to the following formula the self- inductance is equal to: n n

L = Σ Σ Mij i=l j=l

Therein L is the inductance of a solenoid, i and j refer to the i^th and j^th spiral, respectively, and M is the inductance between spiral i and j. In the case where i=j the situation refers to the self inductance of the spiral. So the mutual inductance value will participate to the total self-inductance value and a gain is also expected on the quality factor. Then, of course, a good balance must be found by the gain realized by this operation and the loss induced by the enlargement of the tracks. So, the inductance density in that case is not limited by vias, as is the case in the prior art, but only follows the minimum spacing DRC rule between metal tracks. From a practical point of view, however, it is preferred to avoid to use the minimum DRC (Design Rules Check) rules which in that case is in the same order of magnitude for the Self- Resonant Frequency (SRF).

Fig. Ib gives an overview on the way the tracks (141 top track; 111 bottom track; 140 via; 110 via) are enlarged. Also indicated are the width and length of the solenoid. In that case, mutual coupling between tracks is maximized in order to at least keep the density integration constant, which methodology applied is described below, and the serial electrical resistance value is decreased leading to higher quality factor at low frequency, such as 1 GHz. From a physical point of view the self- inductance per unit length value is decreasing with track width and thickness (very slightly) while it is increasing with conductor length. On the other side coupling between tracks is increasing with the inverse of track spacing. The trade-off here consists in finding the right balance between track self-inductance and mutual track coupling. Fig. 7 shows the evolution of the inductance contribution as a function of the track width (top curves); the evolution of the total self-inductance value as a function of the track width is an enlarged fragment of the top curve (bottom curve). So preferably the track width is smaller than 30 μm, or larger than 65 μm.

Then the electrical serial resistance is calculated and an estimation of the quality factor is carried-out and this confirms the previous choice in the solenoid parameters (i.e. track width).

Fig. 7 b shows the evolution of the inductance contribution as a function of the normalized track width (top curves); the evolution of the total self- inductance value as a function of the normalized track width is an enlarged fragment of the top curve (bottom curve). The normalized track width W/Wi is normalized with respect to a classical width, in this case having a width of 30 μm. The thickness of the tracks is 8 μm. Typically the tracks are formed of copper. The relative thickness of the tracks becomes only important if it becomes approximately as large as the width. It can be seen that if the width is taken to be larger than approximately 2.2 times that of the classical case, the inductance is optimized.

Fig. 8 shows the evolution of electrical serial resistance of the normalized track width (top curves); and evolution of the estimated Q-factor as a function of the normalized track width (bottom curves). The positive effect on relative resistance R/Ro and relative quality factor Q/Qo can be seen from these graphs, wherein Ro and Qo are the resistance and quality factor of the reference or classical solenoid, respectively.

EM simulations with the help of a 3D simulator have been carried out in order to quantify the advantages added by this design improvement. Results are presented on the following Figures:

Fig. 9 shows simulation results showing the variations against frequency of the self inductance value (top curves) and the quality factor (bottom curves). Surprisingly the present invention shows an improved self inductance as well as an improved quality factor.

We can clearly see the big impact of the proposed invention on the quality factor. Its value is increased by 60% (see Fig. 15) over a broad frequency range (from 1*10⁶- 1*10⁹ Hz), whereas at the same time the self inductance is in the same order of magnitude (5% more), but anyhow improved as well. Advantages of the present embodiment are that a single method to enlarge the horizontal tracks of a 3D solenoid in an Si IC process leads to a improvement by 50-60% of the quality factor.

Further, this improvement does not have any negative impact on other intrinsic electrical parameters of the device itself, such as SRF (Self Resonant Frequency) and Self-Inductance value.

It is noted that the present embodiment does not impact the layout of the floor plan (i.e. the footprint of the improved solenoid is not larger a comparable one with classical tracks).

Even further, the design of the present solenoid is not more limited by design rules related to through wafer interconnects (or vias) that are not so much aggressive.

More over, a twisted 3D architecture is described leading to a decrease of EMC related issues together combined with a higher density integration. Thus, the present invention teaches a way to achieve a high value of quality factor only by modifying the design of the horizontal tracks (on top and back side top metals of the process). The self inductance-value is not impacted as the mutual coupling between tracks is maximized. It leads to a drastically reduction of electrical serial resistance value. The present solenoid can be easily used within SiP products in order to realize a low cost and embedded matching network.

Preferably the present solenoid has a length which is from 100 μm - 10.000 μm, preferably from 500 μm - 5.000 μm, more preferably from 750 μm - 3.000 μm, even more preferably from 1000 μm - 2.500 μm, such as 1500 μm, and wherein the width of the solenoid is from 10 μm - 5.000 μm, preferably from 20 μm - 2.000 μm, more preferably from 100 μm - 1.000 μm, even more preferably from 250 μm - 500 μm, such as 400 μm. For a good quality factor and a good inductance the length is preferably not too short. A too long length does not improve the quality factor and inductance that much and occupies too much room, and is therefore less preferred.

The present solenoid can be embedded within the PCB of a new applications coming from emerging business, especially for health care applications. It can be used in e.g. very emerging health care applications: a temperature sensor embedded in a hard gelatine capsule. The patient just needs to eat the capsule and it will establish the communication with a receptor and give the temperature of the human body in real time. Four "big" inductors are needed for this type of applications and of course the capsule needs to be as light/small as possible. Indeed, health care application refers to a typical market where applications weight plays a significant role in the choice of technology/packaging (SiP, ...) and where the design of each device must be optimized in that sense. But this is not the only application of such devices. All SIP applications that have matching network or ESD protection requiring high inductance value can be addressed by this device.

Performances can be also improved by using four or five metal layers carrier substrate. In that case a cross section of the device would look like an 8-shaped on top of another 8-shaped. As such, more than one, such as two, three or four 8- shaped solenoids on top of each other are also envisaged. In a second aspect the present invention relates to a system in package comprising a semiconductor device according to the invention.

In a third aspect the present invention relates to a method for manufacturing a semiconductor device according to the invention, comprising the steps of: providing a substrate, preferably a laminate chose from the group consisting of Laminate substrates such as LTCC, and PCB; organic Laminates, such as those made of PTFE (Teflon) and glass fibers, applying a first metal layer on the substrate; - patterning and etching said first metal layer; applying a first dielectric layer on the substrate; forming vias in the first dielectric layer; applying a second metal layer on the substrate; patterning and etching said second metal layer; - applying a second dielectric layer on the substrate; forming vias in the second dielectric layer; applying a third metal layer on the substrate; patterning and etching said third metal layer; protecting the metal layer from environmental influence, such as by applying a laminate.

Advantages of said method are given above. In order to provide new solutions to reduce the costs, increase performances and the complexity of the designs, some new processes have been developed for RF applications. These new processes (i.e. new substrates) allow many functionality associations such as filtering, amplifier on a planar surface made of several sheets (ceramic, Teflon and so on) on which interconnections and passive elements can be deposited by various thick films techniques. Low Temperature Co- fired Ceramic materials (LTCC) consist of a mixture of glass, ceramic and organic materials, which are cast into, green sheets. A ceramic is by definition a non-organic poly crystalline material that has a very complex structure. The present application refers to the more complex ones used for electronic or thermo mechanical applications. One of the ceramics used by the electronic industry is alumina. It belongs to the family of monoxides. Various types of alumina exist having a different purity,a different relative permittivity at IMHz, a different Tan .and a different thermal conductivity, respectively.

Fig. 10 shows a sample of high temperature superconducting ceramic that has been synthesised at the Argonne National Laboratory. It is like a sheet and it has been prepared to be fired. After this operation, it will be very hard. This one is an "YBaCo" which is very well known by the scientist because of its high temperature superconducting properties.

The sheets need to be slitted. Mostly the greensheets are shipped on a roll; the tape has to be unrolled onto a clean, stainless steel table. The sheet is e.g. cut with a razor, laser or a punch into parts (these parts have to be a little larger than the blank size, if the material needs to be preconditioned). If a laser is used it is necessary to control the power to avoid firing of the sheets.

The sheets may be preconditioned. Some tapes need to be preconditioned; that means the greensheet has to be baked for about half an hour at e.g. 120⁰C (which depends on material). Normally the tapes are shipped with an applied foil/bake sheet, which has to be removed before lamination at the latest; some processors use this foil as a filling mask for the vias.

The sheets may be blanked. A blanking die is used to create orientation marks and lamination tooling holes (and the final working dimension in case of to be preconditioned tapes). It is preferred to rotate the single parts in turn 90° to compensate for a different x/y-shrinking of an LTCC.

Next, vias may be punched or drilled with a laser (low power). Vias can be filled with a conventional thick film screen printer or an extrusion via filler. In the first case the tape has to be placed on a sheet of paper which lays on a porous stone; a vacuum pump holds the tape on his place and is used as an aid for via filling. However, the possibilities of this method are limited; the vias must have a larger diameter than tape thickness. The smallest possible size of vias to be filled also depends on the viscosity of the paste. The second possibility to fill the vias is to use a special extrusion via filler that works with pressures of about 4 to 4.5 bar. Both methods need to have a mask; this mask should be made of a 150-200 mm thick stainless steel. An alternative to that is to use the (Mylar-)foil the tape usually is applied on. For the filling of blind vias it is advisable to form the holes concerned of the masks a little smaller than the diameter of the blind vias. Otherwise there could occur problems with the filling rate.

Cofireable conductors etc. are printed on the green sheet using a conventional thick film screen printer. The screens are standard (250 - 325) emulsion type thick film screens. Just like the via printing process, a porous stone is used to hold the tape in place. Printing of the conductor tends to be easier and of higher resolution than standard thick film on alumina. This is due to the flatness and solvent absorption of the tape. After printing, the vias and conductors have to be dried in an oven at 80 to 120⁰C for 5 to 30 minutes (depends on material); some pastes need to level at room temperature for a few minutes before drying. Resistors may vary their value when terminated with different conductors. With the help of a Micro -Screen printer, it is possible to print conductors with a 50mm line resolution.

Each layer is placed in turns over tooling pins in order to register for Lamination. Some processors use a heat pliers to fix the sheets in turns one on top of the other.

There are two possibilities of laminating the tapes. The first is named uniaxial lamination; the tapes are pressed between heated platens at 70⁰C, 200 bar for 10 minutes (typical values). This method requires a 180° rotation after half the time. The uniaxial lamination could cause problems with cavities / windows. This method causes higher shrinking tolerances than the isostatic lamination. The main problem therein is the flowing of the tape; that results in high shrinkage tolerances (especially at the edge of the part) during the firing and varying thicknesses of single parts of each layer (causes hard problems on the high frequencies sector). The second way is to use an isostatic press. The stacked tapes are vacuum packaged in a foil and pressed in hot water (temperature and time are just the same like using the uniaxial press). The pressure is about 350 bar. However, deep cavities and windows need to have an inlay during lamination.

Laminates are fired in one step on a smooth, flat setter tile. The firing should follow a specific firing profile, what causes the need of a programmable box kiln. A typical profile shows a (slow) rising temperature (about 2-5°C per minute) up to about 450⁰C with a dwell time of about one to two hours, where the organic burnout (binder) takes place; then the temperature has to be rised up to 850 to 875°C with a dwell time of about 10 to 15 minutes. The hole firing cycle lasts between three and eight hours (depends on the material; large / thick parts cause the need of a modification of the firing profile). Especially resistor pastes need to have defined firing conditions (temperatures);Otherwise they vary enormous in value. Some materials need to be postfϊred; that means the paste is to be applied after firing the tape and has to be fired again. The posturing conditions depend on the used material and vary in a wide range. Again, especially resistor pastes need to have defined firing conditions (temperatures); Otherwise they vary enormous in value. If the fired parts have to be cut into smaller pieces or other shapes, there are three different ways to realize. The first is to use a post fire dicing saw, which is a common method and works very well for rectangular shapes; it holds tight outside dimensional tolerances and allows high quality edges. The second possibility is to use an ultrasonic cutter; the final part shows low tolerances and may have unusually shapes. This process is very slow and expensive. The third method uses a laser to cut the fired tape; the tolerances are tight, but the quality of the edges is very bad.

One of the important advantage of the use of LTCC materials, in addition to the low co-firing temperature, is the possibility to check printing quality of each sheet layer individually due to the parallel processing. This is very interesting in term of process-time and cost saving. Then, using LTCC instead of HTCC (high temperature) has also a big advantage: it allows to use metals that have a low melting point such as silver which is better for RF performance than Tungsten for instance that is necessary in HTCC process to make the interconnections or spirals (electrical resistivity of tungsten is 4 times higher than electrical resistivity of silver).

Because of shrinking of the LTCC tapes during the firing it is necessary to observe various design rules. The following part is based on a few design guides. It gives an idea of the possibilities of LTCCs.

Table 1 Design rules generally observed on LTCCs products

Furthermore there is no real limitation related to the shape of vias and circuits shapes. The most common conssts in using round and/or circular vias and rectangular shapes for metallization. But of course, for typical application (coil, balun,...), having special shapes (octagonal, circular,...) is allowed and is feasible.

Concerning the number of layers that you can use in such a sandwich, it is strongly related to thickness of each layer and of to the size of the envisaged package. Usually a maximum number of 10 to 50 layers can be realized and a minimum of 2 to 4 layers is admitted.

The laminate term is a very generic one. In fact, most of the substrates (except silicon) have a lamination step during their manufacturing process. In this part, we will briefly describe Organic laminate substrate suitable for RF and millimetre wave applications.

A laminate substrate is generally made of three or four metallic levels with thick (25 to 200 μm) dielectric organic layers between them. There are two major methods used to deposit the metallization layer at the surface of the dielectric. The former consists on growing electroplated copper and the latter consists in laminating the layer with metal. In case of the second option costs are bigger, but it leads to a high quality surface state on top of the metal (in case of RF it is also an important criteria). The dielectric layer is generally made of a sandwich of several layers such as (glass fibres, quartz, quartz fibres, carbon with some PTFE (well known as Teflon®).

By combining several material, It is possible to obtain "a global sandwich" with different relative permittivity. The relative permittivity of PTFE is equal to 2.07 while the one of glass fibres is equal to 6.0. It is also possible to incorporate ceramic inside the PTFE to increase the relative permittivity.

The following table summarizes the most common materials used with their relative physical properties.

Table 2 Example of physical properties for various laminate substrate

(courtesy of Claudine Vasseur).

Design rules for laminate rules are in the same order of magnitude as in

LTCC substrate. Typically, each dielectric layer has thickness of about 35 μm to 100 μm. Thickness of metal layers is generally comprised between 20 μm and 30 μm. It is generally thicker than in LTCC; it leads to lower resistance and also inductance. Concerning the line width a value of 65 μm (30 um possible) is generally admitted with an average space of 70 μm. In term of global sandwich, a maximum of four dielectric layers is generally used. Low cost laminate solutions utilize mechanical drilled vias that are 200 μm diameters. The via Hole is partially filled with metal. However, the hole is too large to be completely filled with metal.

The present invention is further elucidated by the following figures and examples, which are not intended to limit the scope of the invention. The person skilled in the art will understand that various embodiments may be combined.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig.1 a. Top view of a solenoid.

Fig. Ib. Enlarged width of tracks. For reasons of clarity a spiralized circular solenoid is shown.

Fig. 2. Cross section of the 3-metals process used. Fig. 3. 3D general view of the device. Fig. 4. Direction of the current within different metal layers - Only a part of the solenoid is represented.

Fig. 5. Direction of the current within different metal layers - Only a part of the solenoid is represented.

Fig. 6. Direction of the current within different metal layers - Only a part of the solenoid is represented. Fig.7 shows the evolution of the inductance contribution as a function of the track width (top curves); the evolution of the total self- inductance value as a function of the track width is an enlarged fragment of the top curve (bottom curve). Fig.7 b shows the evolution of the inductance contribution as a function of the normalized track width (top curves); the evolution of the total self- inductance value as a function of the normalized track width is an enlarged fragment of the top curve (bottom curve).

Fig.8 shows the evolution of electrical serial resistance of the normalized track width (top curves); and evolution of the estimated Q-factor as a function of the normalized track width (bottom curves).

Fig.9 Shows simulation results showing the variations against frequency of the self inductance value (top curves) and the quality factor (bottom curves). Fig.10 shows a sample of high temperature superconducting ceramic that has been synthesised at the Argonne National Laboratory. Fig.11 shows a solenoid.

Fig.12 shows two parallel lines wherein G: Line width; H: Line spacing; I: Line pitch. Fig.13 shows a stack of 3 8-shaped spiralized solenoids for a process having multi metallization layers. (100) is a metal layer, whereas (110) is a dielectric layer.

Fig.14 shows 2 adjacent 8-shaped spiralized solenoids. (100) is a metal layer, whereas (110) is a dielectric layer. Fig.15 shows the electrical current flow in 2 adjacent 8-shaped spiralized solenoids. (100) is a metal layer, whereas (110) is a dielectric layer.

DETAILED DESCRIPTION OF THE DRAWINGS

Fig. Ia. Top view of a solenoid : 141 : top metal , 111 : intermediate metal, 100: bottom metal. Vias between metals are represented in as 140 and 110 in the figure, respectively between top metal and intermediate metal and between bottom metal and intermediate metal. Vias are drawn as semi-circular fillings, e.g. as octagon.

Fig. Ib. Enlarged width of tracks. For reasons of clarity a spiralized circular solenoid is shown. Compared to figure Ia the width of the tracks 141, 100 and 111 has been increased, respectively. Also variations in relative width of tracks 141, 100 and 111 are envisaged.

Fig. 2. Cross section of the 3-metals process used. 241 : top metal , 211 : intermediate metal, 200: bottom metal. Vias between metals are represented in as 240 and 210 in the figure, respectively between top metal and intermediate metal and between bottom metal and intermediate metal. Vias are typically semi-circular fillings, e.g. as octagon. Further also dielectric layers 230 and 220 are visible. Typical thickness of the dielectric layers is form 5-300 μm, wherein variations are envisaged as explained above. Fig. 3. 3D general view of the device. A 3 dimensional structure of the solenoid is given. Therein the vias are visible as pillar like structures, and the metal tracks as plate formed objects. Also the 8-shape and spiral structure of the solenoid is visible.

Fig. 4. Direction of the current within different metal layers - Only a part of the solenoid is represented. The electrical current runs partly clockwise and partly anti-clockwise, which configuration may also be reversed. Thereby the magnetic field of a top part and of a bottom part of one eight shape are largely cancelled.

Fig. 5. Direction of the current within different metal layers - Only a part of the solenoid is represented. The electrical current runs partly clockwise and partly anti-clockwise, which configuration may also be reversed. Thereby the magnetic field of a top part and of a bottom part of one eight shape are largely cancelled.

Fig. 6. Direction of the current within different metal layers - Only a part of the solenoid is represented. The magnetic field B is largely cancelled, due to an electrical current that runs partly clockwise and partly anti-clockwise. It is noted that the middle section in fact represents two metal lines, projected on top of each other, on part connecting a first top part of the 8-shaped inductor to a bottom part thereof, and one part connecting the bottom part thereof to a second top part of the 8- shaped inductor.

Fig.7 shows the evolution of the inductance contribution as a function of the track width (top curves); the evolution of the total self-inductance value as a function of the track width is an enlarged fragment of the top curve (bottom curve).

Fig.7 b shows the evolution of the inductance contribution as a function of the normalized track width (top curves); the evolution of the total self- inductance value as a function of the normalized track width is an enlarged fragment of the top curve (bottom curve). Fig.8 shows the evolution of electrical serial resistance of the normalized track width (top curves); and evolution of the estimated Q-factor as a function of the normalized track width (bottom curves).

Fig.9 Shows simulation results showing the variations against frequency of the self inductance value (top curves) and the quality factor (bottom curves).

Fig.10 shows a sample of high temperature superconducting ceramic that has been synthesysed at the Argonne National Laboratory.

Fig.l 1 shows a solenoid wherein 1 : Top Side External Conductor; 2: Cofired or Postfϊred surface resistor; 3: Buried resistor; 4: Buried via; 5: Buried capacitor; 6: Stacked vias; 7: Blind via; A: Via cover Pad; B: Via diameter; C: Via Stagger; D: Via Spacing; E: Via Pitch; F: Via center to Part Edge.

Fig.12 shows two parallel lines wherein G: Line width; H: Line spacing; I: Line pitch.

Fig.13 shows a stack of 3 8-shaped spiralized solenoids for a process having multi metallization layers. (100) is a metal layer, whereas (110) is a dielectric layer.

Fig.14 shows 2 adjacent 8-shaped spiralized solenoids. (100) is a metal layer, whereas (110) is a dielectric layer.

Fig.15 shows the electrical current flow in 2 adjacent 8-shaped spiralized solenoids. (100) is a metal layer, whereas (110) is a dielectric layer.

Claims

High density inductor, having a high quality factor CLAIMS:

1. Semiconductor device comprising one or more 3-dimensional spiralized 8-shaped solenoids, preferably being highly symmetrical, which one or more solenoids comprise a laminate and an inductor, which inductor is substantially inside the laminate, which inductor is formed out of at least three metal layers, which metal layers form electrically conducting tracks, wherein vias are present in between metal layers, which vias are in electrically connection between a first metal layer track and a second metal layer track, which one or more solenoids further comprise a first and second contact, wherein the first and second contact are in electrically connection, which solenoid preferably has from 1-1000 8-shaped spirals, more preferably from 2- 500 spirals, even more preferably from 4-250 spirals, most preferably from 5-100 spirals, such as 20 spirals.

2. Semiconductor device according to claims 1, wherein the material of the laminate is chosen from the group consisting of PCB, LTCC, laminate substrates, and organic laminates.

3. Semiconductor device according to any of claims 1-2, wherein the metal layers comprise an element chosen from the group of copper, aluminum, tungsten, or combinations thereof.

4. Semiconductor device according to any of claims 1-3, wherein the vias comprise an element chosen from the group of copper, aluminum, tungsten, or combinations thereof.

5. Semiconductor device according to any of claims 1-4, wherein the metal layers are separated by a dielectric layer, which dielectric layer comprises a material chosen from the group of silicon dioxide, low-k dielectric material, high k dielectric material, or combinations thereof.

6. Semiconductor device according to any of claims 1-5, wherein the length of the one or more solenoids is from 100 μm - 10.000 μm, preferably from 500 μm - 5.000 μm, more preferably from 750 μm - 3.000 μm, even more preferably from 1000 μm - 2.500 μm, such as 1500 μm, and wherein the width of the solenoid is from 10 μm - 5.000 μm, preferably from 20 μm - 2.000 μm, more preferably from 100 μm - 1.000 μm, even more preferably from 250 μm - 500 μm, such as 400 μm.

7. System in package comprising a semiconductor device according to any of claims 1-6.

8. Method for manufacturing a semiconductor device according to any of claims 1-6, comprising the steps of: providing a substrate, preferably a laminate chosen from the group consisting of Laminate substrates, such as LTCC, and PCB; organic Laminates, such as those made of PTFE (Teflon) and glass fiber; applying a first metal layer on the substrate; - patterning and etching said first metal layer; applying a first dielectric layer on the substrate; forming vias in the first dielectric layer; applying a second metal layer on the substrate; patterning and etching said second metal layer; - applying a second dielectric layer on the substrate; forming vias in the second dielectric layer; applying a third metal layer on the substrate; patterning and etching said third metal layer; protecting the metal layer from environmental influence, such as by applying a laminate.