WO2011003057A2 - Method of forming monolithic cmos-mems hybrid integrated, packaged structures - Google Patents

Method of forming monolithic cmos-mems hybrid integrated, packaged structures Download PDF

Info

Publication number
WO2011003057A2
WO2011003057A2 PCT/US2010/040890 US2010040890W WO2011003057A2 WO 2011003057 A2 WO2011003057 A2 WO 2011003057A2 US 2010040890 W US2010040890 W US 2010040890W WO 2011003057 A2 WO2011003057 A2 WO 2011003057A2
Authority
WO
WIPO (PCT)
Prior art keywords
chip
layer
applying
substrate
overlying
Prior art date
Application number
PCT/US2010/040890
Other languages
French (fr)
Other versions
WO2011003057A3 (en
Inventor
Krishna G. Kumar
Nishit A. Choksi
Joseph M. Chalil
Original Assignee
Advanced Microfab, LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Microfab, LLC filed Critical Advanced Microfab, LLC
Publication of WO2011003057A2 publication Critical patent/WO2011003057A2/en
Publication of WO2011003057A3 publication Critical patent/WO2011003057A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/0023—Packaging together an electronic processing unit die and a micromechanical structure die
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/00238—Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01077—Iridium [Ir]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Definitions

  • the invention relates to a method for integrating MEMS and CMOS structures.
  • MEMS/NEMS and electronics offer significant benefits enabling high volume production driving down the per-unit costs of sensor and actuator systems significantly.
  • Micromechanical transducer systems not only need to receive analog and digital electrical inputs and transmit the output, but should also be able to measure rotation, strain, temperature, pressure, acceleration, infrared radiation, micro fluidic chemical properties of liquids and gasses.
  • Effective integration offers other benefits, including, simplifying interconnect issues, reduced packaging and fabrication complexity and significantly improving the overall performance and ease of use for the device.
  • CMOS complementary metal-oxide semiconductor
  • MEMS micromechanical
  • Monolithic integration process may be divided into three classes: (1) Pre CMOS (2) Intermediate CMOS (3) Post CMOS.
  • pre CMOS fabrication process methods
  • MEMS/NEMS structures are fabricated before the electronics are integrated.
  • MEMS/NEMS structures are fabricated before the electronics are integrated.
  • MEMS/NEMS structures are fabricated before the electronics are integrated.
  • This process is the micromechanics-first approach developed at Sandia National Laboratory by J. Smith et al.
  • CMP chemical- mechanical polishing
  • Conventional CMOS processing was then carried out next to this MEMS area. This defined a CMOS device area and micromechanical device area on the same substrate as shown in Fig. 1.
  • One of the disadvantages with this process is that it needs a dedicated production line and the process is complicated.
  • CMOS complementary metal-oxide-semiconductor
  • MEMS/NEMS structures are fabricated after the CMOS or electronics is fabricated on the substrate.
  • the disadvantage of this process is the temperature limitation of the process to below 400 0 C to protect the aluminum in the electronics. This leads to the elimination of commonly used MEMS/NEMS high temperature materials like LPCVD polysilicon, silicon nitride etc.
  • CMOS complimentary metal-oxide semiconductor
  • Prior art hybrid MCM technology processes include putting one or several dies with different functionality into prefabricated trenches on a substrate, planarizing these chips, providing an insulator layer on top and forming electrodes have been demonstrated in US Patent: 6403463, US Patent No:6780696 Bl, US Patent 6154366 , US Patent No.:6,759,270.
  • Some of the major drawbacks in these prior art references include semiconductor substrates like silicon that are fragile and the devices need to be repackaged resulting in significant costs.
  • the invention describes a method of manufacture for Monolithic hybrid integration of CMOS-MEMS with enhanced flexibility of using materials without hindrance to process parameters. This invention enables this integration effectively without the need to sacrifice the inherent strengths of both the CMOS or MEMS technologies and bringing about their fusion in a hybrid approach on a common substrate. This invention also allows the ability to effectively package the entire system after integration.
  • CMOS-MEMS/NEMS functionality Several of the limitations mentioned above are overcome in the present invention which describes a method to effectively synergize CMOS-MEMS/NEMS functionality and finally package them creating a very cost effective, reliable, robust transduction system
  • protective layers are coated on the substrate to protect either the CMOS device area in the "Post CMOS” process or the MEMS device area in the "Pre CMOS” process to prevent damage to the sensor or electronics.
  • Oxygen plasma etching can be used to open the vias to access conductive layers, being precisely defined by photolithography instead of laser which is known to cause damage in some of the previous integration approaches.
  • Either the "Post CMOS” or “Pre CMOS” fabrication may be carried out on a semiconductor substrate without compromising on the individual technologies strength and then integrating CMOS if MEMS is already present or MEMS if CMOS is already present on the same substrate.
  • the invention provides an improved ability to effectively package an entire system using a glass, silicon, plastic or metal housing.
  • Packaging provides physical protection against external scratching and breakage, environmental protection and any other external forces that may damage the leads or the sensors. Effective packaging of the integrated system leads to lower cost, improved reliability and improved performance.
  • This invention addresses some of the important issues present in current packaging methodologies. As one specific example related to reliability issues with plastic packages, the Thermal coefficient of expansion (TCE) mismatch resulting from the curing of the resins as they shrink in volume, creates a large temperature differential resulting in large strain mismatch, damaging the wire bonds. This issue can be eliminated or reduced significantly in the present invention as there will be no wire bonds involved and the fabrication is planar and the metal traces can be more effectively protected.
  • TCE Thermal coefficient of expansion
  • the packaging methodology from the current invention also eliminates the need for solder bumps for integration of CMOS-MEMS and packaging.
  • the invention also provides a method to further encapsulate the entire system by adding a secondary protective layer of organic materials providing a very effective packaging methodology.
  • the invention relates to a method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures.
  • the method includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contact area; applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the
  • the method includes the steps of: providing a semiconductor substrate having MEMS/NEMS materials including mechanical structural layers and conductive layers; applying a first insulating layer overlying the MEMS/NEMS materials; applying at least one protective layer overlying the MEM/NEMS materials; forming at least one opening on the protective layer to access the semiconductor substrate; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a front face and a bare backside; applying a second insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contact area; applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one another contact area on the chip; applying a third insulating layer overlying the metallization layer on the at least one chip; performing at least one post micro/n
  • FIG. 1 Prior Art showing cross-section of the embedded micromechanics approach to
  • FIG. 2 Prior Art showing simplified cross-sectional view of HDI interconnect MCM technology from GE;
  • Fig. 3a-3h is a cross-sectional view showing the process flow for building a "post
  • CMOS monolithic CMOS-MEMS hybrid integration system and packaging
  • Fig. 4a-Fig.4f is a cross- sectional view showing the process flow for building a "pre
  • CMOS monolithic CMOS-MEMS hybrid integration system
  • Fig. 4(gl-g4) is a cross-sectional view showing the post fabrication of the integrated CMOS MEMS realizing a suspended structure using isotropic etching and finally packaged;
  • Fig. 4(hl-h5) is a cross-sectional view showing the post fabrication of the integrated circuit
  • CMOS MEMS realizing anisotropic etching in the front and backside and finally packaged.
  • CMOS complementary metal-oxide-semiconductor
  • CMOS first hybrid integration approach shown in Figs 3a-3h
  • the already fabricated CMOS semiconductor substrate is modified to achieve this integration.
  • the CMOS device area is first protected so as not to affect their functionality in the ensuing process; fabrication is continued on the same substrate and integrated by coupling the micromechanical structures in a hybrid approach by placing the MEMS/NEMS dies that have been diced.
  • the integrated system is finally packaged in an effective manner.
  • FIG. 3a-h there is shown a cross-sectional process flow for the "Post CMOS" monolithic hybrid integration approach on a semiconductor substrate 302.
  • a CMOS fabricated semiconductor substrate 302 with dielectric layers and metallization in Fig.
  • the CMOS device area 304 may include digital logic circuits, operational amplifiers, inverters, analog and digital circuitry, digital switches, voltage comparators which enable the sensors and actuators to receive analog and digital signals for their effective operation.
  • a protective layer 306 may be applied to the CMOS semiconductor substrate 302 by either spin coated or deposited in vacuum to protect the CMOS area 304 from further processing steps.
  • Protective layer 306 may be selected from oxides, nitrides, polymers, or their combination having a thickness of sub-microns to several microns and that which can effectively protect the electronics.
  • the protective layer 306 may be selectively patterned using lithography and etched anisotropically using oxygen plasma RIE for materials such as polyimide and parylene to define a trench 308 outside of the CMOS device area 304.
  • the trench 308 may be etched using DRIE Bosch process and may be lithographically defined by the size of a chip 312.
  • the protective layer 306 may be left behind or removed.
  • a filler layer 310 may be deposited or dispensed into the trench 308 to anchor a chip 312 into the trench 308 and also to fill a gap between the chip 312 and the wall of the trench 308 and will also ensure the planarity of the chip 312 to the substrate 302.
  • the filler material 310 may be selected from oxides, polyimides, silicones, epoxiess, or their combination or any other materials with similar properties.
  • CMOS integrated chip may include voltage comparators, diodes, op-amps, or other electronic components like power management circuits, resistors, capacitors, and inductors.
  • a MEMS/NEMS dies may include but are not limited to accelerometers, resonators, micro-gyroscopes, microphones, micro-bolometers, transducers involving chemical and biological, optical, mechanical, radiation, thermal, capacitive, rotation, strain, magnetic and electromagnetic, flow, and micro-fluidic chemical properties of liquids and gases.
  • a first insulating layer 314 may be deposited covering the front face and/or the sides of the chip 312 providing the continuity from the semiconductor substrate 302 to the chip 312.
  • the first insulating layer 314 may be selected from polymers, oxides, nitrides, glass, quartz polyimide, parylene, silicone, or a combination of the above.
  • At least one via opening 316 may be etched through the first insulation layer 314 to make electrical contact.
  • the first insulation layer 314 may be anisotropically etched using oxygen plasma or may be etched using wet or dry etching.
  • a metallization layer 318 may be applied to connect the CMOS area 304 on the semiconductor substrate 302 to the chip 312 which may include a contact area having an input/output pad or bond area to make electrical contact.
  • the metallization layer 318 may be selected from metals such as, aluminum, copper, titanium, chrome, gold, silver, iridium or their combination that can be evaporated, sputtered or electroplated.
  • a second insulating layer 320 may be deposited overlying the CMOS area 304 on the semiconductor substrate 302 covering the via 316 and overlying the metallization layer 318 on the chip 312.
  • the second insulation layer 320 may be selected from polymers including polyimide, parylene, silicones, oxides, nitrides, glass, quartz or their combination.
  • polymers including polyimide, parylene, silicones, oxides, nitrides, glass, quartz or their combination.
  • the metallization layer 318 may include multiple layers sandwiched between multiple insulating layers 320 connecting multiple devices and/or multiple chips on the substrate.
  • the packaging of the device may include aligning a rigid substrate 322 and bonding it to the substrate 302 by using an interfacial material 324.
  • the packaging substrate 322 may be selected from ceramics, thermoplastics, thermosets, glass, silicon, quartz, plastic or metals.
  • the bonding may be anodic, eutectic, solder, polymer or fusion bonding.
  • the interfacial material 324 may be selected from metal and/or alloys like gold, tin, epoxies like Benzocyclobuten (BCB) and SU8.
  • a secondary protective layer 326 may be applied overlying the rigid substrate 322.
  • the secondary protective layer 326 may be selected from polymers, oxides, nitrides, metals or a combination of them. A person of ordinary skill in this art will be able to easily make further alterations and modifications in packaging after reading the present invention.
  • FIG. 4 A second embodiment of a "Pre CMOS" monolithic hybrid integration approach is shown in Fig. 4.
  • the second embodiment may include micromachined micromechanical systems involving high temperature materials including but not limited to LPCVD oxide, nitride and polysilicon to effectively fabricate transducers including but not limited to accelerometers, resonators, micro-gyroscopes, microphones, micro-bolometers, etc.
  • a protective layer may be coated on the MEMS device area on the substrate to protect them from further fabrication steps that will be carried out on the same substrate. This protective layer protects the MEMS device area from the ensuing chemical etching.
  • CMOS electronics dies or any other MEMS/NEMS chips may be placed in a photolithographically etched trench with the help of a filler material and then connected to the already fabricated portion of the MEMS/NEMS device area with metallization evaporated or sputtered.
  • the CMOS or electronic dies also involve more sophisticated circuits including digital interfaces and micro controllers.
  • Processing can further resume on the MEMS device area by protecting the CMOS and or MEMS/NEMS chip areas and the MEMS/NEMS device area to realize a released structural layer and any other requirement depending on a specific application. It should be realized that a person of ordinary skill in this art will be able to make further alterations and modifications.
  • FIG. 4 illustrates a cross- sectional process flow for the "Pre CMOS" monolithic hybrid integration approach on a substrate 402.
  • a first step including providing a substrate 402 that may be a semi-conductor insulator as described above.
  • the substrate 402 may include MEMS/NEMS materials 404 applied thereon.
  • the MEMS/NEMS material 404 that can be made conductive include high temperature MEMS materials such as LPCVD polysilicon that can be later doped in boron or phosphorous and or may also include LPCVD nitride and or metals such as aluminum, copper, titanium, chrome, gold, silver, iridium or their combination that can be evaporated, sputtered or electroplated.
  • a first insulating layer 406 may be applied to the MEMS/NEMS materials 404.
  • a protective layer 408 may be applied to the semiconductor substrate 402 by either spin coating or depositing in vacuum to protect the MEMS/NEMS area 404 from further processing steps.
  • Protective layer 408 may be selected from oxides, nitrides, polymers, or their combination having a thickness of sub-microns to several microns and that which can effectively protect the electronics.
  • the protective layer 408 may be selectively patterned using lithography and etched anisotropically using oxygen plasma RIE for materials such as polyimide and parylene to define a trench 410 outside of the MEMS/NEMS area 404.
  • the trench 410 may be etched using DRIE Bosch process and may be lithographically defined by the size of chips 414.
  • the protective layer 408 may be left behind or removed.
  • a filler layer 412 may be deposited or dispensed into the trench 410 to anchor the chip 414 into the cavity and also to fill a gap between the chip 414 and the wall of the trench 410 and will also ensure the planarity of the chip 414 to the substrate 402.
  • the filler material 412 may be selected from oxides, polyimides, silicones, epoxies, or their combination or any other materials with similar properties.
  • CMOS integrated chip may include voltage comparators, diodes, op-amps, or other electronic components like power management circuits, resistors, capacitors, and inductors.
  • a MEMS/NEMS dies may include but are not limited to accelerometers, resonators, micro-gyroscopes, microphones, micro-bolometers, transducers involving chemical and biological, optical, mechanical, radiation, thermal, capacitive, rotation, strain, magnetic and electromagnetic, flow, and micro-fluidic chemical properties of liquids and gases
  • a second insulating layer 416 may be deposited covering the front face and/or the sides of the chip 414 providing the continuity from the semiconductor substrate 402 to the chip 414.
  • the second insulating layer 416 may be selected from polymers, oxides, nitrides, glass, quartz polyimide, parylene, silicone, or a combination of the above.
  • At least one via opening 418 may be etched through the second insulation layer 416 to make electrical contact.
  • the second insulation layer 416 may be anisotropically etched using oxygen plasma or may be etched using wet or dry etching.
  • a metallization layer 420 may be applied to connect the MEMS/NEMS on the semiconductor substrate 402 to the chip 414 which may include a contact area having an input/output pad or bond area to make electrical contact.
  • the metallization layer 420 may be selected from metals such as, aluminum, copper, titanium, chrome, gold, silver, iridium or their combination that can be evaporated, sputtered or electroplated.
  • a third insulating layer 422 may be deposited overlying the MEMS/NEMS on the semiconductor substrate 402 covering the via 418 and overlying the metallization layer 420 on the chip 414.
  • the third insulation layer 422 may be selected from polymers including polyimide, parylene, silicones, oxides, nitrides, glass, quartz or their combination.
  • polymers including polyimide, parylene, silicones, oxides, nitrides, glass, quartz or their combination.
  • the metallization layer 420 may include multiple layers sandwiched between multiple insulating layers 422 connecting multiple devices and/or multiple chips on the substrate.
  • Fig. 4g-l and Fig. 4g-2 there is shown a next step detailing a post micro/nano fabrication step after the integration to realize released mechanical structures 421.
  • the third insulation layer 422 may provide a protective layer for the ensuing fabrication.
  • the insulating layers are patterned and etched to create an opening 424 on the substrate 402.
  • the opening 424 may be formed by anisotropic etching.
  • the mechanical structural layers of the MEMS/NEMS 404 can be released using an isotropic etch forming a cavity 426.
  • the cavity 426 defines a sandwiched suspended structure 428.
  • the packaging of the device may include aligning a rigid substrate 430 and bonding it to the substrate 402 by using an interfacial material 432.
  • the packaging substrate 430 may be selected from ceramics, thermoplastics, thermosets, glass, silicon, quartz, plastic or metals.
  • the bonding may be anodic, eutectic, solder, polymer or fusion bonding.
  • the interfacial material 432 may be selected from metal and/or alloys like gold, tin, epoxies like Benzocyclobuten (BCB) and SU8.
  • a secondary protective layer 434 may be applied overlying the rigid substrate 430.
  • the secondary protective layer 434 may be selected from polymers, oxides, nitrides, metals or a combination of them. A person of ordinary skill in this art will be able to easily make further alterations and modifications in packaging after reading the present invention.
  • the third insulation layer 422 may provide a protective layer for the ensuing fabrication.
  • the backside of the substrate 402 is etched indicated by 436 and shown in Fig. 4h-l.
  • the insulating layers may be patterned and etched to create several openings 436 on the substrate 402.
  • the openings 436 may be formed by anisotropic etching.
  • the mechanical structural layers of the MEMS/NEMS 404 can be released using another anisotropic etch shown in Fig 4h-3, forming a free standing and or suspended structure 438.
  • the packaging of the device may include aligning a rigid substrate 430 and bonding it to the substrate 402 by using an interfacial material 432.
  • the packaging substrate 430 may be selected from ceramics, thermoplastics, thermosets, glass, silicon, quartz, plastic or metals.
  • the bonding may be anodic, eutectic, solder, polymer or fusion bonding.
  • the interfacial material 445 may be selected from metal and/or alloys like gold, tin, epoxies like Benzocyclobuten (BCB) and SU8.
  • a secondary protective layer 434 may be applied overlying the rigid substrate 430.
  • the secondary protective layer 434 may be selected from polymers, oxides, nitrides, metals or a combination of them. A person of ordinary skill in this art will be able to easily make further alterations and modifications in packaging after reading the present invention.

Abstract

A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contact area; applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one another contact area on the chip; applying a second insulating layer overlying the metallization layer on the at least one chip; applying at least one interfacial layer; applying at least one rigid substrate overlying the interfacial layer; and applying at least one secondary protective layer overlying the rigid substrate.

Description

METHOD OF FORMING MONOLITHIC CMOS-MEMS HYBRID
INTEGRATED, PACKAGED STRUCTURES
REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority to United States Patent Application Serial No. 12/497,107 filed July 2, 2009, the contents of which is incorporated herein by reference.
FIELD OF THE INVENTION
[0002] The invention relates to a method for integrating MEMS and CMOS structures.
BACKGROUND OF THE INVENTION
[0003] Monolithic integration of MEMS/NEMS and electronics offers significant benefits enabling high volume production driving down the per-unit costs of sensor and actuator systems significantly. Micromechanical transducer systems not only need to receive analog and digital electrical inputs and transmit the output, but should also be able to measure rotation, strain, temperature, pressure, acceleration, infrared radiation, micro fluidic chemical properties of liquids and gasses. Effective integration offers other benefits, including, simplifying interconnect issues, reduced packaging and fabrication complexity and significantly improving the overall performance and ease of use for the device.
[0004] One method of monolithic integration of CMOS and MEMS is to modify the complementary metal-oxide semiconductor (CMOS) foundry facility to fabricate micromechanical structures. Some of the commonly used micromechanical (MEMS) mechanical structures like polysilicon, nitride etc require high-temperature processing during deposition and annealing to relieve stress and this cannot be performed on the same substrate in the presence of CMOS electronics due to the lower temperature limitation of the metals in CMOS. Another limitation of the method is that CMOS requires the substrate to be planar after the MEMS fabrication to achieve high-resolution features in the photolithographic process. Thus, the current CMOS-MEMS integration methodologies faces serious limitations, requiring sacrificing materials and allowing very little flexibility in device design.
[0005] Monolithic integration process may be divided into three classes: (1) Pre CMOS (2) Intermediate CMOS (3) Post CMOS. In prior art "pre CMOS" fabrication process methods, MEMS/NEMS structures are fabricated before the electronics are integrated. One example of this process is the micromechanics-first approach developed at Sandia National Laboratory by J. Smith et al. In this process a pre-etched trench is used to house the MEMS structures. After the fabrication of the desired MEMS structures, this housing is refilled with oxide, planarized using chemical- mechanical polishing (CMP), and finally sealed with a nitride membrane. Conventional CMOS processing was then carried out next to this MEMS area. This defined a CMOS device area and micromechanical device area on the same substrate as shown in Fig. 1. One of the disadvantages with this process is that it needs a dedicated production line and the process is complicated.
[0006] In the Intermediate CMOS fabrication process, the process flow between CMOS and MEMS is mixed in the sequence. Initially a part of the CMOS process is performed and then paused for additional thin film deposition or micromachining steps. Some of the commercially available sensors in this art include the Analog Devices integrated MEMS and Infineon' s pressure sensor shown by C.Hierold. In the post CMOS process, MEMS/NEMS structures are fabricated after the CMOS or electronics is fabricated on the substrate. The disadvantage of this process is the temperature limitation of the process to below 4000C to protect the aluminum in the electronics. This leads to the elimination of commonly used MEMS/NEMS high temperature materials like LPCVD polysilicon, silicon nitride etc.
[0007] An alternative approach to integration and packaging using high density interconnect (HDI) multichip modules (MCMs) was developed by researchers at GE Corporate Research and Development center as a "chips first" approach described in by W. Daum et al. as shown in Figure 2. This process involves placing bare chips of MEMS test die and a generic CMOS electronics die into mechanically milled cavities on a base substrate and then fabricating the thin-film interconnect structure on top of the components. A computer-controlled argon ion laser system drills via holes through the polyimide film directly to the chip I/O pads. The interconnection metallization and via contacts were formed by a combined sputtering/electroplating process and patterned by computer- controlled adaptive laser lithography and etching. Some of the limitations with this process were the warping of the MEMS device due to excessive heating during the laser ablation step.
[0008] Prior art monolithic integration processes in this art involve utilizing complimentary metal-oxide semiconductor (CMOS) semiconductor layers to fabricate micromechanical structures is shown in US Patent 5717631, US Patent Application No: 11/602,087, US Patent No: 6060336. Some of the major limitations with this approach involve the need to sacrifice MEMS/NEMS materials with various mechanical properties as commercial foundries cannot modify their processes to suit MEMS/NEMS. This also adds additional constraints when fabricating the MEMS/NEMS sensors or actuators as they would need to limit their processing techniques like etching, deposition so as to not harm the electronic circuits present on the substrate. Stress and other mechanical deficiencies may lead to device failure when the materials tailored to CMOS are modified as mechanical elements in MEMS.
[0009] Prior art hybrid MCM technology processes include putting one or several dies with different functionality into prefabricated trenches on a substrate, planarizing these chips, providing an insulator layer on top and forming electrodes have been demonstrated in US Patent: 6403463, US Patent No:6780696 Bl, US Patent 6154366 , US Patent No.:6,759,270. Some of the major drawbacks in these prior art references include semiconductor substrates like silicon that are fragile and the devices need to be repackaged resulting in significant costs.
[0010] The invention describes a method of manufacture for Monolithic hybrid integration of CMOS-MEMS with enhanced flexibility of using materials without hindrance to process parameters. This invention enables this integration effectively without the need to sacrifice the inherent strengths of both the CMOS or MEMS technologies and bringing about their fusion in a hybrid approach on a common substrate. This invention also allows the ability to effectively package the entire system after integration.
[0011] Several of the limitations mentioned above are overcome in the present invention which describes a method to effectively synergize CMOS-MEMS/NEMS functionality and finally package them creating a very cost effective, reliable, robust transduction system In the present invention, protective layers are coated on the substrate to protect either the CMOS device area in the "Post CMOS" process or the MEMS device area in the "Pre CMOS" process to prevent damage to the sensor or electronics. Oxygen plasma etching can be used to open the vias to access conductive layers, being precisely defined by photolithography instead of laser which is known to cause damage in some of the previous integration approaches.
[0012] Either the "Post CMOS" or "Pre CMOS" fabrication may be carried out on a semiconductor substrate without compromising on the individual technologies strength and then integrating CMOS if MEMS is already present or MEMS if CMOS is already present on the same substrate.
[0013] The invention provides an improved ability to effectively package an entire system using a glass, silicon, plastic or metal housing. Packaging provides physical protection against external scratching and breakage, environmental protection and any other external forces that may damage the leads or the sensors. Effective packaging of the integrated system leads to lower cost, improved reliability and improved performance. This invention addresses some of the important issues present in current packaging methodologies. As one specific example related to reliability issues with plastic packages, the Thermal coefficient of expansion (TCE) mismatch resulting from the curing of the resins as they shrink in volume, creates a large temperature differential resulting in large strain mismatch, damaging the wire bonds. This issue can be eliminated or reduced significantly in the present invention as there will be no wire bonds involved and the fabrication is planar and the metal traces can be more effectively protected. The packaging methodology from the current invention also eliminates the need for solder bumps for integration of CMOS-MEMS and packaging. The invention also provides a method to further encapsulate the entire system by adding a secondary protective layer of organic materials providing a very effective packaging methodology. SUMMARY OF THE INVENTION
[0014] Accordingly, the invention relates to a method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures. In one aspect, the method includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contact area; applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one another contact area on the chip; applying a second insulating layer overlying the metallization layer on the at least one chip; applying at least one interfacial layer; applying at least one rigid substrate overlying the interfacial layer; and applying at least one secondary protective layer overlying the rigid substrate.
[0015] In another aspect, the method includes the steps of: providing a semiconductor substrate having MEMS/NEMS materials including mechanical structural layers and conductive layers; applying a first insulating layer overlying the MEMS/NEMS materials; applying at least one protective layer overlying the MEM/NEMS materials; forming at least one opening on the protective layer to access the semiconductor substrate; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a front face and a bare backside; applying a second insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contact area; applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one another contact area on the chip; applying a third insulating layer overlying the metallization layer on the at least one chip; performing at least one post micro/nano fabrication etching step; applying at least one interfacial layer; applying at least one rigid substrate overlying the interfacial layer; and applying at least one secondary protective layer overlying the rigid substrate. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Fig. 1 Prior Art showing cross-section of the embedded micromechanics approach to
CMOS/MEMS integration from Sandia National labs;
[0017] Fig. 2 Prior Art showing simplified cross-sectional view of HDI interconnect MCM technology from GE;
[0018] Fig. 3a-3h is a cross-sectional view showing the process flow for building a "post
CMOS" monolithic CMOS-MEMS hybrid integration system and packaging;
[0019] Fig. 4a-Fig.4f is a cross- sectional view showing the process flow for building a "pre
CMOS" monolithic CMOS-MEMS hybrid integration system;
[0020] Fig. 4(gl-g4) is a cross-sectional view showing the post fabrication of the integrated CMOS MEMS realizing a suspended structure using isotropic etching and finally packaged;
[0021] Fig. 4(hl-h5) is a cross-sectional view showing the post fabrication of the integrated
CMOS MEMS realizing anisotropic etching in the front and backside and finally packaged.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0022] Referring to the various Figures there is shown an effective, reliable, and relatively low cost method of integration between CMOS-MEMS/NEMS.
[0023] In one embodiment of a "post CMOS" or "CMOS first" hybrid integration approach shown in Figs 3a-3h, the already fabricated CMOS semiconductor substrate is modified to achieve this integration. The CMOS device area is first protected so as not to affect their functionality in the ensuing process; fabrication is continued on the same substrate and integrated by coupling the micromechanical structures in a hybrid approach by placing the MEMS/NEMS dies that have been diced. The integrated system is finally packaged in an effective manner. [0024] Again referring to Figures 3a-h, there is shown a cross-sectional process flow for the "Post CMOS" monolithic hybrid integration approach on a semiconductor substrate 302. A CMOS fabricated semiconductor substrate 302 with dielectric layers and metallization in Fig. 3a is provided as a starting point in the integration process. The CMOS device area 304may include digital logic circuits, operational amplifiers, inverters, analog and digital circuitry, digital switches, voltage comparators which enable the sensors and actuators to receive analog and digital signals for their effective operation.
[0025] Next, as shown in Fig. 3b, a protective layer 306 may be applied to the CMOS semiconductor substrate 302 by either spin coated or deposited in vacuum to protect the CMOS area 304 from further processing steps. Protective layer 306 may be selected from oxides, nitrides, polymers, or their combination having a thickness of sub-microns to several microns and that which can effectively protect the electronics. The protective layer 306 may be selectively patterned using lithography and etched anisotropically using oxygen plasma RIE for materials such as polyimide and parylene to define a trench 308 outside of the CMOS device area 304. The trench 308 may be etched using DRIE Bosch process and may be lithographically defined by the size of a chip 312. The protective layer 306 may be left behind or removed.
[0026] In a following step, as shown in Fig. 3c, a filler layer 310 may be deposited or dispensed into the trench 308 to anchor a chip 312 into the trench 308 and also to fill a gap between the chip 312 and the wall of the trench 308 and will also ensure the planarity of the chip 312 to the substrate 302. The filler material 310 may be selected from oxides, polyimides, silicones, epoxiess, or their combination or any other materials with similar properties.
[0027] In a next step as shown in Fig. 3d, the chip 312 of CMOS, MEMS/NEMS or a combination of them may be placed in the trench 308. As described above, a CMOS integrated chip may include voltage comparators, diodes, op-amps, or other electronic components like power management circuits, resistors, capacitors, and inductors. A MEMS/NEMS dies may include but are not limited to accelerometers, resonators, micro-gyroscopes, microphones, micro-bolometers, transducers involving chemical and biological, optical, mechanical, radiation, thermal, capacitive, rotation, strain, magnetic and electromagnetic, flow, and micro-fluidic chemical properties of liquids and gases.
[0028] In a following step as shown in Fig. 3e, a first insulating layer 314 may be deposited covering the front face and/or the sides of the chip 312 providing the continuity from the semiconductor substrate 302 to the chip 312. The first insulating layer 314 may be selected from polymers, oxides, nitrides, glass, quartz polyimide, parylene, silicone, or a combination of the above. At least one via opening 316 may be etched through the first insulation layer 314 to make electrical contact. The first insulation layer 314 may be anisotropically etched using oxygen plasma or may be etched using wet or dry etching.
[0029] In a next step as shown in Fig. 3f, a metallization layer 318 may be applied to connect the CMOS area 304 on the semiconductor substrate 302 to the chip 312 which may include a contact area having an input/output pad or bond area to make electrical contact. The metallization layer 318 may be selected from metals such as, aluminum, copper, titanium, chrome, gold, silver, iridium or their combination that can be evaporated, sputtered or electroplated. A second insulating layer 320 may be deposited overlying the CMOS area 304 on the semiconductor substrate 302 covering the via 316 and overlying the metallization layer 318 on the chip 312. The second insulation layer 320 may be selected from polymers including polyimide, parylene, silicones, oxides, nitrides, glass, quartz or their combination. A person of ordinary skill in this art will be able to easily make further alterations and modifications in packaging after reading the present invention. It can easily be inferred that any particular embodiment illustrated with diagrams and explained cannot be considered limiting. For example the metallization layer 318 may include multiple layers sandwiched between multiple insulating layers 320 connecting multiple devices and/or multiple chips on the substrate.
[0030] In a next step as shown in Fig. 3g, the packaging of the integrated device is detailed. The packaging of the device may include aligning a rigid substrate 322 and bonding it to the substrate 302 by using an interfacial material 324. The packaging substrate 322 may be selected from ceramics, thermoplastics, thermosets, glass, silicon, quartz, plastic or metals. The bonding may be anodic, eutectic, solder, polymer or fusion bonding. The interfacial material 324 may be selected from metal and/or alloys like gold, tin, epoxies like Benzocyclobuten (BCB) and SU8.
[0031] In a subsequent step as shown in Fig. 3h, a secondary protective layer 326 may be applied overlying the rigid substrate 322. The secondary protective layer 326 may be selected from polymers, oxides, nitrides, metals or a combination of them. A person of ordinary skill in this art will be able to easily make further alterations and modifications in packaging after reading the present invention.
[0032] A second embodiment of a "Pre CMOS" monolithic hybrid integration approach is shown in Fig. 4. The second embodiment may include micromachined micromechanical systems involving high temperature materials including but not limited to LPCVD oxide, nitride and polysilicon to effectively fabricate transducers including but not limited to accelerometers, resonators, micro-gyroscopes, microphones, micro-bolometers, etc. A protective layer may be coated on the MEMS device area on the substrate to protect them from further fabrication steps that will be carried out on the same substrate. This protective layer protects the MEMS device area from the ensuing chemical etching. The CMOS electronics dies or any other MEMS/NEMS chips may be placed in a photolithographically etched trench with the help of a filler material and then connected to the already fabricated portion of the MEMS/NEMS device area with metallization evaporated or sputtered. The CMOS or electronic dies also involve more sophisticated circuits including digital interfaces and micro controllers. Thus the temperature limitation of the process to below 4000C to protect the aluminum in the electronics, which has been the limiting step in some of the current integration methodologies, can now be overcome with the present invention with the potential to realize several novel devices. Processing can further resume on the MEMS device area by protecting the CMOS and or MEMS/NEMS chip areas and the MEMS/NEMS device area to realize a released structural layer and any other requirement depending on a specific application. It should be realized that a person of ordinary skill in this art will be able to make further alterations and modifications.
[0033] Fig. 4 illustrates a cross- sectional process flow for the "Pre CMOS" monolithic hybrid integration approach on a substrate 402.
[0034] Referring to Fig. 4a there is shown a first step including providing a substrate 402 that may be a semi-conductor insulator as described above. The substrate 402 may include MEMS/NEMS materials 404 applied thereon. In one aspect, the MEMS/NEMS material 404 that can be made conductive include high temperature MEMS materials such as LPCVD polysilicon that can be later doped in boron or phosphorous and or may also include LPCVD nitride and or metals such as aluminum, copper, titanium, chrome, gold, silver, iridium or their combination that can be evaporated, sputtered or electroplated. In the illustrated embodiment, a first insulating layer 406 may be applied to the MEMS/NEMS materials 404.
[0035] Next, as shown in Fig. 4b, a protective layer 408 may be applied to the semiconductor substrate 402 by either spin coating or depositing in vacuum to protect the MEMS/NEMS area 404 from further processing steps. Protective layer 408 may be selected from oxides, nitrides, polymers, or their combination having a thickness of sub-microns to several microns and that which can effectively protect the electronics. The protective layer 408 may be selectively patterned using lithography and etched anisotropically using oxygen plasma RIE for materials such as polyimide and parylene to define a trench 410 outside of the MEMS/NEMS area 404. The trench 410 may be etched using DRIE Bosch process and may be lithographically defined by the size of chips 414. The protective layer 408 may be left behind or removed. [0036] In a following step, as shown in Fig. 4c, a filler layer 412 may be deposited or dispensed into the trench 410 to anchor the chip 414 into the cavity and also to fill a gap between the chip 414 and the wall of the trench 410 and will also ensure the planarity of the chip 414 to the substrate 402. The filler material 412 may be selected from oxides, polyimides, silicones, epoxies, or their combination or any other materials with similar properties.
[0037] In a next step as shown in Fig. 4d, the chip 414 of CMOS, MEMS/NEMS or a combination of them may be placed in the trench 410. As described above, a CMOS integrated chip may include voltage comparators, diodes, op-amps, or other electronic components like power management circuits, resistors, capacitors, and inductors. A MEMS/NEMS dies may include but are not limited to accelerometers, resonators, micro-gyroscopes, microphones, micro-bolometers, transducers involving chemical and biological, optical, mechanical, radiation, thermal, capacitive, rotation, strain, magnetic and electromagnetic, flow, and micro-fluidic chemical properties of liquids and gases
[0038] In a following step as shown in Fig. 4e, a second insulating layer 416 may be deposited covering the front face and/or the sides of the chip 414 providing the continuity from the semiconductor substrate 402 to the chip 414. The second insulating layer 416 may be selected from polymers, oxides, nitrides, glass, quartz polyimide, parylene, silicone, or a combination of the above. At least one via opening 418 may be etched through the second insulation layer 416 to make electrical contact. The second insulation layer 416 may be anisotropically etched using oxygen plasma or may be etched using wet or dry etching.
[0039] In a next step as shown in Fig. 4f, a metallization layer 420 may be applied to connect the MEMS/NEMS on the semiconductor substrate 402 to the chip 414 which may include a contact area having an input/output pad or bond area to make electrical contact. The metallization layer 420 may be selected from metals such as, aluminum, copper, titanium, chrome, gold, silver, iridium or their combination that can be evaporated, sputtered or electroplated. A third insulating layer 422 may be deposited overlying the MEMS/NEMS on the semiconductor substrate 402 covering the via 418 and overlying the metallization layer 420 on the chip 414. The third insulation layer 422 may be selected from polymers including polyimide, parylene, silicones, oxides, nitrides, glass, quartz or their combination. A person of ordinary skill in this art will be able to easily make further alterations and modifications in packaging after reading the present invention. It can easily be inferred that any particular embodiment illustrated with diagrams and explained cannot be considered limiting. For example the metallization layer 420 may include multiple layers sandwiched between multiple insulating layers 422 connecting multiple devices and/or multiple chips on the substrate.
[0040] Referring to Fig. 4g-l and Fig. 4g-2 there is shown a next step detailing a post micro/nano fabrication step after the integration to realize released mechanical structures 421. The third insulation layer 422 may provide a protective layer for the ensuing fabrication. In the detailed embodiment the insulating layers are patterned and etched to create an opening 424 on the substrate 402. The opening 424 may be formed by anisotropic etching. The mechanical structural layers of the MEMS/NEMS 404 can be released using an isotropic etch forming a cavity 426. The cavity 426 defines a sandwiched suspended structure 428.
[0041] In a next step as shown in Figure 4g-3, the packaging of the integrated device is detailed. The packaging of the device may include aligning a rigid substrate 430 and bonding it to the substrate 402 by using an interfacial material 432. The packaging substrate 430 may be selected from ceramics, thermoplastics, thermosets, glass, silicon, quartz, plastic or metals. The bonding may be anodic, eutectic, solder, polymer or fusion bonding. The interfacial material 432 may be selected from metal and/or alloys like gold, tin, epoxies like Benzocyclobuten (BCB) and SU8.
[0042] In a subsequent step as shown in Fig. 4g-4, a secondary protective layer 434 may be applied overlying the rigid substrate 430. The secondary protective layer 434 may be selected from polymers, oxides, nitrides, metals or a combination of them. A person of ordinary skill in this art will be able to easily make further alterations and modifications in packaging after reading the present invention.
[0043] Referring to Fig. 4h-l to Fig. 4h-3 there is shown an alternative embodiment of the post micro/nano fabrication step after the integration to realize released mechanical structures. The third insulation layer 422 may provide a protective layer for the ensuing fabrication. In the detailed embodiment, the backside of the substrate 402 is etched indicated by 436 and shown in Fig. 4h-l. In the ensuing fabrication the insulating layers may be patterned and etched to create several openings 436 on the substrate 402. The openings 436 may be formed by anisotropic etching. The mechanical structural layers of the MEMS/NEMS 404 can be released using another anisotropic etch shown in Fig 4h-3, forming a free standing and or suspended structure 438.
[0044] In a next step as shown in Figure 4h-4, the packaging of the integrated device is detailed. The packaging of the device may include aligning a rigid substrate 430 and bonding it to the substrate 402 by using an interfacial material 432. The packaging substrate 430 may be selected from ceramics, thermoplastics, thermosets, glass, silicon, quartz, plastic or metals. The bonding may be anodic, eutectic, solder, polymer or fusion bonding. The interfacial material 445 may be selected from metal and/or alloys like gold, tin, epoxies like Benzocyclobuten (BCB) and SU8.
[0045] In a subsequent step as shown in Fig. 4h-5, a secondary protective layer 434 may be applied overlying the rigid substrate 430. The secondary protective layer 434 may be selected from polymers, oxides, nitrides, metals or a combination of them. A person of ordinary skill in this art will be able to easily make further alterations and modifications in packaging after reading the present invention.
[0046] While the above examples provide a description of the process of the present invention, they should not be read as limiting the process of the present invention. The invention has been described in an illustrative manner. It is to be understood that the terminology which has been used is intended to be in the nature of words of description rather than limitation. Many modifications and variations of the invention are possible in light of the above teachings. Therefore, within the scope of the appended claims, the invention may be practiced other than as specifically described.

Claims

1. A method of forming Monolithic CMOS -MEMS hybrid integrated, packaged structure comprising the steps of:
providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers;
applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate;
forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers;
applying at least one filler layer in the at least one opening on the semiconductor substrate;
positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside;
applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip;
forming at least one via opening on the insulating layer covering the chip to access at least one contact area;
applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one another contact area on the chip;
applying a second insulating layer overlying the metallization layer on the at least one chip;
applying at least one interfacial layer;
applying at least one rigid substrate overlying the interfacial layer;
applying at least one secondary protective layer overlying the rigid substrate.
2. The method of claim 1, wherein the CMOS device area includes pre-fabricated structures selected from: multi level poly, multi level metal with digital logic circuits, operational amplifiers, inverters, analog and digital circuitry, digital switches, and voltage comparators.
3. The method of claim 1, wherein the protective layer is selected from variable temperature polymers including polyimide and parylene and lithographically patternable materials including photoresist materials.
4. The method of claim 1, wherein the step of forming an opening of the protective layer includes patterning the dielectric and metallization layers on the substrate material to create access to the semiconductor.
5. The method of claim 4, wherein the patterning includes photolithographically defining open areas and then etching.
6. The method of claim 5 wherein the etching is selected from: wet, dry, isotropic, and anisotropic etching.
7. The method of claim 1, wherein the filler material is selected from: polyimide, silicone, epoxy or their combination.
8. The method of claim 1, wherein the chip is selected from: commercial CMOS integrated circuits, electronics or diced chips from another MEMS/NEMS fabrication process.
9. The method of claim 8, wherein the CMOS integrated circuits are selected from: voltage comparators, diodes, op-amps, power management circuits, resistors, capacitors, and inductors.
10. The method of claim 8, wherein MEMS/NEMS chips include transducers selected from chemical and biological, optical, mechanical, radiation, thermal, capacitive, magnetic and electromagnetic, flow, and micro-fluidic transducers
11. The method of claiml, wherein the first insulation layer covering the chip and the substrate is selected from oxides, nitrides, glass, quartz, and polymers.
12. The method of claim 1, wherein the metallization layer is selected from aluminum, titanium, chrome, gold, platinum or a combination of the same that can be evaporated, sputtered or electroplated.
13. The method of claim 1, wherein the second insulating layer overlying the metallization layer is selected from oxides, nitrides, glass, quartz, and polymers.
14. The method of claim 1, wherein the interfacial material is selected from metals including gold, and tin, alloys, and epoxy including Benzocyclobuten (BCB) and SU8 photoresist.
15. The method of claim 1, wherein the at least one rigid substrate overlying the interfacial layer is selected from ceramics, thermoplastics, thermosets, glass, silicon, quartz, plastic and metal.
16. The method of claim 1, wherein the secondary protective layer overlying the rigid substrate is selected from organic encapsulation including nonelastomeric thermoplastics including parylene, thermosetting polymers including silicones, polymides, and epoxies, metals or their combination.
17. A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged device comprising the steps of:
providing a semiconductor substrate having MEMS/NEMS materials including mechanical structural layers and conductive layers;
applying a first insulating layer overlying the MEMS/NEMS materials; applying at least one protective layer overlying the MEM/NEMS materials;
forming at least one opening on the protective layer to access the semiconductor substrate;
applying at least one filler layer in the at least one opening on the semiconductor substrate;
positioning at least one chip on the filler layer, the chip including a front face and a bare backside;
applying a second insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip;
forming at least one via opening on the insulating layer covering the chip to access at least one contact area;
applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one contact area on the chip;
applying a third insulating layer overlying the metallization layer on the at least one chip; performing at least one post micro/nano fabrication etching step forming a released structure;
applying at least one interfacial layer;
applying at least one rigid substrate overlying the interfacial layer;
applying at least one secondary protective layer overlying the rigid substrate.
18. The method of claim 17, wherein the first insulating layer includes materials selected from LPCVD deposited materials including oxides and nitrides, polymers including parylene and polyimide, glass, and quartz.
19. The method of claim 17, wherein the mechanical structural layer is selected from LPCVD deposited materials, polymer, metal, and single crystal silicon.
20. The method of claim 19, wherein the LPCVD deposited materials is selected from oxides, nitrides, and polysilicon.
21. The method of claim 20, wherein conductive layer is selected from materials doped with boron or phosphorous, polysilicon, single crystal silicon, aluminum, copper, titanium, chrome, gold, silver, or their combination.
22. The method of claim 19, wherein the polymer is selected from parylene, polyimide and silicone.
23. The method of claim 19, wherein the metal is selected from aluminum, titanium, chrome, gold, platinum or a combination of the same that can be evaporated, sputtered or electroplated.
24. The method of claim 17 wherein the protective layer is selected from variable temperature polymers including polyimide and parylene and lithographically patternable materials including photoresist materials.
25. The method of claim 17, wherein the step of forming an opening of the protective layer includes patterning the dielectric and metallization layers on the substrate material to create access to the semiconductor.
26. The method of claim 25, wherein the patterning includes photolithographically defining open areas and then etching.
27. The method of claim 26 wherein the etching is selected from: wet, dry, isotropic, and anisotropic etching.
28. The method of claim 17, wherein the filler material is selected from: polyimide, silicone, epoxy or their combination.
29. The method of claim 17, wherein the chip is selected from: commercial CMOS integrated circuits, electronics or diced chips from another MEMS/NEMS fabrication process.
30. The method of claim 29, wherein the CMOS integrated circuits are selected from: voltage comparators, diodes, op-amps, power management circuits, resistors, capacitors, and inductors.
31. The method of claim 29, wherein MEMS/NEMS chips include transducers selected from chemical and biological, optical, mechanical, radiation, thermal, capacitive, magnetic and electromagnetic, flow, and micro-fluidic transducers
32. The method of claim 17, wherein third insulation layer covering the chip and the substrate comprises materials selected from polymers, oxide, nitride, glass quartz.
layer covering the chip and the substrate is selected from oxides, nitrides, glass, quartz, and polymers.
33. The method of claim 17, wherein the metallization layer is selected from aluminum, titanium, chrome, gold, platinum or a combination of the same that can be evaporated, sputtered or electroplated.
34. The method of claim 17, wherein the second insulating layer overlying the chip is selected from oxides, nitrides, glass, quartz, and polymers.
35. The method of claim 17, wherein the third insulating layer overlying the metallization layer is selected from oxides, nitrides, glass, quartz, and polymers.
36. The method of claim 35, wherein the polymers are selected from parylene, and polyimide.
37. The method of claim 17, wherein the micro/nano fabrication etching step is selected from wet, dry, isotropic, and anisotropic etching.
38. The method of claim 17, wherein the micro/nano fabrication etching further comprises surface micromachining, bulk micromachining, dry etching, and chemical etching from a backside of the substrate.
39. The method of claim 17, wherein the interfacial material is selected from metals including gold, and tin, alloys, and epoxy including Benzocyclobuten (BCB) and SU8 photoresist.
40. The method of claim 17, wherein the at least one rigid substrate overlying the interfacial layer is selected from ceramics, thermoplastics, thermosets, glass, silicon, quartz, plastic and metal.
PCT/US2010/040890 2009-07-02 2010-07-02 Method of forming monolithic cmos-mems hybrid integrated, packaged structures WO2011003057A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/497,107 US7989248B2 (en) 2009-07-02 2009-07-02 Method of forming monolithic CMOS-MEMS hybrid integrated, packaged structures
US12/497,107 2009-07-02

Publications (2)

Publication Number Publication Date
WO2011003057A2 true WO2011003057A2 (en) 2011-01-06
WO2011003057A3 WO2011003057A3 (en) 2011-04-14

Family

ID=43411773

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2010/040890 WO2011003057A2 (en) 2009-07-02 2010-07-02 Method of forming monolithic cmos-mems hybrid integrated, packaged structures

Country Status (2)

Country Link
US (1) US7989248B2 (en)
WO (1) WO2011003057A2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160076512A (en) * 2014-04-25 2016-06-30 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Semiconductor arrangement and formation thereof
EP4241750A2 (en) 2014-12-05 2023-09-13 Egg Medical, Inc. A multimodality medical procedure mattress-based device

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8878312B2 (en) * 2011-03-01 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Electrical bypass structure for MEMS device
US9254992B2 (en) * 2012-07-27 2016-02-09 Tao Ju Method of making a MEMS gyroscope having a magnetic source and a magnetic sensing mechanism
ITTO20120827A1 (en) * 2012-09-24 2014-03-25 St Microelectronics Srl INSULATION AT SLICE LEVEL OF AN INTEGRATED MEMS DEVICE AND ITS MANUFACTURING PROCEDURE
KR102007258B1 (en) * 2012-11-21 2019-08-05 삼성전자주식회사 Method of fabricating optoelectronic substrate
FR3008690B1 (en) * 2013-07-22 2016-12-23 Commissariat Energie Atomique DEVICE COMPRISING A FLUID CHANNEL PROVIDED WITH AT LEAST ONE MICRO OR NANOELECTRONIC SYSTEM AND METHOD OF MAKING SUCH A DEVICE
EP3920200A1 (en) * 2014-05-05 2021-12-08 3D Glass Solutions, Inc. 2d and 3d inductors antenna and transformers fabricating photoactive substrates
US10070533B2 (en) 2015-09-30 2018-09-04 3D Glass Solutions, Inc. Photo-definable glass with integrated electronics and ground plane
KR20180134868A (en) 2016-02-25 2018-12-19 3디 글래스 솔루션즈 인코포레이티드 A photoactive substrate for fabricating 3D capacitors and capacitor arrays
US11161773B2 (en) 2016-04-08 2021-11-02 3D Glass Solutions, Inc. Methods of fabricating photosensitive substrates suitable for optical coupler
US10556791B2 (en) * 2016-07-19 2020-02-11 King Abdulaziz City For Science And Technology CMOS compatible capacitive absolute pressure sensors
US11101532B2 (en) 2017-04-28 2021-08-24 3D Glass Solutions, Inc. RF circulator
JP6995891B2 (en) 2017-07-07 2022-01-17 スリーディー グラス ソリューションズ，インク 2D and 3D RF centralized device for RF systems in packaged photoactive glass substrates
US10312185B2 (en) * 2017-10-05 2019-06-04 Texas Instrument Incorporated Inductively coupled microelectromechanical system resonator
EP3724946B1 (en) 2017-12-15 2024-04-17 3D Glass Solutions, Inc. Coupled transmission line resonate rf filter
CA3082624C (en) 2018-01-04 2022-12-06 3D Glass Solutions, Inc. Impedance matching conductive structure for high efficiency rf circuits
US11076489B2 (en) 2018-04-10 2021-07-27 3D Glass Solutions, Inc. RF integrated power condition capacitor
CA3071138C (en) 2018-05-29 2021-05-25 3D Glass Solutions, Inc. Low insertion loss rf transmission line
AU2019344542B2 (en) 2018-09-17 2022-02-24 3D Glass Solutions, Inc. High efficiency compact slotted antenna with a ground plane
KR102392858B1 (en) 2018-12-28 2022-05-03 3디 글래스 솔루션즈 인코포레이티드 Toroidal Capacitor RF, Microwave, and Mm Wave Systems
KR102493538B1 (en) 2018-12-28 2023-02-06 3디 글래스 솔루션즈 인코포레이티드 Heterogenous integration for rf, microwave and mm wave systems in photoactive glass substrates
KR102601781B1 (en) 2019-04-18 2023-11-14 3디 글래스 솔루션즈 인코포레이티드 High efficiency die dicing and release
US11908617B2 (en) 2020-04-17 2024-02-20 3D Glass Solutions, Inc. Broadband induction

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6012336A (en) * 1995-09-06 2000-01-11 Sandia Corporation Capacitance pressure sensor
JP2001185635A (en) * 1999-10-15 2001-07-06 Lucent Technol Inc Package having cavity for housing mems
EP1808405A2 (en) * 2006-01-13 2007-07-18 Honeywell International Inc. Integrated package for MEMS die and IC chip
US20070224832A1 (en) * 2006-03-21 2007-09-27 Peter Zurcher Method for forming and sealing a cavity for an integrated MEMS device
KR20090031360A (en) * 2006-07-15 2009-03-25 쇼오트 아게 Method for encasing electronic components and integrated circuits

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5717631A (en) * 1995-07-21 1998-02-10 Carnegie Mellon University Microelectromechanical structure and process of making same
JP3214470B2 (en) * 1998-11-16 2001-10-02 日本電気株式会社 Multi-chip module and manufacturing method thereof
US6060336A (en) * 1998-12-11 2000-05-09 C.F. Wan Incorporated Micro-electro mechanical device made from mono-crystalline silicon and method of manufacture therefore
US6154366A (en) * 1999-11-23 2000-11-28 Intel Corporation Structures and processes for fabricating moisture resistant chip-on-flex packages
US6555906B2 (en) * 2000-12-15 2003-04-29 Intel Corporation Microelectronic package having a bumpless laminated interconnection layer
US6808955B2 (en) * 2001-11-02 2004-10-26 Intel Corporation Method of fabricating an integrated circuit that seals a MEMS device within a cavity
US6756662B2 (en) * 2002-09-25 2004-06-29 International Business Machines Corporation Semiconductor chip module and method of manufacture of same
US20040157426A1 (en) * 2003-02-07 2004-08-12 Luc Ouellet Fabrication of advanced silicon-based MEMS devices
TWI293787B (en) * 2004-11-12 2008-02-21 Nat Applied Res Lab Nat Chip Implementation Ct Cmos-mems process
US7875484B2 (en) * 2006-11-20 2011-01-25 Alces Technology, Inc. Monolithic IC and MEMS microfabrication process
US7736929B1 (en) * 2007-03-09 2010-06-15 Silicon Clocks, Inc. Thin film microshells incorporating a getter layer
US7863071B1 (en) * 2007-08-21 2011-01-04 Rf Micro Devices, Inc. Combined micro-electro-mechanical systems device and integrated circuit on a silicon-on-insulator wafer
FR2932790B1 (en) * 2008-06-23 2010-08-20 Commissariat Energie Atomique METHOD FOR MANUFACTURING AN ELECTROMECHANICAL DEVICE COMPRISING AT LEAST ONE ACTIVE ELEMENT

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6012336A (en) * 1995-09-06 2000-01-11 Sandia Corporation Capacitance pressure sensor
JP2001185635A (en) * 1999-10-15 2001-07-06 Lucent Technol Inc Package having cavity for housing mems
EP1808405A2 (en) * 2006-01-13 2007-07-18 Honeywell International Inc. Integrated package for MEMS die and IC chip
US20070224832A1 (en) * 2006-03-21 2007-09-27 Peter Zurcher Method for forming and sealing a cavity for an integrated MEMS device
KR20090031360A (en) * 2006-07-15 2009-03-25 쇼오트 아게 Method for encasing electronic components and integrated circuits

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160076512A (en) * 2014-04-25 2016-06-30 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Semiconductor arrangement and formation thereof
KR101714324B1 (en) 2014-04-25 2017-03-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Semiconductor arrangement and formation thereof
EP4241750A2 (en) 2014-12-05 2023-09-13 Egg Medical, Inc. A multimodality medical procedure mattress-based device

Also Published As

Publication number Publication date
WO2011003057A3 (en) 2011-04-14
US7989248B2 (en) 2011-08-02
US20110003422A1 (en) 2011-01-06

Similar Documents

Publication Publication Date Title
US7989248B2 (en) Method of forming monolithic CMOS-MEMS hybrid integrated, packaged structures
US8101458B2 (en) Method of forming monolithic CMOS-MEMS hybrid integrated, packaged structures
US8101469B2 (en) Method of forming monolithic CMOS-MEMS hybrid integrated, packaged structures
US8227285B1 (en) Method and structure of monolithetically integrated inertial sensor using IC foundry-compatible processes
US8698292B2 (en) Environment-resistant module, micropackage and methods of manufacturing same
US8569090B2 (en) Wafer level structures and methods for fabricating and packaging MEMS
US10040681B2 (en) Method and system for MEMS devices
US7247246B2 (en) Vertical integration of a MEMS structure with electronics in a hermetically sealed cavity
CN107032290B (en) Semiconductor device and method of forming the same
US7104129B2 (en) Vertically integrated MEMS structure with electronics in a hermetically sealed cavity
US6979872B2 (en) Modules integrating MEMS devices with pre-processed electronic circuitry, and methods for fabricating such modules
US7618837B2 (en) Method for fabricating high aspect ratio MEMS device with integrated circuit on the same substrate using post-CMOS process
JP2001068580A (en) Method for manufacturing wafer package
EP3155667A1 (en) Wafer scale monolithic cmos-integration of free-and non-free-standing metal- and metal alloy-based mems structures in a sealed cavity and methods of forming the same
EP1912890A2 (en) Chip scale package for a micro component
KR20090105930A (en) Encapsulation module method for production and use thereof
CN102050418B (en) Three-dimensional integrated structure and production methods thereof
US10266392B2 (en) Environment-resistant module, micropackage and methods of manufacturing same
US20140264647A1 (en) Method of forming monolithic cmos-mems hybrid integrated, packaged structures
Lee et al. Planarization techniques for vertically integrated metallic MEMS on silicon foundry circuits
JP4385145B2 (en) Device equipment
WO2007089204A1 (en) Mems components and method for manufacturing same
Lee et al. Introduction to MEMS packaging
TW201118034A (en) MEMS integrated chip and method for making same
Wijesundara et al. Packaging

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 10794809

Country of ref document: EP

Kind code of ref document: A2

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 10794809

Country of ref document: EP

Kind code of ref document: A2