WO2011003057A3 - Method of forming monolithic cmos-mems hybrid integrated, packaged structures - Google Patents
Method of forming monolithic cmos-mems hybrid integrated, packaged structures Download PDFInfo
- Publication number
- WO2011003057A3 WO2011003057A3 PCT/US2010/040890 US2010040890W WO2011003057A3 WO 2011003057 A3 WO2011003057 A3 WO 2011003057A3 US 2010040890 W US2010040890 W US 2010040890W WO 2011003057 A3 WO2011003057 A3 WO 2011003057A3
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- WIPO (PCT)
- Prior art keywords
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- semiconductor substrate
- forming
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
- B81C1/0023—Packaging together an electronic processing unit die and a micromechanical structure die
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
- B81C1/00238—Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/24227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
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- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
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- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/14—Integrated circuits
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
Abstract
A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contact area; applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one another contact area on the chip; applying a second insulating layer overlying the metallization layer on the at least one chip; applying at least one interfacial layer; applying at least one rigid substrate overlying the interfacial layer; and applying at least one secondary protective layer overlying the rigid substrate.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/497,107 US7989248B2 (en) | 2009-07-02 | 2009-07-02 | Method of forming monolithic CMOS-MEMS hybrid integrated, packaged structures |
US12/497,107 | 2009-07-02 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2011003057A2 WO2011003057A2 (en) | 2011-01-06 |
WO2011003057A3 true WO2011003057A3 (en) | 2011-04-14 |
Family
ID=43411773
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2010/040890 WO2011003057A2 (en) | 2009-07-02 | 2010-07-02 | Method of forming monolithic cmos-mems hybrid integrated, packaged structures |
Country Status (2)
Country | Link |
---|---|
US (1) | US7989248B2 (en) |
WO (1) | WO2011003057A2 (en) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8878312B2 (en) * | 2011-03-01 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical bypass structure for MEMS device |
US9254992B2 (en) * | 2012-07-27 | 2016-02-09 | Tao Ju | Method of making a MEMS gyroscope having a magnetic source and a magnetic sensing mechanism |
ITTO20120827A1 (en) * | 2012-09-24 | 2014-03-25 | St Microelectronics Srl | INSULATION AT SLICE LEVEL OF AN INTEGRATED MEMS DEVICE AND ITS MANUFACTURING PROCEDURE |
KR102007258B1 (en) * | 2012-11-21 | 2019-08-05 | 삼성전자주식회사 | Method of fabricating optoelectronic substrate |
FR3008690B1 (en) * | 2013-07-22 | 2016-12-23 | Commissariat Energie Atomique | DEVICE COMPRISING A FLUID CHANNEL PROVIDED WITH AT LEAST ONE MICRO OR NANOELECTRONIC SYSTEM AND METHOD OF MAKING SUCH A DEVICE |
US9379069B2 (en) * | 2014-04-25 | 2016-06-28 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor arrangement comprising transmission line surrounded by magnetic layer |
EP3920200A1 (en) * | 2014-05-05 | 2021-12-08 | 3D Glass Solutions, Inc. | 2d and 3d inductors antenna and transformers fabricating photoactive substrates |
EP3226822A4 (en) | 2014-12-05 | 2018-08-22 | Egg Medical, Inc. | A multimodality medical procedure mattress-based device |
US10070533B2 (en) | 2015-09-30 | 2018-09-04 | 3D Glass Solutions, Inc. | Photo-definable glass with integrated electronics and ground plane |
AU2017223993B2 (en) | 2016-02-25 | 2019-07-04 | 3D Glass Solutions, Inc. | 3D capacitor and capacitor array fabricating photoactive substrates |
WO2017177171A1 (en) | 2016-04-08 | 2017-10-12 | 3D Glass Solutions, Inc. | Methods of fabricating photosensitive substrates suitable for optical coupler |
US10556791B2 (en) * | 2016-07-19 | 2020-02-11 | King Abdulaziz City For Science And Technology | CMOS compatible capacitive absolute pressure sensors |
JP7150342B2 (en) | 2017-04-28 | 2022-10-11 | スリーディー グラス ソリューションズ,インク | RF circulator |
WO2019010045A1 (en) | 2017-07-07 | 2019-01-10 | 3D Glass Solutions, Inc. | 2d and 3d rf lumped element devices for rf system in a package photoactive glass substrates |
US10312185B2 (en) * | 2017-10-05 | 2019-06-04 | Texas Instrument Incorporated | Inductively coupled microelectromechanical system resonator |
EP3724946A4 (en) | 2017-12-15 | 2020-12-30 | 3D Glass Solutions, Inc. | Coupled transmission line resonate rf filter |
JP7226832B2 (en) | 2018-01-04 | 2023-02-21 | スリーディー グラス ソリューションズ,インク | Impedance-matching conductive structures for high-efficiency RF circuits |
EP3643148A4 (en) | 2018-04-10 | 2021-03-31 | 3D Glass Solutions, Inc. | Rf integrated power condition capacitor |
US10903545B2 (en) | 2018-05-29 | 2021-01-26 | 3D Glass Solutions, Inc. | Method of making a mechanically stabilized radio frequency transmission line device |
US11139582B2 (en) | 2018-09-17 | 2021-10-05 | 3D Glass Solutions, Inc. | High efficiency compact slotted antenna with a ground plane |
CA3107812C (en) | 2018-12-28 | 2023-06-27 | 3D Glass Solutions, Inc. | Annular capacitor rf, microwave and mm wave systems |
US11594457B2 (en) | 2018-12-28 | 2023-02-28 | 3D Glass Solutions, Inc. | Heterogenous integration for RF, microwave and MM wave systems in photoactive glass substrates |
US11373908B2 (en) | 2019-04-18 | 2022-06-28 | 3D Glass Solutions, Inc. | High efficiency die dicing and release |
EP4121988A4 (en) | 2020-04-17 | 2023-08-30 | 3D Glass Solutions, Inc. | Broadband induction |
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US6012336A (en) * | 1995-09-06 | 2000-01-11 | Sandia Corporation | Capacitance pressure sensor |
JP2001185635A (en) * | 1999-10-15 | 2001-07-06 | Lucent Technol Inc | Package having cavity for housing mems |
EP1808405A2 (en) * | 2006-01-13 | 2007-07-18 | Honeywell International Inc. | Integrated package for MEMS die and IC chip |
US20070224832A1 (en) * | 2006-03-21 | 2007-09-27 | Peter Zurcher | Method for forming and sealing a cavity for an integrated MEMS device |
KR20090031360A (en) * | 2006-07-15 | 2009-03-25 | 쇼오트 아게 | Method for encasing electronic components and integrated circuits |
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US5717631A (en) | 1995-07-21 | 1998-02-10 | Carnegie Mellon University | Microelectromechanical structure and process of making same |
JP3214470B2 (en) | 1998-11-16 | 2001-10-02 | 日本電気株式会社 | Multi-chip module and manufacturing method thereof |
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FR2932790B1 (en) * | 2008-06-23 | 2010-08-20 | Commissariat Energie Atomique | METHOD FOR MANUFACTURING AN ELECTROMECHANICAL DEVICE COMPRISING AT LEAST ONE ACTIVE ELEMENT |
-
2009
- 2009-07-02 US US12/497,107 patent/US7989248B2/en not_active Expired - Fee Related
-
2010
- 2010-07-02 WO PCT/US2010/040890 patent/WO2011003057A2/en active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6012336A (en) * | 1995-09-06 | 2000-01-11 | Sandia Corporation | Capacitance pressure sensor |
JP2001185635A (en) * | 1999-10-15 | 2001-07-06 | Lucent Technol Inc | Package having cavity for housing mems |
EP1808405A2 (en) * | 2006-01-13 | 2007-07-18 | Honeywell International Inc. | Integrated package for MEMS die and IC chip |
US20070224832A1 (en) * | 2006-03-21 | 2007-09-27 | Peter Zurcher | Method for forming and sealing a cavity for an integrated MEMS device |
KR20090031360A (en) * | 2006-07-15 | 2009-03-25 | 쇼오트 아게 | Method for encasing electronic components and integrated circuits |
Also Published As
Publication number | Publication date |
---|---|
US20110003422A1 (en) | 2011-01-06 |
US7989248B2 (en) | 2011-08-02 |
WO2011003057A2 (en) | 2011-01-06 |
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