WO2011017202A3 - Packaged semiconductor device for high performance memory and logic - Google Patents

Packaged semiconductor device for high performance memory and logic Download PDF

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Publication number
WO2011017202A3
WO2011017202A3 PCT/US2010/043788 US2010043788W WO2011017202A3 WO 2011017202 A3 WO2011017202 A3 WO 2011017202A3 US 2010043788 W US2010043788 W US 2010043788W WO 2011017202 A3 WO2011017202 A3 WO 2011017202A3
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
packaged semiconductor
face
logic
high performance
Prior art date
Application number
PCT/US2010/043788
Other languages
French (fr)
Other versions
WO2011017202A2 (en
Inventor
Ming Li
Original Assignee
Rambus Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rambus Inc. filed Critical Rambus Inc.
Priority to US13/387,702 priority Critical patent/US9466561B2/en
Priority to EP10806953A priority patent/EP2462614A4/en
Priority to JP2012523664A priority patent/JP2013501380A/en
Publication of WO2011017202A2 publication Critical patent/WO2011017202A2/en
Publication of WO2011017202A3 publication Critical patent/WO2011017202A3/en

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Abstract

A packaged semiconductor device is disclosed. The device comprises a substrate having multiple layers between first and second oppositely disposed faces, and a cavity with an opening at the first face to nest at least one integrated circuit memory device. Logic circuitry is disposed on the second face and includes contacts for electrically coupling to the stacked integrated circuit memory devices. The logic circuitry is coupled to electrical contacts formed on the first face through first electrical paths formed in the multiple layers of the substrate, the first electrical paths including conductive traces and vias.
PCT/US2010/043788 2009-08-06 2010-07-29 Packaged semiconductor device for high performance memory and logic WO2011017202A2 (en)

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US13/387,702 US9466561B2 (en) 2009-08-06 2010-07-29 Packaged semiconductor device for high performance memory and logic
EP10806953A EP2462614A4 (en) 2009-08-06 2010-07-29 Packaged semiconductor device for high performance memory and logic
JP2012523664A JP2013501380A (en) 2009-08-06 2010-07-29 High performance memory and logic package semiconductor devices

Applications Claiming Priority (2)

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US23197309P 2009-08-06 2009-08-06
US61/231,973 2009-08-06

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WO2011017202A3 true WO2011017202A3 (en) 2011-05-05

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EP2462614A2 (en) 2012-06-13
EP2462614A4 (en) 2013-01-16
US20120187578A1 (en) 2012-07-26
WO2011017202A2 (en) 2011-02-10
JP2013501380A (en) 2013-01-10
US9466561B2 (en) 2016-10-11

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